arch/arm64/include/asm/cachetype.h

   1 /*
   2  * Copyright (C) 2012 ARM Ltd.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  *
  13  * You should have received a copy of the GNU General Public License
  14  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  15  */
  16 #ifndef __ASM_CACHETYPE_H
  17 #define __ASM_CACHETYPE_H
  18
  19 #include <asm/cputype.h>
  20
  21 #define CTR_L1IP_SHIFT          14
  22 #define CTR_L1IP_MASK           3
  23 #define CTR_CWG_SHIFT           24
  24 #define CTR_CWG_MASK            15
  25
  26 #define ICACHE_POLICY_RESERVED  0
  27 #define ICACHE_POLICY_AIVIVT    1
  28 #define ICACHE_POLICY_VIPT      2
  29 #define ICACHE_POLICY_PIPT      3
  30
  31 #ifndef __ASSEMBLY__
  32
  33 static inline u32 icache_policy(void)
  34 {
  35         return (read_cpuid_cachetype() >> CTR_L1IP_SHIFT) & CTR_L1IP_MASK;
  36 }
  37
  38 /*
  39  * Whilst the D-side always behaves as PIPT on AArch64, aliasing is
  40  * permitted in the I-cache.
  41  */
  42 static inline int icache_is_aliasing(void)
  43 {
  44         return icache_policy() != ICACHE_POLICY_PIPT;
  45 }
  46
  47 static inline int icache_is_aivivt(void)
  48 {
  49         return icache_policy() == ICACHE_POLICY_AIVIVT;
  50 }
  51
  52 static inline u32 cache_type_cwg(void)
  53 {
  54         return (read_cpuid_cachetype() >> CTR_CWG_SHIFT) & CTR_CWG_MASK;
  55 }
  56
  57 #endif  /* __ASSEMBLY__ */
  58
  59 #endif  /* __ASM_CACHETYPE_H */