arch/arm64/include/asm/cachetype.h

   1 /*
   2  * Copyright (C) 2012 ARM Ltd.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  *
  13  * You should have received a copy of the GNU General Public License
  14  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  15  */
  16 #ifndef __ASM_CACHETYPE_H
  17 #define __ASM_CACHETYPE_H
  18
  19 #include <asm/cputype.h>
  20
  21 #define CTR_L1IP_SHIFT          14
  22 #define CTR_L1IP_MASK           3
  23 #define CTR_CWG_SHIFT           24
  24 #define CTR_CWG_MASK            15
  25
  26 #define ICACHE_POLICY_RESERVED  0
  27 #define ICACHE_POLICY_AIVIVT    1
  28 #define ICACHE_POLICY_VIPT      2
  29 #define ICACHE_POLICY_PIPT      3
  30
  31 #ifndef __ASSEMBLY__
  32
  33 #include <linux/bitops.h>
  34
  35 #define CTR_L1IP(ctr)   (((ctr) >> CTR_L1IP_SHIFT) & CTR_L1IP_MASK)
  36
  37 #define ICACHEF_ALIASING        BIT(0)
  38 #define ICACHEF_AIVIVT          BIT(1)
  39
  40 extern unsigned long __icache_flags;
  41
  42 /*
  43  * Whilst the D-side always behaves as PIPT on AArch64, aliasing is
  44  * permitted in the I-cache.
  45  */
  46 static inline int icache_is_aliasing(void)
  47 {
  48         return test_bit(ICACHEF_ALIASING, &__icache_flags);
  49 }
  50
  51 static inline int icache_is_aivivt(void)
  52 {
  53         return test_bit(ICACHEF_AIVIVT, &__icache_flags);
  54 }
  55
  56 static inline u32 cache_type_cwg(void)
  57 {
  58         return (read_cpuid_cachetype() >> CTR_CWG_SHIFT) & CTR_CWG_MASK;
  59 }
  60
  61 #endif  /* __ASSEMBLY__ */
  62
  63 #endif  /* __ASM_CACHETYPE_H */