arch/arm64/include/asm/cpufeature.h

   1 /*
   2  * Copyright (C) 2014 Linaro Ltd. <ard.biesheuvel@linaro.org>
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8
   9 #ifndef __ASM_CPUFEATURE_H
  10 #define __ASM_CPUFEATURE_H
  11
  12 #include <linux/jump_label.h>
  13
  14 #include <asm/hwcap.h>
  15 #include <asm/sysreg.h>
  16
  17 /*
  18  * In the arm64 world (as in the ARM world), elf_hwcap is used both internally
  19  * in the kernel and for user space to keep track of which optional features
  20  * are supported by the current system. So let's map feature 'x' to HWCAP_x.
  21  * Note that HWCAP_x constants are bit fields so we need to take the log.
  22  */
  23
  24 #define MAX_CPU_FEATURES        (8 * sizeof(elf_hwcap))
  25 #define cpu_feature(x)          ilog2(HWCAP_ ## x)
  26
  27 #define ARM64_WORKAROUND_CLEAN_CACHE            0
  28 #define ARM64_WORKAROUND_DEVICE_LOAD_ACQUIRE    1
  29 #define ARM64_WORKAROUND_845719                 2
  30 #define ARM64_HAS_SYSREG_GIC_CPUIF              3
  31 #define ARM64_HAS_PAN                           4
  32 #define ARM64_HAS_LSE_ATOMICS                   5
  33 #define ARM64_WORKAROUND_CAVIUM_23154           6
  34 #define ARM64_WORKAROUND_834220                 7
  35 #define ARM64_HAS_NO_HW_PREFETCH                8
  36 #define ARM64_HAS_UAO                           9
  37 #define ARM64_ALT_PAN_NOT_UAO                   10
  38 #define ARM64_HAS_VIRT_HOST_EXTN                11
  39 #define ARM64_WORKAROUND_CAVIUM_27456           12
  40 #define ARM64_HAS_32BIT_EL0                     13
  41 #define ARM64_HYP_OFFSET_LOW                    14
  42
  43 #define ARM64_NCAPS                             15
  44
  45 #ifndef __ASSEMBLY__
  46
  47 #include <linux/kernel.h>
  48
  49 /* CPU feature register tracking */
  50 enum ftr_type {
  51         FTR_EXACT,      /* Use a predefined safe value */
  52         FTR_LOWER_SAFE, /* Smaller value is safe */
  53         FTR_HIGHER_SAFE,/* Bigger value is safe */
  54 };
  55
  56 #define FTR_STRICT      true    /* SANITY check strict matching required */
  57 #define FTR_NONSTRICT   false   /* SANITY check ignored */
  58
  59 #define FTR_SIGNED      true    /* Value should be treated as signed */
  60 #define FTR_UNSIGNED    false   /* Value should be treated as unsigned */
  61
  62 struct arm64_ftr_bits {
  63         bool            sign;   /* Value is signed ? */
  64         bool            strict; /* CPU Sanity check: strict matching required ? */
  65         enum ftr_type   type;
  66         u8              shift;
  67         u8              width;
  68         s64             safe_val; /* safe value for discrete features */
  69 };
  70
  71 /*
  72  * @arm64_ftr_reg - Feature register
  73  * @strict_mask         Bits which should match across all CPUs for sanity.
  74  * @sys_val             Safe value across the CPUs (system view)
  75  */
  76 struct arm64_ftr_reg {
  77         const char                      *name;
  78         u64                             strict_mask;
  79         u64                             sys_val;
  80         const struct arm64_ftr_bits     *ftr_bits;
  81 };
  82
  83 extern struct arm64_ftr_reg arm64_ftr_reg_ctrel0;
  84
  85 /* scope of capability check */
  86 enum {
  87         SCOPE_SYSTEM,
  88         SCOPE_LOCAL_CPU,
  89 };
  90
  91 struct arm64_cpu_capabilities {
  92         const char *desc;
  93         u16 capability;
  94         int def_scope;                  /* default scope */
  95         bool (*matches)(const struct arm64_cpu_capabilities *caps, int scope);
  96         void (*enable)(void *);         /* Called on all active CPUs */
  97         union {
  98                 struct {        /* To be used for erratum handling only */
  99                         u32 midr_model;
 100                         u32 midr_range_min, midr_range_max;
 101                 };
 102
 103                 struct {        /* Feature register checking */
 104                         u32 sys_reg;
 105                         u8 field_pos;
 106                         u8 min_field_value;
 107                         u8 hwcap_type;
 108                         bool sign;
 109                         unsigned long hwcap;
 110                 };
 111         };
 112 };
 113
 114 extern DECLARE_BITMAP(cpu_hwcaps, ARM64_NCAPS);
 115 extern struct static_key_false cpu_hwcap_keys[ARM64_NCAPS];
 116
 117 bool this_cpu_has_cap(unsigned int cap);
 118
 119 static inline bool cpu_have_feature(unsigned int num)
 120 {
 121         return elf_hwcap & (1UL << num);
 122 }
 123
 124 static inline bool cpus_have_cap(unsigned int num)
 125 {
 126         if (num >= ARM64_NCAPS)
 127                 return false;
 128         if (__builtin_constant_p(num))
 129                 return static_branch_unlikely(&cpu_hwcap_keys[num]);
 130         else
 131                 return test_bit(num, cpu_hwcaps);
 132 }
 133
 134 static inline void cpus_set_cap(unsigned int num)
 135 {
 136         if (num >= ARM64_NCAPS) {
 137                 pr_warn("Attempt to set an illegal CPU capability (%d >= %d)\n",
 138                         num, ARM64_NCAPS);
 139         } else {
 140                 __set_bit(num, cpu_hwcaps);
 141                 static_branch_enable(&cpu_hwcap_keys[num]);
 142         }
 143 }
 144
 145 static inline int __attribute_const__
 146 cpuid_feature_extract_signed_field_width(u64 features, int field, int width)
 147 {
 148         return (s64)(features << (64 - width - field)) >> (64 - width);
 149 }
 150
 151 static inline int __attribute_const__
 152 cpuid_feature_extract_signed_field(u64 features, int field)
 153 {
 154         return cpuid_feature_extract_signed_field_width(features, field, 4);
 155 }
 156
 157 static inline unsigned int __attribute_const__
 158 cpuid_feature_extract_unsigned_field_width(u64 features, int field, int width)
 159 {
 160         return (u64)(features << (64 - width - field)) >> (64 - width);
 161 }
 162
 163 static inline unsigned int __attribute_const__
 164 cpuid_feature_extract_unsigned_field(u64 features, int field)
 165 {
 166         return cpuid_feature_extract_unsigned_field_width(features, field, 4);
 167 }
 168
 169 static inline u64 arm64_ftr_mask(const struct arm64_ftr_bits *ftrp)
 170 {
 171         return (u64)GENMASK(ftrp->shift + ftrp->width - 1, ftrp->shift);
 172 }
 173
 174 static inline int __attribute_const__
 175 cpuid_feature_extract_field(u64 features, int field, bool sign)
 176 {
 177         return (sign) ?
 178                 cpuid_feature_extract_signed_field(features, field) :
 179                 cpuid_feature_extract_unsigned_field(features, field);
 180 }
 181
 182 static inline s64 arm64_ftr_value(const struct arm64_ftr_bits *ftrp, u64 val)
 183 {
 184         return (s64)cpuid_feature_extract_field(val, ftrp->shift, ftrp->sign);
 185 }
 186
 187 static inline bool id_aa64mmfr0_mixed_endian_el0(u64 mmfr0)
 188 {
 189         return cpuid_feature_extract_unsigned_field(mmfr0, ID_AA64MMFR0_BIGENDEL_SHIFT) == 0x1 ||
 190                 cpuid_feature_extract_unsigned_field(mmfr0, ID_AA64MMFR0_BIGENDEL0_SHIFT) == 0x1;
 191 }
 192
 193 static inline bool id_aa64pfr0_32bit_el0(u64 pfr0)
 194 {
 195         u32 val = cpuid_feature_extract_unsigned_field(pfr0, ID_AA64PFR0_EL0_SHIFT);
 196
 197         return val == ID_AA64PFR0_EL0_32BIT_64BIT;
 198 }
 199
 200 void __init setup_cpu_features(void);
 201
 202 void update_cpu_capabilities(const struct arm64_cpu_capabilities *caps,
 203                             const char *info);
 204 void enable_cpu_capabilities(const struct arm64_cpu_capabilities *caps);
 205 void check_local_cpu_errata(void);
 206 void __init enable_errata_workarounds(void);
 207
 208 void verify_local_cpu_errata(void);
 209 void verify_local_cpu_capabilities(void);
 210
 211 u64 read_system_reg(u32 id);
 212
 213 static inline bool cpu_supports_mixed_endian_el0(void)
 214 {
 215         return id_aa64mmfr0_mixed_endian_el0(read_cpuid(ID_AA64MMFR0_EL1));
 216 }
 217
 218 static inline bool system_supports_32bit_el0(void)
 219 {
 220         return cpus_have_cap(ARM64_HAS_32BIT_EL0);
 221 }
 222
 223 static inline bool system_supports_mixed_endian_el0(void)
 224 {
 225         return id_aa64mmfr0_mixed_endian_el0(read_system_reg(SYS_ID_AA64MMFR0_EL1));
 226 }
 227
 228 #endif /* __ASSEMBLY__ */
 229
 230 #endif