arch/arm64/include/asm/io.h

   1 /*
   2  * Based on arch/arm/include/asm/io.h
   3  *
   4  * Copyright (C) 1996-2000 Russell King
   5  * Copyright (C) 2012 ARM Ltd.
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  18  */
  19 #ifndef __ASM_IO_H
  20 #define __ASM_IO_H
  21
  22 #ifdef __KERNEL__
  23
  24 #include <linux/types.h>
  25 #include <linux/blk_types.h>
  26
  27 #include <asm/byteorder.h>
  28 #include <asm/barrier.h>
  29 #include <asm/pgtable.h>
  30
  31 #include <xen/xen.h>
  32
  33 /*
  34  * Generic IO read/write.  These perform native-endian accesses.
  35  */
  36 static inline void __raw_writeb(u8 val, volatile void __iomem *addr)
  37 {
  38         asm volatile("strb %w0, [%1]" : : "r" (val), "r" (addr));
  39 }
  40
  41 static inline void __raw_writew(u16 val, volatile void __iomem *addr)
  42 {
  43         asm volatile("strh %w0, [%1]" : : "r" (val), "r" (addr));
  44 }
  45
  46 static inline void __raw_writel(u32 val, volatile void __iomem *addr)
  47 {
  48         asm volatile("str %w0, [%1]" : : "r" (val), "r" (addr));
  49 }
  50
  51 static inline void __raw_writeq(u64 val, volatile void __iomem *addr)
  52 {
  53         asm volatile("str %0, [%1]" : : "r" (val), "r" (addr));
  54 }
  55
  56 static inline u8 __raw_readb(const volatile void __iomem *addr)
  57 {
  58         u8 val;
  59         asm volatile("ldrb %w0, [%1]" : "=r" (val) : "r" (addr));
  60         return val;
  61 }
  62
  63 static inline u16 __raw_readw(const volatile void __iomem *addr)
  64 {
  65         u16 val;
  66         asm volatile("ldrh %w0, [%1]" : "=r" (val) : "r" (addr));
  67         return val;
  68 }
  69
  70 static inline u32 __raw_readl(const volatile void __iomem *addr)
  71 {
  72         u32 val;
  73         asm volatile("ldr %w0, [%1]" : "=r" (val) : "r" (addr));
  74         return val;
  75 }
  76
  77 static inline u64 __raw_readq(const volatile void __iomem *addr)
  78 {
  79         u64 val;
  80         asm volatile("ldr %0, [%1]" : "=r" (val) : "r" (addr));
  81         return val;
  82 }
  83
  84 /* IO barriers */
  85 #define __iormb()               rmb()
  86 #define __iowmb()               wmb()
  87
  88 #define mmiowb()                do { } while (0)
  89
  90 /*
  91  * Relaxed I/O memory access primitives. These follow the Device memory
  92  * ordering rules but do not guarantee any ordering relative to Normal memory
  93  * accesses.
  94  */
  95 #define readb_relaxed(c)        ({ u8  __v = __raw_readb(c); __v; })
  96 #define readw_relaxed(c)        ({ u16 __v = le16_to_cpu((__force __le16)__raw_readw(c)); __v; })
  97 #define readl_relaxed(c)        ({ u32 __v = le32_to_cpu((__force __le32)__raw_readl(c)); __v; })
  98 #define readq_relaxed(c)        ({ u64 __v = le64_to_cpu((__force __le64)__raw_readq(c)); __v; })
  99
 100 #define writeb_relaxed(v,c)     ((void)__raw_writeb((v),(c)))
 101 #define writew_relaxed(v,c)     ((void)__raw_writew((__force u16)cpu_to_le16(v),(c)))
 102 #define writel_relaxed(v,c)     ((void)__raw_writel((__force u32)cpu_to_le32(v),(c)))
 103 #define writeq_relaxed(v,c)     ((void)__raw_writeq((__force u64)cpu_to_le64(v),(c)))
 104
 105 /*
 106  * I/O memory access primitives. Reads are ordered relative to any
 107  * following Normal memory access. Writes are ordered relative to any prior
 108  * Normal memory access.
 109  */
 110 #define readb(c)                ({ u8  __v = readb_relaxed(c); __iormb(); __v; })
 111 #define readw(c)                ({ u16 __v = readw_relaxed(c); __iormb(); __v; })
 112 #define readl(c)                ({ u32 __v = readl_relaxed(c); __iormb(); __v; })
 113 #define readq(c)                ({ u64 __v = readq_relaxed(c); __iormb(); __v; })
 114
 115 #define writeb(v,c)             ({ __iowmb(); writeb_relaxed((v),(c)); })
 116 #define writew(v,c)             ({ __iowmb(); writew_relaxed((v),(c)); })
 117 #define writel(v,c)             ({ __iowmb(); writel_relaxed((v),(c)); })
 118 #define writeq(v,c)             ({ __iowmb(); writeq_relaxed((v),(c)); })
 119
 120 /*
 121  *  I/O port access primitives.
 122  */
 123 #define IO_SPACE_LIMIT          0xffff
 124 #define PCI_IOBASE              ((void __iomem *)(MODULES_VADDR - SZ_32M))
 125
 126 static inline u8 inb(unsigned long addr)
 127 {
 128         return readb(addr + PCI_IOBASE);
 129 }
 130
 131 static inline u16 inw(unsigned long addr)
 132 {
 133         return readw(addr + PCI_IOBASE);
 134 }
 135
 136 static inline u32 inl(unsigned long addr)
 137 {
 138         return readl(addr + PCI_IOBASE);
 139 }
 140
 141 static inline void outb(u8 b, unsigned long addr)
 142 {
 143         writeb(b, addr + PCI_IOBASE);
 144 }
 145
 146 static inline void outw(u16 b, unsigned long addr)
 147 {
 148         writew(b, addr + PCI_IOBASE);
 149 }
 150
 151 static inline void outl(u32 b, unsigned long addr)
 152 {
 153         writel(b, addr + PCI_IOBASE);
 154 }
 155
 156 #define inb_p(addr)     inb(addr)
 157 #define inw_p(addr)     inw(addr)
 158 #define inl_p(addr)     inl(addr)
 159
 160 #define outb_p(x, addr) outb((x), (addr))
 161 #define outw_p(x, addr) outw((x), (addr))
 162 #define outl_p(x, addr) outl((x), (addr))
 163
 164 static inline void insb(unsigned long addr, void *buffer, int count)
 165 {
 166         u8 *buf = buffer;
 167         while (count--)
 168                 *buf++ = __raw_readb(addr + PCI_IOBASE);
 169 }
 170
 171 static inline void insw(unsigned long addr, void *buffer, int count)
 172 {
 173         u16 *buf = buffer;
 174         while (count--)
 175                 *buf++ = __raw_readw(addr + PCI_IOBASE);
 176 }
 177
 178 static inline void insl(unsigned long addr, void *buffer, int count)
 179 {
 180         u32 *buf = buffer;
 181         while (count--)
 182                 *buf++ = __raw_readl(addr + PCI_IOBASE);
 183 }
 184
 185 static inline void outsb(unsigned long addr, const void *buffer, int count)
 186 {
 187         const u8 *buf = buffer;
 188         while (count--)
 189                 __raw_writeb(*buf++, addr + PCI_IOBASE);
 190 }
 191
 192 static inline void outsw(unsigned long addr, const void *buffer, int count)
 193 {
 194         const u16 *buf = buffer;
 195         while (count--)
 196                 __raw_writew(*buf++, addr + PCI_IOBASE);
 197 }
 198
 199 static inline void outsl(unsigned long addr, const void *buffer, int count)
 200 {
 201         const u32 *buf = buffer;
 202         while (count--)
 203                 __raw_writel(*buf++, addr + PCI_IOBASE);
 204 }
 205
 206 #define insb_p(port,to,len)     insb(port,to,len)
 207 #define insw_p(port,to,len)     insw(port,to,len)
 208 #define insl_p(port,to,len)     insl(port,to,len)
 209
 210 #define outsb_p(port,from,len)  outsb(port,from,len)
 211 #define outsw_p(port,from,len)  outsw(port,from,len)
 212 #define outsl_p(port,from,len)  outsl(port,from,len)
 213
 214 /*
 215  * String version of I/O memory access operations.
 216  */
 217 extern void __memcpy_fromio(void *, const volatile void __iomem *, size_t);
 218 extern void __memcpy_toio(volatile void __iomem *, const void *, size_t);
 219 extern void __memset_io(volatile void __iomem *, int, size_t);
 220
 221 #define memset_io(c,v,l)        __memset_io((c),(v),(l))
 222 #define memcpy_fromio(a,c,l)    __memcpy_fromio((a),(c),(l))
 223 #define memcpy_toio(c,a,l)      __memcpy_toio((c),(a),(l))
 224
 225 /*
 226  * I/O memory mapping functions.
 227  */
 228 extern void __iomem *__ioremap(phys_addr_t phys_addr, size_t size, pgprot_t prot);
 229 extern void __iounmap(volatile void __iomem *addr);
 230 extern void __iomem *ioremap_cache(phys_addr_t phys_addr, size_t size);
 231
 232 #define PROT_DEFAULT            (PTE_TYPE_PAGE | PTE_AF | PTE_DIRTY)
 233 #define PROT_DEVICE_nGnRE       (PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_ATTRINDX(MT_DEVICE_nGnRE))
 234 #define PROT_NORMAL_NC          (PROT_DEFAULT | PTE_ATTRINDX(MT_NORMAL_NC))
 235 #define PROT_NORMAL             (PROT_DEFAULT | PTE_ATTRINDX(MT_NORMAL))
 236
 237 #define ioremap(addr, size)             __ioremap((addr), (size), __pgprot(PROT_DEVICE_nGnRE))
 238 #define ioremap_nocache(addr, size)     __ioremap((addr), (size), __pgprot(PROT_DEVICE_nGnRE))
 239 #define ioremap_wc(addr, size)          __ioremap((addr), (size), __pgprot(PROT_NORMAL_NC))
 240 #define iounmap                         __iounmap
 241
 242 #define PROT_SECT_DEFAULT       (PMD_TYPE_SECT | PMD_SECT_AF)
 243 #define PROT_SECT_DEVICE_nGnRE  (PROT_SECT_DEFAULT | PTE_PXN | PTE_UXN | PMD_ATTRINDX(MT_DEVICE_nGnRE))
 244
 245 #define ARCH_HAS_IOREMAP_WC
 246 #include <asm-generic/iomap.h>
 247
 248 /*
 249  * More restrictive address range checking than the default implementation
 250  * (PHYS_OFFSET and PHYS_MASK taken into account).
 251  */
 252 #define ARCH_HAS_VALID_PHYS_ADDR_RANGE
 253 extern int valid_phys_addr_range(unsigned long addr, size_t size);
 254 extern int valid_mmap_phys_addr_range(unsigned long pfn, size_t size);
 255
 256 extern int devmem_is_allowed(unsigned long pfn);
 257
 258 /*
 259  * Convert a physical pointer to a virtual kernel pointer for /dev/mem
 260  * access
 261  */
 262 #define xlate_dev_mem_ptr(p)    __va(p)
 263
 264 /*
 265  * Convert a virtual cached pointer to an uncached pointer
 266  */
 267 #define xlate_dev_kmem_ptr(p)   p
 268
 269 struct bio_vec;
 270 extern bool xen_biovec_phys_mergeable(const struct bio_vec *vec1,
 271                                       const struct bio_vec *vec2);
 272 #define BIOVEC_PHYS_MERGEABLE(vec1, vec2)                               \
 273         (__BIOVEC_PHYS_MERGEABLE(vec1, vec2) &&                         \
 274          (!xen_domain() || xen_biovec_phys_mergeable(vec1, vec2)))
 275
 276 #endif  /* __KERNEL__ */
 277 #endif  /* __ASM_IO_H */