arch/arm64/include/asm/io.h

   1 /*
   2  * Based on arch/arm/include/asm/io.h
   3  *
   4  * Copyright (C) 1996-2000 Russell King
   5  * Copyright (C) 2012 ARM Ltd.
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  18  */
  19 #ifndef __ASM_IO_H
  20 #define __ASM_IO_H
  21
  22 #ifdef __KERNEL__
  23
  24 #include <linux/types.h>
  25 #include <linux/blk_types.h>
  26
  27 #include <asm/byteorder.h>
  28 #include <asm/barrier.h>
  29 #include <asm/pgtable.h>
  30 #include <asm/early_ioremap.h>
  31 #include <asm/alternative.h>
  32 #include <asm/cpufeature.h>
  33
  34 #include <xen/xen.h>
  35
  36 /*
  37  * Generic IO read/write.  These perform native-endian accesses.
  38  */
  39 #define __raw_writeb __raw_writeb
  40 static inline void __raw_writeb(u8 val, volatile void __iomem *addr)
  41 {
  42         asm volatile("strb %w0, [%1]" : : "r" (val), "r" (addr));
  43 }
  44
  45 #define __raw_writew __raw_writew
  46 static inline void __raw_writew(u16 val, volatile void __iomem *addr)
  47 {
  48         asm volatile("strh %w0, [%1]" : : "r" (val), "r" (addr));
  49 }
  50
  51 #define __raw_writel __raw_writel
  52 static inline void __raw_writel(u32 val, volatile void __iomem *addr)
  53 {
  54         asm volatile("str %w0, [%1]" : : "r" (val), "r" (addr));
  55 }
  56
  57 #define __raw_writeq __raw_writeq
  58 static inline void __raw_writeq(u64 val, volatile void __iomem *addr)
  59 {
  60         asm volatile("str %0, [%1]" : : "r" (val), "r" (addr));
  61 }
  62
  63 #define __raw_readb __raw_readb
  64 static inline u8 __raw_readb(const volatile void __iomem *addr)
  65 {
  66         u8 val;
  67         asm volatile(ALTERNATIVE("ldrb %w0, [%1]",
  68                                  "ldarb %w0, [%1]",
  69                                  ARM64_WORKAROUND_DEVICE_LOAD_ACQUIRE)
  70                      : "=r" (val) : "r" (addr));
  71         return val;
  72 }
  73
  74 #define __raw_readw __raw_readw
  75 static inline u16 __raw_readw(const volatile void __iomem *addr)
  76 {
  77         u16 val;
  78
  79         asm volatile(ALTERNATIVE("ldrh %w0, [%1]",
  80                                  "ldarh %w0, [%1]",
  81                                  ARM64_WORKAROUND_DEVICE_LOAD_ACQUIRE)
  82                      : "=r" (val) : "r" (addr));
  83         return val;
  84 }
  85
  86 #define __raw_readl __raw_readl
  87 static inline u32 __raw_readl(const volatile void __iomem *addr)
  88 {
  89         u32 val;
  90         asm volatile(ALTERNATIVE("ldr %w0, [%1]",
  91                                  "ldar %w0, [%1]",
  92                                  ARM64_WORKAROUND_DEVICE_LOAD_ACQUIRE)
  93                      : "=r" (val) : "r" (addr));
  94         return val;
  95 }
  96
  97 #define __raw_readq __raw_readq
  98 static inline u64 __raw_readq(const volatile void __iomem *addr)
  99 {
 100         u64 val;
 101         asm volatile(ALTERNATIVE("ldr %0, [%1]",
 102                                  "ldar %0, [%1]",
 103                                  ARM64_WORKAROUND_DEVICE_LOAD_ACQUIRE)
 104                      : "=r" (val) : "r" (addr));
 105         return val;
 106 }
 107
 108 /* IO barriers */
 109 #define __iormb()               rmb()
 110 #define __iowmb()               wmb()
 111
 112 #define mmiowb()                do { } while (0)
 113
 114 /*
 115  * Relaxed I/O memory access primitives. These follow the Device memory
 116  * ordering rules but do not guarantee any ordering relative to Normal memory
 117  * accesses.
 118  */
 119 #define readb_relaxed(c)        ({ u8  __v = __raw_readb(c); __v; })
 120 #define readw_relaxed(c)        ({ u16 __v = le16_to_cpu((__force __le16)__raw_readw(c)); __v; })
 121 #define readl_relaxed(c)        ({ u32 __v = le32_to_cpu((__force __le32)__raw_readl(c)); __v; })
 122 #define readq_relaxed(c)        ({ u64 __v = le64_to_cpu((__force __le64)__raw_readq(c)); __v; })
 123
 124 #define writeb_relaxed(v,c)     ((void)__raw_writeb((v),(c)))
 125 #define writew_relaxed(v,c)     ((void)__raw_writew((__force u16)cpu_to_le16(v),(c)))
 126 #define writel_relaxed(v,c)     ((void)__raw_writel((__force u32)cpu_to_le32(v),(c)))
 127 #define writeq_relaxed(v,c)     ((void)__raw_writeq((__force u64)cpu_to_le64(v),(c)))
 128
 129 /*
 130  * I/O memory access primitives. Reads are ordered relative to any
 131  * following Normal memory access. Writes are ordered relative to any prior
 132  * Normal memory access.
 133  */
 134 #define readb(c)                ({ u8  __v = readb_relaxed(c); __iormb(); __v; })
 135 #define readw(c)                ({ u16 __v = readw_relaxed(c); __iormb(); __v; })
 136 #define readl(c)                ({ u32 __v = readl_relaxed(c); __iormb(); __v; })
 137 #define readq(c)                ({ u64 __v = readq_relaxed(c); __iormb(); __v; })
 138
 139 #define writeb(v,c)             ({ __iowmb(); writeb_relaxed((v),(c)); })
 140 #define writew(v,c)             ({ __iowmb(); writew_relaxed((v),(c)); })
 141 #define writel(v,c)             ({ __iowmb(); writel_relaxed((v),(c)); })
 142 #define writeq(v,c)             ({ __iowmb(); writeq_relaxed((v),(c)); })
 143
 144 /*
 145  *  I/O port access primitives.
 146  */
 147 #define arch_has_dev_port()     (1)
 148 #define IO_SPACE_LIMIT          (SZ_32M - 1)
 149 #define PCI_IOBASE              ((void __iomem *)(MODULES_VADDR - SZ_32M))
 150
 151 /*
 152  * String version of I/O memory access operations.
 153  */
 154 extern void __memcpy_fromio(void *, const volatile void __iomem *, size_t);
 155 extern void __memcpy_toio(volatile void __iomem *, const void *, size_t);
 156 extern void __memset_io(volatile void __iomem *, int, size_t);
 157
 158 #define memset_io(c,v,l)        __memset_io((c),(v),(l))
 159 #define memcpy_fromio(a,c,l)    __memcpy_fromio((a),(c),(l))
 160 #define memcpy_toio(c,a,l)      __memcpy_toio((c),(a),(l))
 161
 162 /*
 163  * I/O memory mapping functions.
 164  */
 165 extern void __iomem *__ioremap(phys_addr_t phys_addr, size_t size, pgprot_t prot);
 166 extern void __iounmap(volatile void __iomem *addr);
 167 extern void __iomem *ioremap_cache(phys_addr_t phys_addr, size_t size);
 168
 169 #define ioremap(addr, size)             __ioremap((addr), (size), __pgprot(PROT_DEVICE_nGnRE))
 170 #define ioremap_nocache(addr, size)     __ioremap((addr), (size), __pgprot(PROT_DEVICE_nGnRE))
 171 #define ioremap_wc(addr, size)          __ioremap((addr), (size), __pgprot(PROT_NORMAL_NC))
 172 #define iounmap                         __iounmap
 173
 174 /*
 175  * io{read,write}{16,32}be() macros
 176  */
 177 #define ioread16be(p)           ({ __u16 __v = be16_to_cpu((__force __be16)__raw_readw(p)); __iormb(); __v; })
 178 #define ioread32be(p)           ({ __u32 __v = be32_to_cpu((__force __be32)__raw_readl(p)); __iormb(); __v; })
 179
 180 #define iowrite16be(v,p)        ({ __iowmb(); __raw_writew((__force __u16)cpu_to_be16(v), p); })
 181 #define iowrite32be(v,p)        ({ __iowmb(); __raw_writel((__force __u32)cpu_to_be32(v), p); })
 182
 183 /*
 184  * Convert a physical pointer to a virtual kernel pointer for /dev/mem
 185  * access
 186  */
 187 #define xlate_dev_mem_ptr(p)    __va(p)
 188
 189 /*
 190  * Convert a virtual cached pointer to an uncached pointer
 191  */
 192 #define xlate_dev_kmem_ptr(p)   p
 193
 194 #include <asm-generic/io.h>
 195
 196 /*
 197  * More restrictive address range checking than the default implementation
 198  * (PHYS_OFFSET and PHYS_MASK taken into account).
 199  */
 200 #define ARCH_HAS_VALID_PHYS_ADDR_RANGE
 201 extern int valid_phys_addr_range(phys_addr_t addr, size_t size);
 202 extern int valid_mmap_phys_addr_range(unsigned long pfn, size_t size);
 203
 204 extern int devmem_is_allowed(unsigned long pfn);
 205
 206 struct bio_vec;
 207 extern bool xen_biovec_phys_mergeable(const struct bio_vec *vec1,
 208                                       const struct bio_vec *vec2);
 209 #define BIOVEC_PHYS_MERGEABLE(vec1, vec2)                               \
 210         (__BIOVEC_PHYS_MERGEABLE(vec1, vec2) &&                         \
 211          (!xen_domain() || xen_biovec_phys_mergeable(vec1, vec2)))
 212
 213 #endif  /* __KERNEL__ */
 214 #endif  /* __ASM_IO_H */