arch/arm64/include/asm/kvm_mmu.h

   1 /*
   2  * Copyright (C) 2012,2013 - ARM Ltd
   3  * Author: Marc Zyngier <marc.zyngier@arm.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License
  15  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  16  */
  17
  18 #ifndef __ARM64_KVM_MMU_H__
  19 #define __ARM64_KVM_MMU_H__
  20
  21 #include <asm/page.h>
  22 #include <asm/memory.h>
  23
  24 /*
  25  * As we only have the TTBR0_EL2 register, we cannot express
  26  * "negative" addresses. This makes it impossible to directly share
  27  * mappings with the kernel.
  28  *
  29  * Instead, give the HYP mode its own VA region at a fixed offset from
  30  * the kernel by just masking the top bits (which are all ones for a
  31  * kernel address).
  32  */
  33 #define HYP_PAGE_OFFSET_SHIFT   VA_BITS
  34 #define HYP_PAGE_OFFSET_MASK    ((UL(1) << HYP_PAGE_OFFSET_SHIFT) - 1)
  35 #define HYP_PAGE_OFFSET         (PAGE_OFFSET & HYP_PAGE_OFFSET_MASK)
  36
  37 /*
  38  * Our virtual mapping for the idmap-ed MMU-enable code. Must be
  39  * shared across all the page-tables. Conveniently, we use the last
  40  * possible page, where no kernel mapping will ever exist.
  41  */
  42 #define TRAMPOLINE_VA           (HYP_PAGE_OFFSET_MASK & PAGE_MASK)
  43
  44 /*
  45  * KVM_MMU_CACHE_MIN_PAGES is the number of stage2 page table translation
  46  * levels in addition to the PGD and potentially the PUD which are
  47  * pre-allocated (we pre-allocate the fake PGD and the PUD when the Stage-2
  48  * tables use one level of tables less than the kernel.
  49  */
  50 #ifdef CONFIG_ARM64_64K_PAGES
  51 #define KVM_MMU_CACHE_MIN_PAGES 1
  52 #else
  53 #define KVM_MMU_CACHE_MIN_PAGES 2
  54 #endif
  55
  56 #ifdef __ASSEMBLY__
  57
  58 /*
  59  * Convert a kernel VA into a HYP VA.
  60  * reg: VA to be converted.
  61  */
  62 .macro kern_hyp_va      reg
  63         and     \reg, \reg, #HYP_PAGE_OFFSET_MASK
  64 .endm
  65
  66 #else
  67
  68 #include <asm/pgalloc.h>
  69 #include <asm/cachetype.h>
  70 #include <asm/cacheflush.h>
  71
  72 #define KERN_TO_HYP(kva)        ((unsigned long)kva - PAGE_OFFSET + HYP_PAGE_OFFSET)
  73
  74 /*
  75  * We currently only support a 40bit IPA.
  76  */
  77 #define KVM_PHYS_SHIFT  (40)
  78 #define KVM_PHYS_SIZE   (1UL << KVM_PHYS_SHIFT)
  79 #define KVM_PHYS_MASK   (KVM_PHYS_SIZE - 1UL)
  80
  81 int create_hyp_mappings(void *from, void *to);
  82 int create_hyp_io_mappings(void *from, void *to, phys_addr_t);
  83 void free_boot_hyp_pgd(void);
  84 void free_hyp_pgds(void);
  85
  86 int kvm_alloc_stage2_pgd(struct kvm *kvm);
  87 void kvm_free_stage2_pgd(struct kvm *kvm);
  88 int kvm_phys_addr_ioremap(struct kvm *kvm, phys_addr_t guest_ipa,
  89                           phys_addr_t pa, unsigned long size, bool writable);
  90
  91 int kvm_handle_guest_abort(struct kvm_vcpu *vcpu, struct kvm_run *run);
  92
  93 void kvm_mmu_free_memory_caches(struct kvm_vcpu *vcpu);
  94
  95 phys_addr_t kvm_mmu_get_httbr(void);
  96 phys_addr_t kvm_mmu_get_boot_httbr(void);
  97 phys_addr_t kvm_get_idmap_vector(void);
  98 int kvm_mmu_init(void);
  99 void kvm_clear_hyp_idmap(void);
 100
 101 #define kvm_set_pte(ptep, pte)          set_pte(ptep, pte)
 102 #define kvm_set_pmd(pmdp, pmd)          set_pmd(pmdp, pmd)
 103
 104 static inline void kvm_clean_pgd(pgd_t *pgd) {}
 105 static inline void kvm_clean_pmd(pmd_t *pmd) {}
 106 static inline void kvm_clean_pmd_entry(pmd_t *pmd) {}
 107 static inline void kvm_clean_pte(pte_t *pte) {}
 108 static inline void kvm_clean_pte_entry(pte_t *pte) {}
 109
 110 static inline void kvm_set_s2pte_writable(pte_t *pte)
 111 {
 112         pte_val(*pte) |= PTE_S2_RDWR;
 113 }
 114
 115 static inline void kvm_set_s2pmd_writable(pmd_t *pmd)
 116 {
 117         pmd_val(*pmd) |= PMD_S2_RDWR;
 118 }
 119
 120 #define kvm_pgd_addr_end(addr, end)     pgd_addr_end(addr, end)
 121 #define kvm_pud_addr_end(addr, end)     pud_addr_end(addr, end)
 122 #define kvm_pmd_addr_end(addr, end)     pmd_addr_end(addr, end)
 123
 124 /*
 125  * In the case where PGDIR_SHIFT is larger than KVM_PHYS_SHIFT, we can address
 126  * the entire IPA input range with a single pgd entry, and we would only need
 127  * one pgd entry.  Note that in this case, the pgd is actually not used by
 128  * the MMU for Stage-2 translations, but is merely a fake pgd used as a data
 129  * structure for the kernel pgtable macros to work.
 130  */
 131 #if PGDIR_SHIFT > KVM_PHYS_SHIFT
 132 #define PTRS_PER_S2_PGD_SHIFT   0
 133 #else
 134 #define PTRS_PER_S2_PGD_SHIFT   (KVM_PHYS_SHIFT - PGDIR_SHIFT)
 135 #endif
 136 #define PTRS_PER_S2_PGD         (1 << PTRS_PER_S2_PGD_SHIFT)
 137 #define S2_PGD_ORDER            get_order(PTRS_PER_S2_PGD * sizeof(pgd_t))
 138
 139 /*
 140  * If we are concatenating first level stage-2 page tables, we would have less
 141  * than or equal to 16 pointers in the fake PGD, because that's what the
 142  * architecture allows.  In this case, (4 - CONFIG_ARM64_PGTABLE_LEVELS)
 143  * represents the first level for the host, and we add 1 to go to the next
 144  * level (which uses contatenation) for the stage-2 tables.
 145  */
 146 #if PTRS_PER_S2_PGD <= 16
 147 #define KVM_PREALLOC_LEVEL      (4 - CONFIG_ARM64_PGTABLE_LEVELS + 1)
 148 #else
 149 #define KVM_PREALLOC_LEVEL      (0)
 150 #endif
 151
 152 /**
 153  * kvm_prealloc_hwpgd - allocate inital table for VTTBR
 154  * @kvm:        The KVM struct pointer for the VM.
 155  * @pgd:        The kernel pseudo pgd
 156  *
 157  * When the kernel uses more levels of page tables than the guest, we allocate
 158  * a fake PGD and pre-populate it to point to the next-level page table, which
 159  * will be the real initial page table pointed to by the VTTBR.
 160  *
 161  * When KVM_PREALLOC_LEVEL==2, we allocate a single page for the PMD and
 162  * the kernel will use folded pud.  When KVM_PREALLOC_LEVEL==1, we
 163  * allocate 2 consecutive PUD pages.
 164  */
 165 static inline int kvm_prealloc_hwpgd(struct kvm *kvm, pgd_t *pgd)
 166 {
 167         unsigned int i;
 168         unsigned long hwpgd;
 169
 170         if (KVM_PREALLOC_LEVEL == 0)
 171                 return 0;
 172
 173         hwpgd = __get_free_pages(GFP_KERNEL | __GFP_ZERO, PTRS_PER_S2_PGD_SHIFT);
 174         if (!hwpgd)
 175                 return -ENOMEM;
 176
 177         for (i = 0; i < PTRS_PER_S2_PGD; i++) {
 178                 if (KVM_PREALLOC_LEVEL == 1)
 179                         pgd_populate(NULL, pgd + i,
 180                                      (pud_t *)hwpgd + i * PTRS_PER_PUD);
 181                 else if (KVM_PREALLOC_LEVEL == 2)
 182                         pud_populate(NULL, pud_offset(pgd, 0) + i,
 183                                      (pmd_t *)hwpgd + i * PTRS_PER_PMD);
 184         }
 185
 186         return 0;
 187 }
 188
 189 static inline void *kvm_get_hwpgd(struct kvm *kvm)
 190 {
 191         pgd_t *pgd = kvm->arch.pgd;
 192         pud_t *pud;
 193
 194         if (KVM_PREALLOC_LEVEL == 0)
 195                 return pgd;
 196
 197         pud = pud_offset(pgd, 0);
 198         if (KVM_PREALLOC_LEVEL == 1)
 199                 return pud;
 200
 201         BUG_ON(KVM_PREALLOC_LEVEL != 2);
 202         return pmd_offset(pud, 0);
 203 }
 204
 205 static inline void kvm_free_hwpgd(struct kvm *kvm)
 206 {
 207         if (KVM_PREALLOC_LEVEL > 0) {
 208                 unsigned long hwpgd = (unsigned long)kvm_get_hwpgd(kvm);
 209                 free_pages(hwpgd, PTRS_PER_S2_PGD_SHIFT);
 210         }
 211 }
 212
 213 static inline bool kvm_page_empty(void *ptr)
 214 {
 215         struct page *ptr_page = virt_to_page(ptr);
 216         return page_count(ptr_page) == 1;
 217 }
 218
 219 #define kvm_pte_table_empty(kvm, ptep) kvm_page_empty(ptep)
 220
 221 #ifdef __PAGETABLE_PMD_FOLDED
 222 #define kvm_pmd_table_empty(kvm, pmdp) (0)
 223 #else
 224 #define kvm_pmd_table_empty(kvm, pmdp) \
 225         (kvm_page_empty(pmdp) && (!(kvm) || KVM_PREALLOC_LEVEL < 2))
 226 #endif
 227
 228 #ifdef __PAGETABLE_PUD_FOLDED
 229 #define kvm_pud_table_empty(kvm, pudp) (0)
 230 #else
 231 #define kvm_pud_table_empty(kvm, pudp) \
 232         (kvm_page_empty(pudp) && (!(kvm) || KVM_PREALLOC_LEVEL < 1))
 233 #endif
 234
 235
 236 struct kvm;
 237
 238 #define kvm_flush_dcache_to_poc(a,l)    __flush_dcache_area((a), (l))
 239
 240 static inline bool vcpu_has_cache_enabled(struct kvm_vcpu *vcpu)
 241 {
 242         return (vcpu_sys_reg(vcpu, SCTLR_EL1) & 0b101) == 0b101;
 243 }
 244
 245 static inline void coherent_cache_guest_page(struct kvm_vcpu *vcpu, hva_t hva,
 246                                              unsigned long size)
 247 {
 248         if (!vcpu_has_cache_enabled(vcpu))
 249                 kvm_flush_dcache_to_poc((void *)hva, size);
 250
 251         if (!icache_is_aliasing()) {            /* PIPT */
 252                 flush_icache_range(hva, hva + size);
 253         } else if (!icache_is_aivivt()) {       /* non ASID-tagged VIVT */
 254                 /* any kind of VIPT cache */
 255                 __flush_icache_all();
 256         }
 257 }
 258
 259 #define kvm_virt_to_phys(x)             __virt_to_phys((unsigned long)(x))
 260
 261 void stage2_flush_vm(struct kvm *kvm);
 262
 263 #endif /* __ASSEMBLY__ */
 264 #endif /* __ARM64_KVM_MMU_H__ */