arch/arm64/include/asm/kvm_mmu.h

   1 /*
   2  * Copyright (C) 2012,2013 - ARM Ltd
   3  * Author: Marc Zyngier <marc.zyngier@arm.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License
  15  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  16  */
  17
  18 #ifndef __ARM64_KVM_MMU_H__
  19 #define __ARM64_KVM_MMU_H__
  20
  21 #include <asm/page.h>
  22 #include <asm/memory.h>
  23
  24 /*
  25  * As we only have the TTBR0_EL2 register, we cannot express
  26  * "negative" addresses. This makes it impossible to directly share
  27  * mappings with the kernel.
  28  *
  29  * Instead, give the HYP mode its own VA region at a fixed offset from
  30  * the kernel by just masking the top bits (which are all ones for a
  31  * kernel address).
  32  */
  33 #define HYP_PAGE_OFFSET_SHIFT   VA_BITS
  34 #define HYP_PAGE_OFFSET_MASK    ((UL(1) << HYP_PAGE_OFFSET_SHIFT) - 1)
  35 #define HYP_PAGE_OFFSET         (PAGE_OFFSET & HYP_PAGE_OFFSET_MASK)
  36
  37 /*
  38  * Our virtual mapping for the idmap-ed MMU-enable code. Must be
  39  * shared across all the page-tables. Conveniently, we use the last
  40  * possible page, where no kernel mapping will ever exist.
  41  */
  42 #define TRAMPOLINE_VA           (HYP_PAGE_OFFSET_MASK & PAGE_MASK)
  43
  44 /*
  45  * KVM_MMU_CACHE_MIN_PAGES is the number of stage2 page table translation
  46  * levels in addition to the PGD and potentially the PUD which are
  47  * pre-allocated (we pre-allocate the fake PGD and the PUD when the Stage-2
  48  * tables use one level of tables less than the kernel.
  49  */
  50 #ifdef CONFIG_ARM64_64K_PAGES
  51 #define KVM_MMU_CACHE_MIN_PAGES 1
  52 #else
  53 #define KVM_MMU_CACHE_MIN_PAGES 2
  54 #endif
  55
  56 #ifdef __ASSEMBLY__
  57
  58 /*
  59  * Convert a kernel VA into a HYP VA.
  60  * reg: VA to be converted.
  61  */
  62 .macro kern_hyp_va      reg
  63         and     \reg, \reg, #HYP_PAGE_OFFSET_MASK
  64 .endm
  65
  66 #else
  67
  68 #include <asm/pgalloc.h>
  69 #include <asm/cachetype.h>
  70 #include <asm/cacheflush.h>
  71
  72 #define KERN_TO_HYP(kva)        ((unsigned long)kva - PAGE_OFFSET + HYP_PAGE_OFFSET)
  73
  74 /*
  75  * We currently only support a 40bit IPA.
  76  */
  77 #define KVM_PHYS_SHIFT  (40)
  78 #define KVM_PHYS_SIZE   (1UL << KVM_PHYS_SHIFT)
  79 #define KVM_PHYS_MASK   (KVM_PHYS_SIZE - 1UL)
  80
  81 int create_hyp_mappings(void *from, void *to);
  82 int create_hyp_io_mappings(void *from, void *to, phys_addr_t);
  83 void free_boot_hyp_pgd(void);
  84 void free_hyp_pgds(void);
  85
  86 void stage2_unmap_vm(struct kvm *kvm);
  87 int kvm_alloc_stage2_pgd(struct kvm *kvm);
  88 void kvm_free_stage2_pgd(struct kvm *kvm);
  89 int kvm_phys_addr_ioremap(struct kvm *kvm, phys_addr_t guest_ipa,
  90                           phys_addr_t pa, unsigned long size, bool writable);
  91
  92 int kvm_handle_guest_abort(struct kvm_vcpu *vcpu, struct kvm_run *run);
  93
  94 void kvm_mmu_free_memory_caches(struct kvm_vcpu *vcpu);
  95
  96 phys_addr_t kvm_mmu_get_httbr(void);
  97 phys_addr_t kvm_mmu_get_boot_httbr(void);
  98 phys_addr_t kvm_get_idmap_vector(void);
  99 int kvm_mmu_init(void);
 100 void kvm_clear_hyp_idmap(void);
 101
 102 #define kvm_set_pte(ptep, pte)          set_pte(ptep, pte)
 103 #define kvm_set_pmd(pmdp, pmd)          set_pmd(pmdp, pmd)
 104
 105 static inline void kvm_clean_pgd(pgd_t *pgd) {}
 106 static inline void kvm_clean_pmd(pmd_t *pmd) {}
 107 static inline void kvm_clean_pmd_entry(pmd_t *pmd) {}
 108 static inline void kvm_clean_pte(pte_t *pte) {}
 109 static inline void kvm_clean_pte_entry(pte_t *pte) {}
 110
 111 static inline void kvm_set_s2pte_writable(pte_t *pte)
 112 {
 113         pte_val(*pte) |= PTE_S2_RDWR;
 114 }
 115
 116 static inline void kvm_set_s2pmd_writable(pmd_t *pmd)
 117 {
 118         pmd_val(*pmd) |= PMD_S2_RDWR;
 119 }
 120
 121 static inline void kvm_set_s2pte_readonly(pte_t *pte)
 122 {
 123         pte_val(*pte) = (pte_val(*pte) & ~PTE_S2_RDWR) | PTE_S2_RDONLY;
 124 }
 125
 126 static inline bool kvm_s2pte_readonly(pte_t *pte)
 127 {
 128         return (pte_val(*pte) & PTE_S2_RDWR) == PTE_S2_RDONLY;
 129 }
 130
 131 static inline void kvm_set_s2pmd_readonly(pmd_t *pmd)
 132 {
 133         pmd_val(*pmd) = (pmd_val(*pmd) & ~PMD_S2_RDWR) | PMD_S2_RDONLY;
 134 }
 135
 136 static inline bool kvm_s2pmd_readonly(pmd_t *pmd)
 137 {
 138         return (pmd_val(*pmd) & PMD_S2_RDWR) == PMD_S2_RDONLY;
 139 }
 140
 141
 142 #define kvm_pgd_addr_end(addr, end)     pgd_addr_end(addr, end)
 143 #define kvm_pud_addr_end(addr, end)     pud_addr_end(addr, end)
 144 #define kvm_pmd_addr_end(addr, end)     pmd_addr_end(addr, end)
 145
 146 /*
 147  * In the case where PGDIR_SHIFT is larger than KVM_PHYS_SHIFT, we can address
 148  * the entire IPA input range with a single pgd entry, and we would only need
 149  * one pgd entry.  Note that in this case, the pgd is actually not used by
 150  * the MMU for Stage-2 translations, but is merely a fake pgd used as a data
 151  * structure for the kernel pgtable macros to work.
 152  */
 153 #if PGDIR_SHIFT > KVM_PHYS_SHIFT
 154 #define PTRS_PER_S2_PGD_SHIFT   0
 155 #else
 156 #define PTRS_PER_S2_PGD_SHIFT   (KVM_PHYS_SHIFT - PGDIR_SHIFT)
 157 #endif
 158 #define PTRS_PER_S2_PGD         (1 << PTRS_PER_S2_PGD_SHIFT)
 159 #define S2_PGD_ORDER            get_order(PTRS_PER_S2_PGD * sizeof(pgd_t))
 160
 161 #define kvm_pgd_index(addr)     (((addr) >> PGDIR_SHIFT) & (PTRS_PER_S2_PGD - 1))
 162
 163 /*
 164  * If we are concatenating first level stage-2 page tables, we would have less
 165  * than or equal to 16 pointers in the fake PGD, because that's what the
 166  * architecture allows.  In this case, (4 - CONFIG_ARM64_PGTABLE_LEVELS)
 167  * represents the first level for the host, and we add 1 to go to the next
 168  * level (which uses contatenation) for the stage-2 tables.
 169  */
 170 #if PTRS_PER_S2_PGD <= 16
 171 #define KVM_PREALLOC_LEVEL      (4 - CONFIG_ARM64_PGTABLE_LEVELS + 1)
 172 #else
 173 #define KVM_PREALLOC_LEVEL      (0)
 174 #endif
 175
 176 static inline void *kvm_get_hwpgd(struct kvm *kvm)
 177 {
 178         pgd_t *pgd = kvm->arch.pgd;
 179         pud_t *pud;
 180
 181         if (KVM_PREALLOC_LEVEL == 0)
 182                 return pgd;
 183
 184         pud = pud_offset(pgd, 0);
 185         if (KVM_PREALLOC_LEVEL == 1)
 186                 return pud;
 187
 188         BUG_ON(KVM_PREALLOC_LEVEL != 2);
 189         return pmd_offset(pud, 0);
 190 }
 191
 192 static inline unsigned int kvm_get_hwpgd_size(void)
 193 {
 194         if (KVM_PREALLOC_LEVEL > 0)
 195                 return PTRS_PER_S2_PGD * PAGE_SIZE;
 196         return PTRS_PER_S2_PGD * sizeof(pgd_t);
 197 }
 198
 199 static inline bool kvm_page_empty(void *ptr)
 200 {
 201         struct page *ptr_page = virt_to_page(ptr);
 202         return page_count(ptr_page) == 1;
 203 }
 204
 205 #define kvm_pte_table_empty(kvm, ptep) kvm_page_empty(ptep)
 206
 207 #ifdef __PAGETABLE_PMD_FOLDED
 208 #define kvm_pmd_table_empty(kvm, pmdp) (0)
 209 #else
 210 #define kvm_pmd_table_empty(kvm, pmdp) \
 211         (kvm_page_empty(pmdp) && (!(kvm) || KVM_PREALLOC_LEVEL < 2))
 212 #endif
 213
 214 #ifdef __PAGETABLE_PUD_FOLDED
 215 #define kvm_pud_table_empty(kvm, pudp) (0)
 216 #else
 217 #define kvm_pud_table_empty(kvm, pudp) \
 218         (kvm_page_empty(pudp) && (!(kvm) || KVM_PREALLOC_LEVEL < 1))
 219 #endif
 220
 221
 222 struct kvm;
 223
 224 #define kvm_flush_dcache_to_poc(a,l)    __flush_dcache_area((a), (l))
 225
 226 static inline bool vcpu_has_cache_enabled(struct kvm_vcpu *vcpu)
 227 {
 228         return (vcpu_sys_reg(vcpu, SCTLR_EL1) & 0b101) == 0b101;
 229 }
 230
 231 static inline void __coherent_cache_guest_page(struct kvm_vcpu *vcpu, pfn_t pfn,
 232                                                unsigned long size,
 233                                                bool ipa_uncached)
 234 {
 235         void *va = page_address(pfn_to_page(pfn));
 236
 237         if (!vcpu_has_cache_enabled(vcpu) || ipa_uncached)
 238                 kvm_flush_dcache_to_poc(va, size);
 239
 240         if (!icache_is_aliasing()) {            /* PIPT */
 241                 flush_icache_range((unsigned long)va,
 242                                    (unsigned long)va + size);
 243         } else if (!icache_is_aivivt()) {       /* non ASID-tagged VIVT */
 244                 /* any kind of VIPT cache */
 245                 __flush_icache_all();
 246         }
 247 }
 248
 249 static inline void __kvm_flush_dcache_pte(pte_t pte)
 250 {
 251         struct page *page = pte_page(pte);
 252         kvm_flush_dcache_to_poc(page_address(page), PAGE_SIZE);
 253 }
 254
 255 static inline void __kvm_flush_dcache_pmd(pmd_t pmd)
 256 {
 257         struct page *page = pmd_page(pmd);
 258         kvm_flush_dcache_to_poc(page_address(page), PMD_SIZE);
 259 }
 260
 261 static inline void __kvm_flush_dcache_pud(pud_t pud)
 262 {
 263         struct page *page = pud_page(pud);
 264         kvm_flush_dcache_to_poc(page_address(page), PUD_SIZE);
 265 }
 266
 267 #define kvm_virt_to_phys(x)             __virt_to_phys((unsigned long)(x))
 268
 269 void kvm_set_way_flush(struct kvm_vcpu *vcpu);
 270 void kvm_toggle_cache(struct kvm_vcpu *vcpu, bool was_enabled);
 271
 272 #endif /* __ASSEMBLY__ */
 273 #endif /* __ARM64_KVM_MMU_H__ */