arch/arm64/include/asm/pgtable.h

   1 /*
   2  * Copyright (C) 2012 ARM Ltd.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  *
  13  * You should have received a copy of the GNU General Public License
  14  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  15  */
  16 #ifndef __ASM_PGTABLE_H
  17 #define __ASM_PGTABLE_H
  18
  19 #include <asm/bug.h>
  20 #include <asm/proc-fns.h>
  21
  22 #include <asm/memory.h>
  23 #include <asm/pgtable-hwdef.h>
  24
  25 /*
  26  * Software defined PTE bits definition.
  27  */
  28 #define PTE_VALID               (_AT(pteval_t, 1) << 0)
  29 #define PTE_WRITE               (PTE_DBM)                /* same as DBM (51) */
  30 #define PTE_DIRTY               (_AT(pteval_t, 1) << 55)
  31 #define PTE_SPECIAL             (_AT(pteval_t, 1) << 56)
  32 #define PTE_PROT_NONE           (_AT(pteval_t, 1) << 58) /* only when !PTE_VALID */
  33
  34 /*
  35  * VMALLOC and SPARSEMEM_VMEMMAP ranges.
  36  *
  37  * VMEMAP_SIZE: allows the whole VA space to be covered by a struct page array
  38  *      (rounded up to PUD_SIZE).
  39  * VMALLOC_START: beginning of the kernel VA space
  40  * VMALLOC_END: extends to the available space below vmmemmap, PCI I/O space,
  41  *      fixed mappings and modules
  42  */
  43 #define VMEMMAP_SIZE            ALIGN((1UL << (VA_BITS - PAGE_SHIFT)) * sizeof(struct page), PUD_SIZE)
  44
  45 #ifndef CONFIG_KASAN
  46 #define VMALLOC_START           (VA_START)
  47 #else
  48 #include <asm/kasan.h>
  49 #define VMALLOC_START           (KASAN_SHADOW_END + SZ_64K)
  50 #endif
  51
  52 #define VMALLOC_END             (PAGE_OFFSET - PUD_SIZE - VMEMMAP_SIZE - SZ_64K)
  53
  54 #define vmemmap                 ((struct page *)(VMALLOC_END + SZ_64K))
  55
  56 #define FIRST_USER_ADDRESS      0UL
  57
  58 #ifndef __ASSEMBLY__
  59
  60 #include <linux/mmdebug.h>
  61
  62 extern void __pte_error(const char *file, int line, unsigned long val);
  63 extern void __pmd_error(const char *file, int line, unsigned long val);
  64 extern void __pud_error(const char *file, int line, unsigned long val);
  65 extern void __pgd_error(const char *file, int line, unsigned long val);
  66
  67 #define PROT_DEFAULT            (PTE_TYPE_PAGE | PTE_AF | PTE_SHARED)
  68 #define PROT_SECT_DEFAULT       (PMD_TYPE_SECT | PMD_SECT_AF | PMD_SECT_S)
  69
  70 #define PROT_DEVICE_nGnRnE      (PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_DIRTY | PTE_WRITE | PTE_ATTRINDX(MT_DEVICE_nGnRnE))
  71 #define PROT_DEVICE_nGnRE       (PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_DIRTY | PTE_WRITE | PTE_ATTRINDX(MT_DEVICE_nGnRE))
  72 #define PROT_NORMAL_NC          (PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_DIRTY | PTE_WRITE | PTE_ATTRINDX(MT_NORMAL_NC))
  73 #define PROT_NORMAL_WT          (PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_DIRTY | PTE_WRITE | PTE_ATTRINDX(MT_NORMAL_WT))
  74 #define PROT_NORMAL             (PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_DIRTY | PTE_WRITE | PTE_ATTRINDX(MT_NORMAL))
  75
  76 #define PROT_SECT_DEVICE_nGnRE  (PROT_SECT_DEFAULT | PMD_SECT_PXN | PMD_SECT_UXN | PMD_ATTRINDX(MT_DEVICE_nGnRE))
  77 #define PROT_SECT_NORMAL        (PROT_SECT_DEFAULT | PMD_SECT_PXN | PMD_SECT_UXN | PMD_ATTRINDX(MT_NORMAL))
  78 #define PROT_SECT_NORMAL_EXEC   (PROT_SECT_DEFAULT | PMD_SECT_UXN | PMD_ATTRINDX(MT_NORMAL))
  79
  80 #define _PAGE_DEFAULT           (PROT_DEFAULT | PTE_ATTRINDX(MT_NORMAL))
  81
  82 #define PAGE_KERNEL             __pgprot(_PAGE_DEFAULT | PTE_PXN | PTE_UXN | PTE_DIRTY | PTE_WRITE)
  83 #define PAGE_KERNEL_RO          __pgprot(_PAGE_DEFAULT | PTE_PXN | PTE_UXN | PTE_DIRTY | PTE_RDONLY)
  84 #define PAGE_KERNEL_ROX         __pgprot(_PAGE_DEFAULT | PTE_UXN | PTE_DIRTY | PTE_RDONLY)
  85 #define PAGE_KERNEL_EXEC        __pgprot(_PAGE_DEFAULT | PTE_UXN | PTE_DIRTY | PTE_WRITE)
  86 #define PAGE_KERNEL_EXEC_CONT   __pgprot(_PAGE_DEFAULT | PTE_UXN | PTE_DIRTY | PTE_WRITE | PTE_CONT)
  87
  88 #define PAGE_HYP                __pgprot(_PAGE_DEFAULT | PTE_HYP)
  89 #define PAGE_HYP_DEVICE         __pgprot(PROT_DEVICE_nGnRE | PTE_HYP)
  90
  91 #define PAGE_S2                 __pgprot(PROT_DEFAULT | PTE_S2_MEMATTR(MT_S2_NORMAL) | PTE_S2_RDONLY)
  92 #define PAGE_S2_DEVICE          __pgprot(PROT_DEFAULT | PTE_S2_MEMATTR(MT_S2_DEVICE_nGnRE) | PTE_S2_RDONLY | PTE_UXN)
  93
  94 #define PAGE_NONE               __pgprot(((_PAGE_DEFAULT) & ~PTE_VALID) | PTE_PROT_NONE | PTE_PXN | PTE_UXN)
  95 #define PAGE_SHARED             __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_NG | PTE_PXN | PTE_UXN | PTE_WRITE)
  96 #define PAGE_SHARED_EXEC        __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_NG | PTE_PXN | PTE_WRITE)
  97 #define PAGE_COPY               __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_NG | PTE_PXN | PTE_UXN)
  98 #define PAGE_COPY_EXEC          __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_NG | PTE_PXN)
  99 #define PAGE_READONLY           __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_NG | PTE_PXN | PTE_UXN)
 100 #define PAGE_READONLY_EXEC      __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_NG | PTE_PXN)
 101
 102 #define __P000  PAGE_NONE
 103 #define __P001  PAGE_READONLY
 104 #define __P010  PAGE_COPY
 105 #define __P011  PAGE_COPY
 106 #define __P100  PAGE_READONLY_EXEC
 107 #define __P101  PAGE_READONLY_EXEC
 108 #define __P110  PAGE_COPY_EXEC
 109 #define __P111  PAGE_COPY_EXEC
 110
 111 #define __S000  PAGE_NONE
 112 #define __S001  PAGE_READONLY
 113 #define __S010  PAGE_SHARED
 114 #define __S011  PAGE_SHARED
 115 #define __S100  PAGE_READONLY_EXEC
 116 #define __S101  PAGE_READONLY_EXEC
 117 #define __S110  PAGE_SHARED_EXEC
 118 #define __S111  PAGE_SHARED_EXEC
 119
 120 /*
 121  * ZERO_PAGE is a global shared page that is always zero: used
 122  * for zero-mapped memory areas etc..
 123  */
 124 extern unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)];
 125 #define ZERO_PAGE(vaddr)        virt_to_page(empty_zero_page)
 126
 127 #define pte_ERROR(pte)          __pte_error(__FILE__, __LINE__, pte_val(pte))
 128
 129 #define pte_pfn(pte)            ((pte_val(pte) & PHYS_MASK) >> PAGE_SHIFT)
 130
 131 #define pfn_pte(pfn,prot)       (__pte(((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot)))
 132
 133 #define pte_none(pte)           (!pte_val(pte))
 134 #define pte_clear(mm,addr,ptep) set_pte(ptep, __pte(0))
 135 #define pte_page(pte)           (pfn_to_page(pte_pfn(pte)))
 136
 137 /*
 138  * The following only work if pte_present(). Undefined behaviour otherwise.
 139  */
 140 #define pte_present(pte)        (!!(pte_val(pte) & (PTE_VALID | PTE_PROT_NONE)))
 141 #define pte_young(pte)          (!!(pte_val(pte) & PTE_AF))
 142 #define pte_special(pte)        (!!(pte_val(pte) & PTE_SPECIAL))
 143 #define pte_write(pte)          (!!(pte_val(pte) & PTE_WRITE))
 144 #define pte_exec(pte)           (!(pte_val(pte) & PTE_UXN))
 145 #define pte_cont(pte)           (!!(pte_val(pte) & PTE_CONT))
 146 #define pte_user(pte)           (!!(pte_val(pte) & PTE_USER))
 147
 148 #ifdef CONFIG_ARM64_HW_AFDBM
 149 #define pte_hw_dirty(pte)       (pte_write(pte) && !(pte_val(pte) & PTE_RDONLY))
 150 #else
 151 #define pte_hw_dirty(pte)       (0)
 152 #endif
 153 #define pte_sw_dirty(pte)       (!!(pte_val(pte) & PTE_DIRTY))
 154 #define pte_dirty(pte)          (pte_sw_dirty(pte) || pte_hw_dirty(pte))
 155
 156 #define pte_valid(pte)          (!!(pte_val(pte) & PTE_VALID))
 157 #define pte_valid_not_user(pte) \
 158         ((pte_val(pte) & (PTE_VALID | PTE_USER)) == PTE_VALID)
 159 #define pte_valid_young(pte) \
 160         ((pte_val(pte) & (PTE_VALID | PTE_AF)) == (PTE_VALID | PTE_AF))
 161
 162 /*
 163  * Could the pte be present in the TLB? We must check mm_tlb_flush_pending
 164  * so that we don't erroneously return false for pages that have been
 165  * remapped as PROT_NONE but are yet to be flushed from the TLB.
 166  */
 167 #define pte_accessible(mm, pte) \
 168         (mm_tlb_flush_pending(mm) ? pte_present(pte) : pte_valid_young(pte))
 169
 170 static inline pte_t clear_pte_bit(pte_t pte, pgprot_t prot)
 171 {
 172         pte_val(pte) &= ~pgprot_val(prot);
 173         return pte;
 174 }
 175
 176 static inline pte_t set_pte_bit(pte_t pte, pgprot_t prot)
 177 {
 178         pte_val(pte) |= pgprot_val(prot);
 179         return pte;
 180 }
 181
 182 static inline pte_t pte_wrprotect(pte_t pte)
 183 {
 184         return clear_pte_bit(pte, __pgprot(PTE_WRITE));
 185 }
 186
 187 static inline pte_t pte_mkwrite(pte_t pte)
 188 {
 189         return set_pte_bit(pte, __pgprot(PTE_WRITE));
 190 }
 191
 192 static inline pte_t pte_mkclean(pte_t pte)
 193 {
 194         return clear_pte_bit(pte, __pgprot(PTE_DIRTY));
 195 }
 196
 197 static inline pte_t pte_mkdirty(pte_t pte)
 198 {
 199         return set_pte_bit(pte, __pgprot(PTE_DIRTY));
 200 }
 201
 202 static inline pte_t pte_mkold(pte_t pte)
 203 {
 204         return clear_pte_bit(pte, __pgprot(PTE_AF));
 205 }
 206
 207 static inline pte_t pte_mkyoung(pte_t pte)
 208 {
 209         return set_pte_bit(pte, __pgprot(PTE_AF));
 210 }
 211
 212 static inline pte_t pte_mkspecial(pte_t pte)
 213 {
 214         return set_pte_bit(pte, __pgprot(PTE_SPECIAL));
 215 }
 216
 217 static inline pte_t pte_mkcont(pte_t pte)
 218 {
 219         pte = set_pte_bit(pte, __pgprot(PTE_CONT));
 220         return set_pte_bit(pte, __pgprot(PTE_TYPE_PAGE));
 221 }
 222
 223 static inline pte_t pte_mknoncont(pte_t pte)
 224 {
 225         return clear_pte_bit(pte, __pgprot(PTE_CONT));
 226 }
 227
 228 static inline pmd_t pmd_mkcont(pmd_t pmd)
 229 {
 230         return __pmd(pmd_val(pmd) | PMD_SECT_CONT);
 231 }
 232
 233 static inline void set_pte(pte_t *ptep, pte_t pte)
 234 {
 235         *ptep = pte;
 236
 237         /*
 238          * Only if the new pte is valid and kernel, otherwise TLB maintenance
 239          * or update_mmu_cache() have the necessary barriers.
 240          */
 241         if (pte_valid_not_user(pte)) {
 242                 dsb(ishst);
 243                 isb();
 244         }
 245 }
 246
 247 struct mm_struct;
 248 struct vm_area_struct;
 249
 250 extern void __sync_icache_dcache(pte_t pteval, unsigned long addr);
 251
 252 /*
 253  * PTE bits configuration in the presence of hardware Dirty Bit Management
 254  * (PTE_WRITE == PTE_DBM):
 255  *
 256  * Dirty  Writable | PTE_RDONLY  PTE_WRITE  PTE_DIRTY (sw)
 257  *   0      0      |   1           0          0
 258  *   0      1      |   1           1          0
 259  *   1      0      |   1           0          1
 260  *   1      1      |   0           1          x
 261  *
 262  * When hardware DBM is not present, the sofware PTE_DIRTY bit is updated via
 263  * the page fault mechanism. Checking the dirty status of a pte becomes:
 264  *
 265  *   PTE_DIRTY || (PTE_WRITE && !PTE_RDONLY)
 266  */
 267 static inline void set_pte_at(struct mm_struct *mm, unsigned long addr,
 268                               pte_t *ptep, pte_t pte)
 269 {
 270         if (pte_valid(pte)) {
 271                 if (pte_sw_dirty(pte) && pte_write(pte))
 272                         pte_val(pte) &= ~PTE_RDONLY;
 273                 else
 274                         pte_val(pte) |= PTE_RDONLY;
 275                 if (pte_user(pte) && pte_exec(pte) && !pte_special(pte))
 276                         __sync_icache_dcache(pte, addr);
 277         }
 278
 279         /*
 280          * If the existing pte is valid, check for potential race with
 281          * hardware updates of the pte (ptep_set_access_flags safely changes
 282          * valid ptes without going through an invalid entry).
 283          */
 284         if (IS_ENABLED(CONFIG_ARM64_HW_AFDBM) &&
 285             pte_valid(*ptep) && pte_valid(pte)) {
 286                 VM_WARN_ONCE(!pte_young(pte),
 287                              "%s: racy access flag clearing: 0x%016llx -> 0x%016llx",
 288                              __func__, pte_val(*ptep), pte_val(pte));
 289                 VM_WARN_ONCE(pte_write(*ptep) && !pte_dirty(pte),
 290                              "%s: racy dirty state clearing: 0x%016llx -> 0x%016llx",
 291                              __func__, pte_val(*ptep), pte_val(pte));
 292         }
 293
 294         set_pte(ptep, pte);
 295 }
 296
 297 /*
 298  * Huge pte definitions.
 299  */
 300 #define pte_huge(pte)           (!(pte_val(pte) & PTE_TABLE_BIT))
 301 #define pte_mkhuge(pte)         (__pte(pte_val(pte) & ~PTE_TABLE_BIT))
 302
 303 /*
 304  * Hugetlb definitions.
 305  */
 306 #define HUGE_MAX_HSTATE         4
 307 #define HPAGE_SHIFT             PMD_SHIFT
 308 #define HPAGE_SIZE              (_AC(1, UL) << HPAGE_SHIFT)
 309 #define HPAGE_MASK              (~(HPAGE_SIZE - 1))
 310 #define HUGETLB_PAGE_ORDER      (HPAGE_SHIFT - PAGE_SHIFT)
 311
 312 #define __HAVE_ARCH_PTE_SPECIAL
 313
 314 static inline pte_t pud_pte(pud_t pud)
 315 {
 316         return __pte(pud_val(pud));
 317 }
 318
 319 static inline pmd_t pud_pmd(pud_t pud)
 320 {
 321         return __pmd(pud_val(pud));
 322 }
 323
 324 static inline pte_t pmd_pte(pmd_t pmd)
 325 {
 326         return __pte(pmd_val(pmd));
 327 }
 328
 329 static inline pmd_t pte_pmd(pte_t pte)
 330 {
 331         return __pmd(pte_val(pte));
 332 }
 333
 334 static inline pgprot_t mk_sect_prot(pgprot_t prot)
 335 {
 336         return __pgprot(pgprot_val(prot) & ~PTE_TABLE_BIT);
 337 }
 338
 339 /*
 340  * THP definitions.
 341  */
 342
 343 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
 344 #define pmd_trans_huge(pmd)     (pmd_val(pmd) && !(pmd_val(pmd) & PMD_TABLE_BIT))
 345 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */
 346
 347 #define pmd_dirty(pmd)          pte_dirty(pmd_pte(pmd))
 348 #define pmd_young(pmd)          pte_young(pmd_pte(pmd))
 349 #define pmd_wrprotect(pmd)      pte_pmd(pte_wrprotect(pmd_pte(pmd)))
 350 #define pmd_mkold(pmd)          pte_pmd(pte_mkold(pmd_pte(pmd)))
 351 #define pmd_mkwrite(pmd)        pte_pmd(pte_mkwrite(pmd_pte(pmd)))
 352 #define pmd_mkclean(pmd)       pte_pmd(pte_mkclean(pmd_pte(pmd)))
 353 #define pmd_mkdirty(pmd)        pte_pmd(pte_mkdirty(pmd_pte(pmd)))
 354 #define pmd_mkyoung(pmd)        pte_pmd(pte_mkyoung(pmd_pte(pmd)))
 355 #define pmd_mknotpresent(pmd)   (__pmd(pmd_val(pmd) & ~PMD_TYPE_MASK))
 356
 357 #define __HAVE_ARCH_PMD_WRITE
 358 #define pmd_write(pmd)          pte_write(pmd_pte(pmd))
 359
 360 #define pmd_mkhuge(pmd)         (__pmd(pmd_val(pmd) & ~PMD_TABLE_BIT))
 361
 362 #define pmd_pfn(pmd)            (((pmd_val(pmd) & PMD_MASK) & PHYS_MASK) >> PAGE_SHIFT)
 363 #define pfn_pmd(pfn,prot)       (__pmd(((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot)))
 364 #define mk_pmd(page,prot)       pfn_pmd(page_to_pfn(page),prot)
 365
 366 #define pud_write(pud)          pte_write(pud_pte(pud))
 367 #define pud_pfn(pud)            (((pud_val(pud) & PUD_MASK) & PHYS_MASK) >> PAGE_SHIFT)
 368
 369 #define set_pmd_at(mm, addr, pmdp, pmd) set_pte_at(mm, addr, (pte_t *)pmdp, pmd_pte(pmd))
 370
 371 static inline int has_transparent_hugepage(void)
 372 {
 373         return 1;
 374 }
 375
 376 #define __pgprot_modify(prot,mask,bits) \
 377         __pgprot((pgprot_val(prot) & ~(mask)) | (bits))
 378
 379 /*
 380  * Mark the prot value as uncacheable and unbufferable.
 381  */
 382 #define pgprot_noncached(prot) \
 383         __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRnE) | PTE_PXN | PTE_UXN)
 384 #define pgprot_writecombine(prot) \
 385         __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL_NC) | PTE_PXN | PTE_UXN)
 386 #define pgprot_device(prot) \
 387         __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRE) | PTE_PXN | PTE_UXN)
 388 #define __HAVE_PHYS_MEM_ACCESS_PROT
 389 struct file;
 390 extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
 391                                      unsigned long size, pgprot_t vma_prot);
 392
 393 #define pmd_none(pmd)           (!pmd_val(pmd))
 394 #define pmd_present(pmd)        (pmd_val(pmd))
 395
 396 #define pmd_bad(pmd)            (!(pmd_val(pmd) & 2))
 397
 398 #define pmd_table(pmd)          ((pmd_val(pmd) & PMD_TYPE_MASK) == \
 399                                  PMD_TYPE_TABLE)
 400 #define pmd_sect(pmd)           ((pmd_val(pmd) & PMD_TYPE_MASK) == \
 401                                  PMD_TYPE_SECT)
 402
 403 #ifdef CONFIG_ARM64_64K_PAGES
 404 #define pud_sect(pud)           (0)
 405 #define pud_table(pud)          (1)
 406 #else
 407 #define pud_sect(pud)           ((pud_val(pud) & PUD_TYPE_MASK) == \
 408                                  PUD_TYPE_SECT)
 409 #define pud_table(pud)          ((pud_val(pud) & PUD_TYPE_MASK) == \
 410                                  PUD_TYPE_TABLE)
 411 #endif
 412
 413 static inline void set_pmd(pmd_t *pmdp, pmd_t pmd)
 414 {
 415         *pmdp = pmd;
 416         dsb(ishst);
 417         isb();
 418 }
 419
 420 static inline void pmd_clear(pmd_t *pmdp)
 421 {
 422         set_pmd(pmdp, __pmd(0));
 423 }
 424
 425 static inline phys_addr_t pmd_page_paddr(pmd_t pmd)
 426 {
 427         return pmd_val(pmd) & PHYS_MASK & (s32)PAGE_MASK;
 428 }
 429
 430 /* Find an entry in the third-level page table. */
 431 #define pte_index(addr)         (((addr) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
 432
 433 #define pte_offset_phys(dir,addr)       (pmd_page_paddr(*(dir)) + pte_index(addr) * sizeof(pte_t))
 434 #define pte_offset_kernel(dir,addr)     ((pte_t *)__va(pte_offset_phys((dir), (addr))))
 435
 436 #define pte_offset_map(dir,addr)        pte_offset_kernel((dir), (addr))
 437 #define pte_offset_map_nested(dir,addr) pte_offset_kernel((dir), (addr))
 438 #define pte_unmap(pte)                  do { } while (0)
 439 #define pte_unmap_nested(pte)           do { } while (0)
 440
 441 #define pmd_page(pmd)           pfn_to_page(__phys_to_pfn(pmd_val(pmd) & PHYS_MASK))
 442
 443 /*
 444  * Conversion functions: convert a page and protection to a page entry,
 445  * and a page entry and page directory to the page they refer to.
 446  */
 447 #define mk_pte(page,prot)       pfn_pte(page_to_pfn(page),prot)
 448
 449 #if CONFIG_PGTABLE_LEVELS > 2
 450
 451 #define pmd_ERROR(pmd)          __pmd_error(__FILE__, __LINE__, pmd_val(pmd))
 452
 453 #define pud_none(pud)           (!pud_val(pud))
 454 #define pud_bad(pud)            (!(pud_val(pud) & 2))
 455 #define pud_present(pud)        (pud_val(pud))
 456
 457 static inline void set_pud(pud_t *pudp, pud_t pud)
 458 {
 459         *pudp = pud;
 460         dsb(ishst);
 461         isb();
 462 }
 463
 464 static inline void pud_clear(pud_t *pudp)
 465 {
 466         set_pud(pudp, __pud(0));
 467 }
 468
 469 static inline phys_addr_t pud_page_paddr(pud_t pud)
 470 {
 471         return pud_val(pud) & PHYS_MASK & (s32)PAGE_MASK;
 472 }
 473
 474 /* Find an entry in the second-level page table. */
 475 #define pmd_index(addr)         (((addr) >> PMD_SHIFT) & (PTRS_PER_PMD - 1))
 476
 477 #define pmd_offset_phys(dir, addr)      (pud_page_paddr(*(dir)) + pmd_index(addr) * sizeof(pmd_t))
 478 #define pmd_offset(dir, addr)           ((pmd_t *)__va(pmd_offset_phys((dir), (addr))))
 479
 480 #define pud_page(pud)           pfn_to_page(__phys_to_pfn(pud_val(pud) & PHYS_MASK))
 481
 482 #else
 483
 484 #define pud_page_paddr(pud)     ({ BUILD_BUG(); 0; })
 485
 486 #endif  /* CONFIG_PGTABLE_LEVELS > 2 */
 487
 488 #if CONFIG_PGTABLE_LEVELS > 3
 489
 490 #define pud_ERROR(pud)          __pud_error(__FILE__, __LINE__, pud_val(pud))
 491
 492 #define pgd_none(pgd)           (!pgd_val(pgd))
 493 #define pgd_bad(pgd)            (!(pgd_val(pgd) & 2))
 494 #define pgd_present(pgd)        (pgd_val(pgd))
 495
 496 static inline void set_pgd(pgd_t *pgdp, pgd_t pgd)
 497 {
 498         *pgdp = pgd;
 499         dsb(ishst);
 500 }
 501
 502 static inline void pgd_clear(pgd_t *pgdp)
 503 {
 504         set_pgd(pgdp, __pgd(0));
 505 }
 506
 507 static inline phys_addr_t pgd_page_paddr(pgd_t pgd)
 508 {
 509         return pgd_val(pgd) & PHYS_MASK & (s32)PAGE_MASK;
 510 }
 511
 512 /* Find an entry in the frst-level page table. */
 513 #define pud_index(addr)         (((addr) >> PUD_SHIFT) & (PTRS_PER_PUD - 1))
 514
 515 #define pud_offset_phys(dir, addr)      (pgd_page_paddr(*(dir)) + pud_index(addr) * sizeof(pud_t))
 516 #define pud_offset(dir, addr)           ((pud_t *)__va(pud_offset_phys((dir), (addr))))
 517
 518 #define pgd_page(pgd)           pfn_to_page(__phys_to_pfn(pgd_val(pgd) & PHYS_MASK))
 519
 520 #else
 521
 522 #define pgd_page_paddr(pgd)     ({ BUILD_BUG(); 0;})
 523
 524 #endif  /* CONFIG_PGTABLE_LEVELS > 3 */
 525
 526 #define pgd_ERROR(pgd)          __pgd_error(__FILE__, __LINE__, pgd_val(pgd))
 527
 528 /* to find an entry in a page-table-directory */
 529 #define pgd_index(addr)         (((addr) >> PGDIR_SHIFT) & (PTRS_PER_PGD - 1))
 530
 531 #define pgd_offset_raw(pgd, addr)       ((pgd) + pgd_index(addr))
 532
 533 #define pgd_offset(mm, addr)    (pgd_offset_raw((mm)->pgd, (addr)))
 534
 535 /* to find an entry in a kernel page-table-directory */
 536 #define pgd_offset_k(addr)      pgd_offset(&init_mm, addr)
 537
 538 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
 539 {
 540         const pteval_t mask = PTE_USER | PTE_PXN | PTE_UXN | PTE_RDONLY |
 541                               PTE_PROT_NONE | PTE_VALID | PTE_WRITE;
 542         /* preserve the hardware dirty information */
 543         if (pte_hw_dirty(pte))
 544                 pte = pte_mkdirty(pte);
 545         pte_val(pte) = (pte_val(pte) & ~mask) | (pgprot_val(newprot) & mask);
 546         return pte;
 547 }
 548
 549 static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot)
 550 {
 551         return pte_pmd(pte_modify(pmd_pte(pmd), newprot));
 552 }
 553
 554 #ifdef CONFIG_ARM64_HW_AFDBM
 555 /*
 556  * Atomic pte/pmd modifications.
 557  */
 558 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
 559 static inline int ptep_test_and_clear_young(struct vm_area_struct *vma,
 560                                             unsigned long address,
 561                                             pte_t *ptep)
 562 {
 563         pteval_t pteval;
 564         unsigned int tmp, res;
 565
 566         asm volatile("//        ptep_test_and_clear_young\n"
 567         "       prfm    pstl1strm, %2\n"
 568         "1:     ldxr    %0, %2\n"
 569         "       ubfx    %w3, %w0, %5, #1        // extract PTE_AF (young)\n"
 570         "       and     %0, %0, %4              // clear PTE_AF\n"
 571         "       stxr    %w1, %0, %2\n"
 572         "       cbnz    %w1, 1b\n"
 573         : "=&r" (pteval), "=&r" (tmp), "+Q" (pte_val(*ptep)), "=&r" (res)
 574         : "L" (~PTE_AF), "I" (ilog2(PTE_AF)));
 575
 576         return res;
 577 }
 578
 579 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
 580 #define __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG
 581 static inline int pmdp_test_and_clear_young(struct vm_area_struct *vma,
 582                                             unsigned long address,
 583                                             pmd_t *pmdp)
 584 {
 585         return ptep_test_and_clear_young(vma, address, (pte_t *)pmdp);
 586 }
 587 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */
 588
 589 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR
 590 static inline pte_t ptep_get_and_clear(struct mm_struct *mm,
 591                                        unsigned long address, pte_t *ptep)
 592 {
 593         pteval_t old_pteval;
 594         unsigned int tmp;
 595
 596         asm volatile("//        ptep_get_and_clear\n"
 597         "       prfm    pstl1strm, %2\n"
 598         "1:     ldxr    %0, %2\n"
 599         "       stxr    %w1, xzr, %2\n"
 600         "       cbnz    %w1, 1b\n"
 601         : "=&r" (old_pteval), "=&r" (tmp), "+Q" (pte_val(*ptep)));
 602
 603         return __pte(old_pteval);
 604 }
 605
 606 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
 607 #define __HAVE_ARCH_PMDP_GET_AND_CLEAR
 608 static inline pmd_t pmdp_get_and_clear(struct mm_struct *mm,
 609                                        unsigned long address, pmd_t *pmdp)
 610 {
 611         return pte_pmd(ptep_get_and_clear(mm, address, (pte_t *)pmdp));
 612 }
 613 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */
 614
 615 /*
 616  * ptep_set_wrprotect - mark read-only while trasferring potential hardware
 617  * dirty status (PTE_DBM && !PTE_RDONLY) to the software PTE_DIRTY bit.
 618  */
 619 #define __HAVE_ARCH_PTEP_SET_WRPROTECT
 620 static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long address, pte_t *ptep)
 621 {
 622         pteval_t pteval;
 623         unsigned long tmp;
 624
 625         asm volatile("//        ptep_set_wrprotect\n"
 626         "       prfm    pstl1strm, %2\n"
 627         "1:     ldxr    %0, %2\n"
 628         "       tst     %0, %4                  // check for hw dirty (!PTE_RDONLY)\n"
 629         "       csel    %1, %3, xzr, eq         // set PTE_DIRTY|PTE_RDONLY if dirty\n"
 630         "       orr     %0, %0, %1              // if !dirty, PTE_RDONLY is already set\n"
 631         "       and     %0, %0, %5              // clear PTE_WRITE/PTE_DBM\n"
 632         "       stxr    %w1, %0, %2\n"
 633         "       cbnz    %w1, 1b\n"
 634         : "=&r" (pteval), "=&r" (tmp), "+Q" (pte_val(*ptep))
 635         : "r" (PTE_DIRTY|PTE_RDONLY), "L" (PTE_RDONLY), "L" (~PTE_WRITE)
 636         : "cc");
 637 }
 638
 639 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
 640 #define __HAVE_ARCH_PMDP_SET_WRPROTECT
 641 static inline void pmdp_set_wrprotect(struct mm_struct *mm,
 642                                       unsigned long address, pmd_t *pmdp)
 643 {
 644         ptep_set_wrprotect(mm, address, (pte_t *)pmdp);
 645 }
 646 #endif
 647 #endif  /* CONFIG_ARM64_HW_AFDBM */
 648
 649 extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
 650 extern pgd_t idmap_pg_dir[PTRS_PER_PGD];
 651
 652 /*
 653  * Encode and decode a swap entry:
 654  *      bits 0-1:       present (must be zero)
 655  *      bits 2-7:       swap type
 656  *      bits 8-57:      swap offset
 657  */
 658 #define __SWP_TYPE_SHIFT        2
 659 #define __SWP_TYPE_BITS         6
 660 #define __SWP_OFFSET_BITS       50
 661 #define __SWP_TYPE_MASK         ((1 << __SWP_TYPE_BITS) - 1)
 662 #define __SWP_OFFSET_SHIFT      (__SWP_TYPE_BITS + __SWP_TYPE_SHIFT)
 663 #define __SWP_OFFSET_MASK       ((1UL << __SWP_OFFSET_BITS) - 1)
 664
 665 #define __swp_type(x)           (((x).val >> __SWP_TYPE_SHIFT) & __SWP_TYPE_MASK)
 666 #define __swp_offset(x)         (((x).val >> __SWP_OFFSET_SHIFT) & __SWP_OFFSET_MASK)
 667 #define __swp_entry(type,offset) ((swp_entry_t) { ((type) << __SWP_TYPE_SHIFT) | ((offset) << __SWP_OFFSET_SHIFT) })
 668
 669 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
 670 #define __swp_entry_to_pte(swp) ((pte_t) { (swp).val })
 671
 672 /*
 673  * Ensure that there are not more swap files than can be encoded in the kernel
 674  * PTEs.
 675  */
 676 #define MAX_SWAPFILES_CHECK() BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > __SWP_TYPE_BITS)
 677
 678 extern int kern_addr_valid(unsigned long addr);
 679
 680 #include <asm-generic/pgtable.h>
 681
 682 void pgd_cache_init(void);
 683 #define pgtable_cache_init      pgd_cache_init
 684
 685 /*
 686  * On AArch64, the cache coherency is handled via the set_pte_at() function.
 687  */
 688 static inline void update_mmu_cache(struct vm_area_struct *vma,
 689                                     unsigned long addr, pte_t *ptep)
 690 {
 691         /*
 692          * We don't do anything here, so there's a very small chance of
 693          * us retaking a user fault which we just fixed up. The alternative
 694          * is doing a dsb(ishst), but that penalises the fastpath.
 695          */
 696 }
 697
 698 #define update_mmu_cache_pmd(vma, address, pmd) do { } while (0)
 699
 700 #define kc_vaddr_to_offset(v)   ((v) & ~VA_START)
 701 #define kc_offset_to_vaddr(o)   ((o) | VA_START)
 702
 703 #endif /* !__ASSEMBLY__ */
 704
 705 #endif /* __ASM_PGTABLE_H */