arch/arm64/kernel/cpu_errata.c

   1 /*
   2  * Contains CPU specific errata definitions
   3  *
   4  * Copyright (C) 2014 ARM Ltd.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  17  */
  18
  19 #include <linux/types.h>
  20 #include <asm/cpu.h>
  21 #include <asm/cputype.h>
  22 #include <asm/cpufeature.h>
  23
  24 #define MIDR_CORTEX_A53 MIDR_CPU_PART(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A53)
  25 #define MIDR_CORTEX_A57 MIDR_CPU_PART(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A57)
  26
  27 #define CPU_MODEL_MASK (MIDR_IMPLEMENTOR_MASK | MIDR_PARTNUM_MASK | \
  28                         MIDR_ARCHITECTURE_MASK)
  29
  30 static bool __maybe_unused
  31 is_affected_midr_range(const struct arm64_cpu_capabilities *entry)
  32 {
  33         u32 midr = read_cpuid_id();
  34
  35         if ((midr & CPU_MODEL_MASK) != entry->midr_model)
  36                 return false;
  37
  38         midr &= MIDR_REVISION_MASK | MIDR_VARIANT_MASK;
  39
  40         return (midr >= entry->midr_range_min && midr <= entry->midr_range_max);
  41 }
  42
  43 #define MIDR_RANGE(model, min, max) \
  44         .matches = is_affected_midr_range, \
  45         .midr_model = model, \
  46         .midr_range_min = min, \
  47         .midr_range_max = max
  48
  49 const struct arm64_cpu_capabilities arm64_errata[] = {
  50 #if     defined(CONFIG_ARM64_ERRATUM_826319) || \
  51         defined(CONFIG_ARM64_ERRATUM_827319) || \
  52         defined(CONFIG_ARM64_ERRATUM_824069)
  53         {
  54         /* Cortex-A53 r0p[012] */
  55                 .desc = "ARM errata 826319, 827319, 824069",
  56                 .capability = ARM64_WORKAROUND_CLEAN_CACHE,
  57                 MIDR_RANGE(MIDR_CORTEX_A53, 0x00, 0x02),
  58         },
  59 #endif
  60 #ifdef CONFIG_ARM64_ERRATUM_819472
  61         {
  62         /* Cortex-A53 r0p[01] */
  63                 .desc = "ARM errata 819472",
  64                 .capability = ARM64_WORKAROUND_CLEAN_CACHE,
  65                 MIDR_RANGE(MIDR_CORTEX_A53, 0x00, 0x01),
  66         },
  67 #endif
  68 #ifdef CONFIG_ARM64_ERRATUM_832075
  69         {
  70         /* Cortex-A57 r0p0 - r1p2 */
  71                 .desc = "ARM erratum 832075",
  72                 .capability = ARM64_WORKAROUND_DEVICE_LOAD_ACQUIRE,
  73                 MIDR_RANGE(MIDR_CORTEX_A57, 0x00,
  74                            (1 << MIDR_VARIANT_SHIFT) | 2),
  75         },
  76 #endif
  77 #ifdef CONFIG_ARM64_ERRATUM_845719
  78         {
  79         /* Cortex-A53 r0p[01234] */
  80                 .desc = "ARM erratum 845719",
  81                 .capability = ARM64_WORKAROUND_845719,
  82                 MIDR_RANGE(MIDR_CORTEX_A53, 0x00, 0x04),
  83         },
  84 #endif
  85         {
  86         }
  87 };
  88
  89 void check_local_cpu_errata(void)
  90 {
  91         check_cpu_capabilities(arm64_errata, "enabling workaround for");
  92 }