2 * Contains CPU feature definitions
4 * Copyright (C) 2015 ARM Ltd.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program. If not, see <http://www.gnu.org/licenses/>.
19 #define pr_fmt(fmt) "CPU features: " fmt
21 #include <linux/bsearch.h>
22 #include <linux/sort.h>
23 #include <linux/types.h>
25 #include <asm/cpufeature.h>
26 #include <asm/cpu_ops.h>
27 #include <asm/mmu_context.h>
28 #include <asm/processor.h>
29 #include <asm/sysreg.h>
32 unsigned long elf_hwcap __read_mostly
;
33 EXPORT_SYMBOL_GPL(elf_hwcap
);
36 #define COMPAT_ELF_HWCAP_DEFAULT \
37 (COMPAT_HWCAP_HALF|COMPAT_HWCAP_THUMB|\
38 COMPAT_HWCAP_FAST_MULT|COMPAT_HWCAP_EDSP|\
39 COMPAT_HWCAP_TLS|COMPAT_HWCAP_VFP|\
40 COMPAT_HWCAP_VFPv3|COMPAT_HWCAP_VFPv4|\
41 COMPAT_HWCAP_NEON|COMPAT_HWCAP_IDIV|\
43 unsigned int compat_elf_hwcap __read_mostly
= COMPAT_ELF_HWCAP_DEFAULT
;
44 unsigned int compat_elf_hwcap2 __read_mostly
;
47 DECLARE_BITMAP(cpu_hwcaps
, ARM64_NCAPS
);
49 #define __ARM64_FTR_BITS(SIGNED, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
56 .safe_val = SAFE_VAL, \
59 /* Define a feature with unsigned values */
60 #define ARM64_FTR_BITS(STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
61 __ARM64_FTR_BITS(FTR_UNSIGNED, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL)
63 /* Define a feature with a signed value */
64 #define S_ARM64_FTR_BITS(STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
65 __ARM64_FTR_BITS(FTR_SIGNED, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL)
67 #define ARM64_FTR_END \
72 /* meta feature for alternatives */
73 static bool __maybe_unused
74 cpufeature_pan_not_uao(const struct arm64_cpu_capabilities
*entry
, int __unused
);
77 static const struct arm64_ftr_bits ftr_id_aa64isar0
[] = {
78 ARM64_FTR_BITS(FTR_STRICT
, FTR_EXACT
, 32, 32, 0),
79 ARM64_FTR_BITS(FTR_STRICT
, FTR_EXACT
, ID_AA64ISAR0_RDM_SHIFT
, 4, 0),
80 ARM64_FTR_BITS(FTR_STRICT
, FTR_EXACT
, 24, 4, 0),
81 ARM64_FTR_BITS(FTR_STRICT
, FTR_LOWER_SAFE
, ID_AA64ISAR0_ATOMICS_SHIFT
, 4, 0),
82 ARM64_FTR_BITS(FTR_STRICT
, FTR_LOWER_SAFE
, ID_AA64ISAR0_CRC32_SHIFT
, 4, 0),
83 ARM64_FTR_BITS(FTR_STRICT
, FTR_LOWER_SAFE
, ID_AA64ISAR0_SHA2_SHIFT
, 4, 0),
84 ARM64_FTR_BITS(FTR_STRICT
, FTR_LOWER_SAFE
, ID_AA64ISAR0_SHA1_SHIFT
, 4, 0),
85 ARM64_FTR_BITS(FTR_STRICT
, FTR_LOWER_SAFE
, ID_AA64ISAR0_AES_SHIFT
, 4, 0),
86 ARM64_FTR_BITS(FTR_STRICT
, FTR_EXACT
, 0, 4, 0), /* RAZ */
90 static const struct arm64_ftr_bits ftr_id_aa64pfr0
[] = {
91 ARM64_FTR_BITS(FTR_STRICT
, FTR_EXACT
, 32, 32, 0),
92 ARM64_FTR_BITS(FTR_STRICT
, FTR_EXACT
, 28, 4, 0),
93 ARM64_FTR_BITS(FTR_STRICT
, FTR_EXACT
, ID_AA64PFR0_GIC_SHIFT
, 4, 0),
94 S_ARM64_FTR_BITS(FTR_STRICT
, FTR_LOWER_SAFE
, ID_AA64PFR0_ASIMD_SHIFT
, 4, ID_AA64PFR0_ASIMD_NI
),
95 S_ARM64_FTR_BITS(FTR_STRICT
, FTR_LOWER_SAFE
, ID_AA64PFR0_FP_SHIFT
, 4, ID_AA64PFR0_FP_NI
),
96 /* Linux doesn't care about the EL3 */
97 ARM64_FTR_BITS(FTR_NONSTRICT
, FTR_EXACT
, ID_AA64PFR0_EL3_SHIFT
, 4, 0),
98 ARM64_FTR_BITS(FTR_STRICT
, FTR_EXACT
, ID_AA64PFR0_EL2_SHIFT
, 4, 0),
99 ARM64_FTR_BITS(FTR_STRICT
, FTR_EXACT
, ID_AA64PFR0_EL1_SHIFT
, 4, ID_AA64PFR0_EL1_64BIT_ONLY
),
100 ARM64_FTR_BITS(FTR_STRICT
, FTR_EXACT
, ID_AA64PFR0_EL0_SHIFT
, 4, ID_AA64PFR0_EL0_64BIT_ONLY
),
104 static const struct arm64_ftr_bits ftr_id_aa64mmfr0
[] = {
105 ARM64_FTR_BITS(FTR_STRICT
, FTR_EXACT
, 32, 32, 0),
106 S_ARM64_FTR_BITS(FTR_STRICT
, FTR_EXACT
, ID_AA64MMFR0_TGRAN4_SHIFT
, 4, ID_AA64MMFR0_TGRAN4_NI
),
107 S_ARM64_FTR_BITS(FTR_STRICT
, FTR_EXACT
, ID_AA64MMFR0_TGRAN64_SHIFT
, 4, ID_AA64MMFR0_TGRAN64_NI
),
108 ARM64_FTR_BITS(FTR_STRICT
, FTR_EXACT
, ID_AA64MMFR0_TGRAN16_SHIFT
, 4, ID_AA64MMFR0_TGRAN16_NI
),
109 ARM64_FTR_BITS(FTR_STRICT
, FTR_EXACT
, ID_AA64MMFR0_BIGENDEL0_SHIFT
, 4, 0),
110 /* Linux shouldn't care about secure memory */
111 ARM64_FTR_BITS(FTR_NONSTRICT
, FTR_EXACT
, ID_AA64MMFR0_SNSMEM_SHIFT
, 4, 0),
112 ARM64_FTR_BITS(FTR_STRICT
, FTR_EXACT
, ID_AA64MMFR0_BIGENDEL_SHIFT
, 4, 0),
113 ARM64_FTR_BITS(FTR_STRICT
, FTR_EXACT
, ID_AA64MMFR0_ASID_SHIFT
, 4, 0),
115 * Differing PARange is fine as long as all peripherals and memory are mapped
116 * within the minimum PARange of all CPUs
118 ARM64_FTR_BITS(FTR_NONSTRICT
, FTR_LOWER_SAFE
, ID_AA64MMFR0_PARANGE_SHIFT
, 4, 0),
122 static const struct arm64_ftr_bits ftr_id_aa64mmfr1
[] = {
123 ARM64_FTR_BITS(FTR_STRICT
, FTR_EXACT
, 32, 32, 0),
124 ARM64_FTR_BITS(FTR_STRICT
, FTR_LOWER_SAFE
, ID_AA64MMFR1_PAN_SHIFT
, 4, 0),
125 ARM64_FTR_BITS(FTR_STRICT
, FTR_EXACT
, ID_AA64MMFR1_LOR_SHIFT
, 4, 0),
126 ARM64_FTR_BITS(FTR_STRICT
, FTR_EXACT
, ID_AA64MMFR1_HPD_SHIFT
, 4, 0),
127 ARM64_FTR_BITS(FTR_STRICT
, FTR_EXACT
, ID_AA64MMFR1_VHE_SHIFT
, 4, 0),
128 ARM64_FTR_BITS(FTR_STRICT
, FTR_EXACT
, ID_AA64MMFR1_VMIDBITS_SHIFT
, 4, 0),
129 ARM64_FTR_BITS(FTR_STRICT
, FTR_EXACT
, ID_AA64MMFR1_HADBS_SHIFT
, 4, 0),
133 static const struct arm64_ftr_bits ftr_id_aa64mmfr2
[] = {
134 ARM64_FTR_BITS(FTR_STRICT
, FTR_EXACT
, ID_AA64MMFR2_LVA_SHIFT
, 4, 0),
135 ARM64_FTR_BITS(FTR_STRICT
, FTR_EXACT
, ID_AA64MMFR2_IESB_SHIFT
, 4, 0),
136 ARM64_FTR_BITS(FTR_STRICT
, FTR_EXACT
, ID_AA64MMFR2_LSM_SHIFT
, 4, 0),
137 ARM64_FTR_BITS(FTR_STRICT
, FTR_EXACT
, ID_AA64MMFR2_UAO_SHIFT
, 4, 0),
138 ARM64_FTR_BITS(FTR_STRICT
, FTR_EXACT
, ID_AA64MMFR2_CNP_SHIFT
, 4, 0),
142 static const struct arm64_ftr_bits ftr_ctr
[] = {
143 ARM64_FTR_BITS(FTR_STRICT
, FTR_EXACT
, 31, 1, 1), /* RAO */
144 ARM64_FTR_BITS(FTR_STRICT
, FTR_EXACT
, 28, 3, 0),
145 ARM64_FTR_BITS(FTR_STRICT
, FTR_HIGHER_SAFE
, 24, 4, 0), /* CWG */
146 ARM64_FTR_BITS(FTR_STRICT
, FTR_LOWER_SAFE
, 20, 4, 0), /* ERG */
147 ARM64_FTR_BITS(FTR_STRICT
, FTR_LOWER_SAFE
, 16, 4, 1), /* DminLine */
149 * Linux can handle differing I-cache policies. Userspace JITs will
150 * make use of *minLine
152 ARM64_FTR_BITS(FTR_NONSTRICT
, FTR_EXACT
, 14, 2, 0), /* L1Ip */
153 ARM64_FTR_BITS(FTR_STRICT
, FTR_EXACT
, 4, 10, 0), /* RAZ */
154 ARM64_FTR_BITS(FTR_STRICT
, FTR_LOWER_SAFE
, 0, 4, 0), /* IminLine */
158 struct arm64_ftr_reg arm64_ftr_reg_ctrel0
= {
159 .name
= "SYS_CTR_EL0",
163 static const struct arm64_ftr_bits ftr_id_mmfr0
[] = {
164 S_ARM64_FTR_BITS(FTR_STRICT
, FTR_EXACT
, 28, 4, 0xf), /* InnerShr */
165 ARM64_FTR_BITS(FTR_STRICT
, FTR_EXACT
, 24, 4, 0), /* FCSE */
166 ARM64_FTR_BITS(FTR_NONSTRICT
, FTR_LOWER_SAFE
, 20, 4, 0), /* AuxReg */
167 ARM64_FTR_BITS(FTR_STRICT
, FTR_EXACT
, 16, 4, 0), /* TCM */
168 ARM64_FTR_BITS(FTR_STRICT
, FTR_EXACT
, 12, 4, 0), /* ShareLvl */
169 S_ARM64_FTR_BITS(FTR_STRICT
, FTR_EXACT
, 8, 4, 0xf), /* OuterShr */
170 ARM64_FTR_BITS(FTR_STRICT
, FTR_EXACT
, 4, 4, 0), /* PMSA */
171 ARM64_FTR_BITS(FTR_STRICT
, FTR_EXACT
, 0, 4, 0), /* VMSA */
175 static const struct arm64_ftr_bits ftr_id_aa64dfr0
[] = {
176 ARM64_FTR_BITS(FTR_STRICT
, FTR_EXACT
, 32, 32, 0),
177 ARM64_FTR_BITS(FTR_STRICT
, FTR_LOWER_SAFE
, ID_AA64DFR0_CTX_CMPS_SHIFT
, 4, 0),
178 ARM64_FTR_BITS(FTR_STRICT
, FTR_LOWER_SAFE
, ID_AA64DFR0_WRPS_SHIFT
, 4, 0),
179 ARM64_FTR_BITS(FTR_STRICT
, FTR_LOWER_SAFE
, ID_AA64DFR0_BRPS_SHIFT
, 4, 0),
180 S_ARM64_FTR_BITS(FTR_STRICT
, FTR_EXACT
, ID_AA64DFR0_PMUVER_SHIFT
, 4, 0),
181 ARM64_FTR_BITS(FTR_STRICT
, FTR_EXACT
, ID_AA64DFR0_TRACEVER_SHIFT
, 4, 0),
182 ARM64_FTR_BITS(FTR_STRICT
, FTR_EXACT
, ID_AA64DFR0_DEBUGVER_SHIFT
, 4, 0x6),
186 static const struct arm64_ftr_bits ftr_mvfr2
[] = {
187 ARM64_FTR_BITS(FTR_STRICT
, FTR_EXACT
, 8, 24, 0), /* RAZ */
188 ARM64_FTR_BITS(FTR_STRICT
, FTR_EXACT
, 4, 4, 0), /* FPMisc */
189 ARM64_FTR_BITS(FTR_STRICT
, FTR_EXACT
, 0, 4, 0), /* SIMDMisc */
193 static const struct arm64_ftr_bits ftr_dczid
[] = {
194 ARM64_FTR_BITS(FTR_STRICT
, FTR_EXACT
, 5, 27, 0), /* RAZ */
195 ARM64_FTR_BITS(FTR_STRICT
, FTR_EXACT
, 4, 1, 1), /* DZP */
196 ARM64_FTR_BITS(FTR_STRICT
, FTR_LOWER_SAFE
, 0, 4, 0), /* BS */
201 static const struct arm64_ftr_bits ftr_id_isar5
[] = {
202 ARM64_FTR_BITS(FTR_STRICT
, FTR_EXACT
, ID_ISAR5_RDM_SHIFT
, 4, 0),
203 ARM64_FTR_BITS(FTR_STRICT
, FTR_EXACT
, 20, 4, 0), /* RAZ */
204 ARM64_FTR_BITS(FTR_STRICT
, FTR_EXACT
, ID_ISAR5_CRC32_SHIFT
, 4, 0),
205 ARM64_FTR_BITS(FTR_STRICT
, FTR_EXACT
, ID_ISAR5_SHA2_SHIFT
, 4, 0),
206 ARM64_FTR_BITS(FTR_STRICT
, FTR_EXACT
, ID_ISAR5_SHA1_SHIFT
, 4, 0),
207 ARM64_FTR_BITS(FTR_STRICT
, FTR_EXACT
, ID_ISAR5_AES_SHIFT
, 4, 0),
208 ARM64_FTR_BITS(FTR_STRICT
, FTR_EXACT
, ID_ISAR5_SEVL_SHIFT
, 4, 0),
212 static const struct arm64_ftr_bits ftr_id_mmfr4
[] = {
213 ARM64_FTR_BITS(FTR_STRICT
, FTR_EXACT
, 8, 24, 0), /* RAZ */
214 ARM64_FTR_BITS(FTR_STRICT
, FTR_EXACT
, 4, 4, 0), /* ac2 */
215 ARM64_FTR_BITS(FTR_STRICT
, FTR_EXACT
, 0, 4, 0), /* RAZ */
219 static const struct arm64_ftr_bits ftr_id_pfr0
[] = {
220 ARM64_FTR_BITS(FTR_STRICT
, FTR_EXACT
, 16, 16, 0), /* RAZ */
221 ARM64_FTR_BITS(FTR_STRICT
, FTR_EXACT
, 12, 4, 0), /* State3 */
222 ARM64_FTR_BITS(FTR_STRICT
, FTR_EXACT
, 8, 4, 0), /* State2 */
223 ARM64_FTR_BITS(FTR_STRICT
, FTR_EXACT
, 4, 4, 0), /* State1 */
224 ARM64_FTR_BITS(FTR_STRICT
, FTR_EXACT
, 0, 4, 0), /* State0 */
228 static const struct arm64_ftr_bits ftr_id_dfr0
[] = {
229 ARM64_FTR_BITS(FTR_STRICT
, FTR_LOWER_SAFE
, 28, 4, 0),
230 S_ARM64_FTR_BITS(FTR_STRICT
, FTR_LOWER_SAFE
, 24, 4, 0xf), /* PerfMon */
231 ARM64_FTR_BITS(FTR_STRICT
, FTR_LOWER_SAFE
, 20, 4, 0),
232 ARM64_FTR_BITS(FTR_STRICT
, FTR_LOWER_SAFE
, 16, 4, 0),
233 ARM64_FTR_BITS(FTR_STRICT
, FTR_LOWER_SAFE
, 12, 4, 0),
234 ARM64_FTR_BITS(FTR_STRICT
, FTR_LOWER_SAFE
, 8, 4, 0),
235 ARM64_FTR_BITS(FTR_STRICT
, FTR_LOWER_SAFE
, 4, 4, 0),
236 ARM64_FTR_BITS(FTR_STRICT
, FTR_LOWER_SAFE
, 0, 4, 0),
241 * Common ftr bits for a 32bit register with all hidden, strict
242 * attributes, with 4bit feature fields and a default safe value of
243 * 0. Covers the following 32bit registers:
244 * id_isar[0-4], id_mmfr[1-3], id_pfr1, mvfr[0-1]
246 static const struct arm64_ftr_bits ftr_generic_32bits
[] = {
247 ARM64_FTR_BITS(FTR_STRICT
, FTR_LOWER_SAFE
, 28, 4, 0),
248 ARM64_FTR_BITS(FTR_STRICT
, FTR_LOWER_SAFE
, 24, 4, 0),
249 ARM64_FTR_BITS(FTR_STRICT
, FTR_LOWER_SAFE
, 20, 4, 0),
250 ARM64_FTR_BITS(FTR_STRICT
, FTR_LOWER_SAFE
, 16, 4, 0),
251 ARM64_FTR_BITS(FTR_STRICT
, FTR_LOWER_SAFE
, 12, 4, 0),
252 ARM64_FTR_BITS(FTR_STRICT
, FTR_LOWER_SAFE
, 8, 4, 0),
253 ARM64_FTR_BITS(FTR_STRICT
, FTR_LOWER_SAFE
, 4, 4, 0),
254 ARM64_FTR_BITS(FTR_STRICT
, FTR_LOWER_SAFE
, 0, 4, 0),
258 static const struct arm64_ftr_bits ftr_generic
[] = {
259 ARM64_FTR_BITS(FTR_STRICT
, FTR_EXACT
, 0, 64, 0),
263 static const struct arm64_ftr_bits ftr_generic32
[] = {
264 ARM64_FTR_BITS(FTR_STRICT
, FTR_EXACT
, 0, 32, 0),
268 static const struct arm64_ftr_bits ftr_aa64raz
[] = {
269 ARM64_FTR_BITS(FTR_STRICT
, FTR_EXACT
, 0, 64, 0),
273 #define ARM64_FTR_REG(id, table) { \
275 .reg = &(struct arm64_ftr_reg){ \
277 .ftr_bits = &((table)[0]), \
280 static const struct __ftr_reg_entry
{
282 struct arm64_ftr_reg
*reg
;
283 } arm64_ftr_regs
[] = {
285 /* Op1 = 0, CRn = 0, CRm = 1 */
286 ARM64_FTR_REG(SYS_ID_PFR0_EL1
, ftr_id_pfr0
),
287 ARM64_FTR_REG(SYS_ID_PFR1_EL1
, ftr_generic_32bits
),
288 ARM64_FTR_REG(SYS_ID_DFR0_EL1
, ftr_id_dfr0
),
289 ARM64_FTR_REG(SYS_ID_MMFR0_EL1
, ftr_id_mmfr0
),
290 ARM64_FTR_REG(SYS_ID_MMFR1_EL1
, ftr_generic_32bits
),
291 ARM64_FTR_REG(SYS_ID_MMFR2_EL1
, ftr_generic_32bits
),
292 ARM64_FTR_REG(SYS_ID_MMFR3_EL1
, ftr_generic_32bits
),
294 /* Op1 = 0, CRn = 0, CRm = 2 */
295 ARM64_FTR_REG(SYS_ID_ISAR0_EL1
, ftr_generic_32bits
),
296 ARM64_FTR_REG(SYS_ID_ISAR1_EL1
, ftr_generic_32bits
),
297 ARM64_FTR_REG(SYS_ID_ISAR2_EL1
, ftr_generic_32bits
),
298 ARM64_FTR_REG(SYS_ID_ISAR3_EL1
, ftr_generic_32bits
),
299 ARM64_FTR_REG(SYS_ID_ISAR4_EL1
, ftr_generic_32bits
),
300 ARM64_FTR_REG(SYS_ID_ISAR5_EL1
, ftr_id_isar5
),
301 ARM64_FTR_REG(SYS_ID_MMFR4_EL1
, ftr_id_mmfr4
),
303 /* Op1 = 0, CRn = 0, CRm = 3 */
304 ARM64_FTR_REG(SYS_MVFR0_EL1
, ftr_generic_32bits
),
305 ARM64_FTR_REG(SYS_MVFR1_EL1
, ftr_generic_32bits
),
306 ARM64_FTR_REG(SYS_MVFR2_EL1
, ftr_mvfr2
),
308 /* Op1 = 0, CRn = 0, CRm = 4 */
309 ARM64_FTR_REG(SYS_ID_AA64PFR0_EL1
, ftr_id_aa64pfr0
),
310 ARM64_FTR_REG(SYS_ID_AA64PFR1_EL1
, ftr_aa64raz
),
312 /* Op1 = 0, CRn = 0, CRm = 5 */
313 ARM64_FTR_REG(SYS_ID_AA64DFR0_EL1
, ftr_id_aa64dfr0
),
314 ARM64_FTR_REG(SYS_ID_AA64DFR1_EL1
, ftr_generic
),
316 /* Op1 = 0, CRn = 0, CRm = 6 */
317 ARM64_FTR_REG(SYS_ID_AA64ISAR0_EL1
, ftr_id_aa64isar0
),
318 ARM64_FTR_REG(SYS_ID_AA64ISAR1_EL1
, ftr_aa64raz
),
320 /* Op1 = 0, CRn = 0, CRm = 7 */
321 ARM64_FTR_REG(SYS_ID_AA64MMFR0_EL1
, ftr_id_aa64mmfr0
),
322 ARM64_FTR_REG(SYS_ID_AA64MMFR1_EL1
, ftr_id_aa64mmfr1
),
323 ARM64_FTR_REG(SYS_ID_AA64MMFR2_EL1
, ftr_id_aa64mmfr2
),
325 /* Op1 = 3, CRn = 0, CRm = 0 */
326 { SYS_CTR_EL0
, &arm64_ftr_reg_ctrel0
},
327 ARM64_FTR_REG(SYS_DCZID_EL0
, ftr_dczid
),
329 /* Op1 = 3, CRn = 14, CRm = 0 */
330 ARM64_FTR_REG(SYS_CNTFRQ_EL0
, ftr_generic32
),
333 static int search_cmp_ftr_reg(const void *id
, const void *regp
)
335 return (int)(unsigned long)id
- (int)((const struct __ftr_reg_entry
*)regp
)->sys_id
;
339 * get_arm64_ftr_reg - Lookup a feature register entry using its
340 * sys_reg() encoding. With the array arm64_ftr_regs sorted in the
341 * ascending order of sys_id , we use binary search to find a matching
344 * returns - Upon success, matching ftr_reg entry for id.
345 * - NULL on failure. It is upto the caller to decide
346 * the impact of a failure.
348 static struct arm64_ftr_reg
*get_arm64_ftr_reg(u32 sys_id
)
350 const struct __ftr_reg_entry
*ret
;
352 ret
= bsearch((const void *)(unsigned long)sys_id
,
354 ARRAY_SIZE(arm64_ftr_regs
),
355 sizeof(arm64_ftr_regs
[0]),
362 static u64
arm64_ftr_set_value(const struct arm64_ftr_bits
*ftrp
, s64 reg
,
365 u64 mask
= arm64_ftr_mask(ftrp
);
368 reg
|= (ftr_val
<< ftrp
->shift
) & mask
;
372 static s64
arm64_ftr_safe_value(const struct arm64_ftr_bits
*ftrp
, s64
new,
377 switch (ftrp
->type
) {
379 ret
= ftrp
->safe_val
;
382 ret
= new < cur
? new : cur
;
384 case FTR_HIGHER_SAFE
:
385 ret
= new > cur
? new : cur
;
394 static void __init
sort_ftr_regs(void)
398 /* Check that the array is sorted so that we can do the binary search */
399 for (i
= 1; i
< ARRAY_SIZE(arm64_ftr_regs
); i
++)
400 BUG_ON(arm64_ftr_regs
[i
].sys_id
< arm64_ftr_regs
[i
- 1].sys_id
);
404 * Initialise the CPU feature register from Boot CPU values.
405 * Also initiliases the strict_mask for the register.
407 static void __init
init_cpu_ftr_reg(u32 sys_reg
, u64
new)
410 u64 strict_mask
= ~0x0ULL
;
411 const struct arm64_ftr_bits
*ftrp
;
412 struct arm64_ftr_reg
*reg
= get_arm64_ftr_reg(sys_reg
);
416 for (ftrp
= reg
->ftr_bits
; ftrp
->width
; ftrp
++) {
417 s64 ftr_new
= arm64_ftr_value(ftrp
, new);
419 val
= arm64_ftr_set_value(ftrp
, val
, ftr_new
);
421 strict_mask
&= ~arm64_ftr_mask(ftrp
);
424 reg
->strict_mask
= strict_mask
;
427 void __init
init_cpu_features(struct cpuinfo_arm64
*info
)
429 /* Before we start using the tables, make sure it is sorted */
432 init_cpu_ftr_reg(SYS_CTR_EL0
, info
->reg_ctr
);
433 init_cpu_ftr_reg(SYS_DCZID_EL0
, info
->reg_dczid
);
434 init_cpu_ftr_reg(SYS_CNTFRQ_EL0
, info
->reg_cntfrq
);
435 init_cpu_ftr_reg(SYS_ID_AA64DFR0_EL1
, info
->reg_id_aa64dfr0
);
436 init_cpu_ftr_reg(SYS_ID_AA64DFR1_EL1
, info
->reg_id_aa64dfr1
);
437 init_cpu_ftr_reg(SYS_ID_AA64ISAR0_EL1
, info
->reg_id_aa64isar0
);
438 init_cpu_ftr_reg(SYS_ID_AA64ISAR1_EL1
, info
->reg_id_aa64isar1
);
439 init_cpu_ftr_reg(SYS_ID_AA64MMFR0_EL1
, info
->reg_id_aa64mmfr0
);
440 init_cpu_ftr_reg(SYS_ID_AA64MMFR1_EL1
, info
->reg_id_aa64mmfr1
);
441 init_cpu_ftr_reg(SYS_ID_AA64MMFR2_EL1
, info
->reg_id_aa64mmfr2
);
442 init_cpu_ftr_reg(SYS_ID_AA64PFR0_EL1
, info
->reg_id_aa64pfr0
);
443 init_cpu_ftr_reg(SYS_ID_AA64PFR1_EL1
, info
->reg_id_aa64pfr1
);
445 if (id_aa64pfr0_32bit_el0(info
->reg_id_aa64pfr0
)) {
446 init_cpu_ftr_reg(SYS_ID_DFR0_EL1
, info
->reg_id_dfr0
);
447 init_cpu_ftr_reg(SYS_ID_ISAR0_EL1
, info
->reg_id_isar0
);
448 init_cpu_ftr_reg(SYS_ID_ISAR1_EL1
, info
->reg_id_isar1
);
449 init_cpu_ftr_reg(SYS_ID_ISAR2_EL1
, info
->reg_id_isar2
);
450 init_cpu_ftr_reg(SYS_ID_ISAR3_EL1
, info
->reg_id_isar3
);
451 init_cpu_ftr_reg(SYS_ID_ISAR4_EL1
, info
->reg_id_isar4
);
452 init_cpu_ftr_reg(SYS_ID_ISAR5_EL1
, info
->reg_id_isar5
);
453 init_cpu_ftr_reg(SYS_ID_MMFR0_EL1
, info
->reg_id_mmfr0
);
454 init_cpu_ftr_reg(SYS_ID_MMFR1_EL1
, info
->reg_id_mmfr1
);
455 init_cpu_ftr_reg(SYS_ID_MMFR2_EL1
, info
->reg_id_mmfr2
);
456 init_cpu_ftr_reg(SYS_ID_MMFR3_EL1
, info
->reg_id_mmfr3
);
457 init_cpu_ftr_reg(SYS_ID_PFR0_EL1
, info
->reg_id_pfr0
);
458 init_cpu_ftr_reg(SYS_ID_PFR1_EL1
, info
->reg_id_pfr1
);
459 init_cpu_ftr_reg(SYS_MVFR0_EL1
, info
->reg_mvfr0
);
460 init_cpu_ftr_reg(SYS_MVFR1_EL1
, info
->reg_mvfr1
);
461 init_cpu_ftr_reg(SYS_MVFR2_EL1
, info
->reg_mvfr2
);
466 static void update_cpu_ftr_reg(struct arm64_ftr_reg
*reg
, u64
new)
468 const struct arm64_ftr_bits
*ftrp
;
470 for (ftrp
= reg
->ftr_bits
; ftrp
->width
; ftrp
++) {
471 s64 ftr_cur
= arm64_ftr_value(ftrp
, reg
->sys_val
);
472 s64 ftr_new
= arm64_ftr_value(ftrp
, new);
474 if (ftr_cur
== ftr_new
)
476 /* Find a safe value */
477 ftr_new
= arm64_ftr_safe_value(ftrp
, ftr_new
, ftr_cur
);
478 reg
->sys_val
= arm64_ftr_set_value(ftrp
, reg
->sys_val
, ftr_new
);
483 static int check_update_ftr_reg(u32 sys_id
, int cpu
, u64 val
, u64 boot
)
485 struct arm64_ftr_reg
*regp
= get_arm64_ftr_reg(sys_id
);
488 update_cpu_ftr_reg(regp
, val
);
489 if ((boot
& regp
->strict_mask
) == (val
& regp
->strict_mask
))
491 pr_warn("SANITY CHECK: Unexpected variation in %s. Boot CPU: %#016llx, CPU%d: %#016llx\n",
492 regp
->name
, boot
, cpu
, val
);
497 * Update system wide CPU feature registers with the values from a
498 * non-boot CPU. Also performs SANITY checks to make sure that there
499 * aren't any insane variations from that of the boot CPU.
501 void update_cpu_features(int cpu
,
502 struct cpuinfo_arm64
*info
,
503 struct cpuinfo_arm64
*boot
)
508 * The kernel can handle differing I-cache policies, but otherwise
509 * caches should look identical. Userspace JITs will make use of
512 taint
|= check_update_ftr_reg(SYS_CTR_EL0
, cpu
,
513 info
->reg_ctr
, boot
->reg_ctr
);
516 * Userspace may perform DC ZVA instructions. Mismatched block sizes
517 * could result in too much or too little memory being zeroed if a
518 * process is preempted and migrated between CPUs.
520 taint
|= check_update_ftr_reg(SYS_DCZID_EL0
, cpu
,
521 info
->reg_dczid
, boot
->reg_dczid
);
523 /* If different, timekeeping will be broken (especially with KVM) */
524 taint
|= check_update_ftr_reg(SYS_CNTFRQ_EL0
, cpu
,
525 info
->reg_cntfrq
, boot
->reg_cntfrq
);
528 * The kernel uses self-hosted debug features and expects CPUs to
529 * support identical debug features. We presently need CTX_CMPs, WRPs,
530 * and BRPs to be identical.
531 * ID_AA64DFR1 is currently RES0.
533 taint
|= check_update_ftr_reg(SYS_ID_AA64DFR0_EL1
, cpu
,
534 info
->reg_id_aa64dfr0
, boot
->reg_id_aa64dfr0
);
535 taint
|= check_update_ftr_reg(SYS_ID_AA64DFR1_EL1
, cpu
,
536 info
->reg_id_aa64dfr1
, boot
->reg_id_aa64dfr1
);
538 * Even in big.LITTLE, processors should be identical instruction-set
541 taint
|= check_update_ftr_reg(SYS_ID_AA64ISAR0_EL1
, cpu
,
542 info
->reg_id_aa64isar0
, boot
->reg_id_aa64isar0
);
543 taint
|= check_update_ftr_reg(SYS_ID_AA64ISAR1_EL1
, cpu
,
544 info
->reg_id_aa64isar1
, boot
->reg_id_aa64isar1
);
547 * Differing PARange support is fine as long as all peripherals and
548 * memory are mapped within the minimum PARange of all CPUs.
549 * Linux should not care about secure memory.
551 taint
|= check_update_ftr_reg(SYS_ID_AA64MMFR0_EL1
, cpu
,
552 info
->reg_id_aa64mmfr0
, boot
->reg_id_aa64mmfr0
);
553 taint
|= check_update_ftr_reg(SYS_ID_AA64MMFR1_EL1
, cpu
,
554 info
->reg_id_aa64mmfr1
, boot
->reg_id_aa64mmfr1
);
555 taint
|= check_update_ftr_reg(SYS_ID_AA64MMFR2_EL1
, cpu
,
556 info
->reg_id_aa64mmfr2
, boot
->reg_id_aa64mmfr2
);
559 * EL3 is not our concern.
560 * ID_AA64PFR1 is currently RES0.
562 taint
|= check_update_ftr_reg(SYS_ID_AA64PFR0_EL1
, cpu
,
563 info
->reg_id_aa64pfr0
, boot
->reg_id_aa64pfr0
);
564 taint
|= check_update_ftr_reg(SYS_ID_AA64PFR1_EL1
, cpu
,
565 info
->reg_id_aa64pfr1
, boot
->reg_id_aa64pfr1
);
568 * If we have AArch32, we care about 32-bit features for compat.
569 * If the system doesn't support AArch32, don't update them.
571 if (id_aa64pfr0_32bit_el0(read_system_reg(SYS_ID_AA64PFR0_EL1
)) &&
572 id_aa64pfr0_32bit_el0(info
->reg_id_aa64pfr0
)) {
574 taint
|= check_update_ftr_reg(SYS_ID_DFR0_EL1
, cpu
,
575 info
->reg_id_dfr0
, boot
->reg_id_dfr0
);
576 taint
|= check_update_ftr_reg(SYS_ID_ISAR0_EL1
, cpu
,
577 info
->reg_id_isar0
, boot
->reg_id_isar0
);
578 taint
|= check_update_ftr_reg(SYS_ID_ISAR1_EL1
, cpu
,
579 info
->reg_id_isar1
, boot
->reg_id_isar1
);
580 taint
|= check_update_ftr_reg(SYS_ID_ISAR2_EL1
, cpu
,
581 info
->reg_id_isar2
, boot
->reg_id_isar2
);
582 taint
|= check_update_ftr_reg(SYS_ID_ISAR3_EL1
, cpu
,
583 info
->reg_id_isar3
, boot
->reg_id_isar3
);
584 taint
|= check_update_ftr_reg(SYS_ID_ISAR4_EL1
, cpu
,
585 info
->reg_id_isar4
, boot
->reg_id_isar4
);
586 taint
|= check_update_ftr_reg(SYS_ID_ISAR5_EL1
, cpu
,
587 info
->reg_id_isar5
, boot
->reg_id_isar5
);
590 * Regardless of the value of the AuxReg field, the AIFSR, ADFSR, and
591 * ACTLR formats could differ across CPUs and therefore would have to
592 * be trapped for virtualization anyway.
594 taint
|= check_update_ftr_reg(SYS_ID_MMFR0_EL1
, cpu
,
595 info
->reg_id_mmfr0
, boot
->reg_id_mmfr0
);
596 taint
|= check_update_ftr_reg(SYS_ID_MMFR1_EL1
, cpu
,
597 info
->reg_id_mmfr1
, boot
->reg_id_mmfr1
);
598 taint
|= check_update_ftr_reg(SYS_ID_MMFR2_EL1
, cpu
,
599 info
->reg_id_mmfr2
, boot
->reg_id_mmfr2
);
600 taint
|= check_update_ftr_reg(SYS_ID_MMFR3_EL1
, cpu
,
601 info
->reg_id_mmfr3
, boot
->reg_id_mmfr3
);
602 taint
|= check_update_ftr_reg(SYS_ID_PFR0_EL1
, cpu
,
603 info
->reg_id_pfr0
, boot
->reg_id_pfr0
);
604 taint
|= check_update_ftr_reg(SYS_ID_PFR1_EL1
, cpu
,
605 info
->reg_id_pfr1
, boot
->reg_id_pfr1
);
606 taint
|= check_update_ftr_reg(SYS_MVFR0_EL1
, cpu
,
607 info
->reg_mvfr0
, boot
->reg_mvfr0
);
608 taint
|= check_update_ftr_reg(SYS_MVFR1_EL1
, cpu
,
609 info
->reg_mvfr1
, boot
->reg_mvfr1
);
610 taint
|= check_update_ftr_reg(SYS_MVFR2_EL1
, cpu
,
611 info
->reg_mvfr2
, boot
->reg_mvfr2
);
615 * Mismatched CPU features are a recipe for disaster. Don't even
616 * pretend to support them.
618 WARN_TAINT_ONCE(taint
, TAINT_CPU_OUT_OF_SPEC
,
619 "Unsupported CPU feature variation.\n");
622 u64
read_system_reg(u32 id
)
624 struct arm64_ftr_reg
*regp
= get_arm64_ftr_reg(id
);
626 /* We shouldn't get a request for an unsupported register */
628 return regp
->sys_val
;
632 * __raw_read_system_reg() - Used by a STARTING cpu before cpuinfo is populated.
633 * Read the system register on the current CPU
635 static u64
__raw_read_system_reg(u32 sys_id
)
638 case SYS_ID_PFR0_EL1
: return read_cpuid(ID_PFR0_EL1
);
639 case SYS_ID_PFR1_EL1
: return read_cpuid(ID_PFR1_EL1
);
640 case SYS_ID_DFR0_EL1
: return read_cpuid(ID_DFR0_EL1
);
641 case SYS_ID_MMFR0_EL1
: return read_cpuid(ID_MMFR0_EL1
);
642 case SYS_ID_MMFR1_EL1
: return read_cpuid(ID_MMFR1_EL1
);
643 case SYS_ID_MMFR2_EL1
: return read_cpuid(ID_MMFR2_EL1
);
644 case SYS_ID_MMFR3_EL1
: return read_cpuid(ID_MMFR3_EL1
);
645 case SYS_ID_ISAR0_EL1
: return read_cpuid(ID_ISAR0_EL1
);
646 case SYS_ID_ISAR1_EL1
: return read_cpuid(ID_ISAR1_EL1
);
647 case SYS_ID_ISAR2_EL1
: return read_cpuid(ID_ISAR2_EL1
);
648 case SYS_ID_ISAR3_EL1
: return read_cpuid(ID_ISAR3_EL1
);
649 case SYS_ID_ISAR4_EL1
: return read_cpuid(ID_ISAR4_EL1
);
650 case SYS_ID_ISAR5_EL1
: return read_cpuid(ID_ISAR4_EL1
);
651 case SYS_MVFR0_EL1
: return read_cpuid(MVFR0_EL1
);
652 case SYS_MVFR1_EL1
: return read_cpuid(MVFR1_EL1
);
653 case SYS_MVFR2_EL1
: return read_cpuid(MVFR2_EL1
);
655 case SYS_ID_AA64PFR0_EL1
: return read_cpuid(ID_AA64PFR0_EL1
);
656 case SYS_ID_AA64PFR1_EL1
: return read_cpuid(ID_AA64PFR0_EL1
);
657 case SYS_ID_AA64DFR0_EL1
: return read_cpuid(ID_AA64DFR0_EL1
);
658 case SYS_ID_AA64DFR1_EL1
: return read_cpuid(ID_AA64DFR0_EL1
);
659 case SYS_ID_AA64MMFR0_EL1
: return read_cpuid(ID_AA64MMFR0_EL1
);
660 case SYS_ID_AA64MMFR1_EL1
: return read_cpuid(ID_AA64MMFR1_EL1
);
661 case SYS_ID_AA64MMFR2_EL1
: return read_cpuid(ID_AA64MMFR2_EL1
);
662 case SYS_ID_AA64ISAR0_EL1
: return read_cpuid(ID_AA64ISAR0_EL1
);
663 case SYS_ID_AA64ISAR1_EL1
: return read_cpuid(ID_AA64ISAR1_EL1
);
665 case SYS_CNTFRQ_EL0
: return read_cpuid(CNTFRQ_EL0
);
666 case SYS_CTR_EL0
: return read_cpuid(CTR_EL0
);
667 case SYS_DCZID_EL0
: return read_cpuid(DCZID_EL0
);
674 #include <linux/irqchip/arm-gic-v3.h>
677 feature_matches(u64 reg
, const struct arm64_cpu_capabilities
*entry
)
679 int val
= cpuid_feature_extract_field(reg
, entry
->field_pos
, entry
->sign
);
681 return val
>= entry
->min_field_value
;
685 has_cpuid_feature(const struct arm64_cpu_capabilities
*entry
, int scope
)
689 WARN_ON(scope
== SCOPE_LOCAL_CPU
&& preemptible());
690 if (scope
== SCOPE_SYSTEM
)
691 val
= read_system_reg(entry
->sys_reg
);
693 val
= __raw_read_system_reg(entry
->sys_reg
);
695 return feature_matches(val
, entry
);
698 static bool has_useable_gicv3_cpuif(const struct arm64_cpu_capabilities
*entry
, int scope
)
702 if (!has_cpuid_feature(entry
, scope
))
705 has_sre
= gic_enable_sre();
707 pr_warn_once("%s present but disabled by higher exception level\n",
713 static bool has_no_hw_prefetch(const struct arm64_cpu_capabilities
*entry
, int __unused
)
715 u32 midr
= read_cpuid_id();
718 /* Cavium ThunderX pass 1.x and 2.x */
720 rv_max
= (1 << MIDR_VARIANT_SHIFT
) | MIDR_REVISION_MASK
;
722 return MIDR_IS_CPU_MODEL_RANGE(midr
, MIDR_THUNDERX
, rv_min
, rv_max
);
725 static bool runs_at_el2(const struct arm64_cpu_capabilities
*entry
, int __unused
)
727 return is_kernel_in_hyp_mode();
730 static bool hyp_offset_low(const struct arm64_cpu_capabilities
*entry
,
733 phys_addr_t idmap_addr
= virt_to_phys(__hyp_idmap_text_start
);
736 * Activate the lower HYP offset only if:
737 * - the idmap doesn't clash with it,
738 * - the kernel is not running at EL2.
740 return idmap_addr
> GENMASK(VA_BITS
- 2, 0) && !is_kernel_in_hyp_mode();
743 static const struct arm64_cpu_capabilities arm64_features
[] = {
745 .desc
= "GIC system register CPU interface",
746 .capability
= ARM64_HAS_SYSREG_GIC_CPUIF
,
747 .def_scope
= SCOPE_SYSTEM
,
748 .matches
= has_useable_gicv3_cpuif
,
749 .sys_reg
= SYS_ID_AA64PFR0_EL1
,
750 .field_pos
= ID_AA64PFR0_GIC_SHIFT
,
751 .sign
= FTR_UNSIGNED
,
752 .min_field_value
= 1,
754 #ifdef CONFIG_ARM64_PAN
756 .desc
= "Privileged Access Never",
757 .capability
= ARM64_HAS_PAN
,
758 .def_scope
= SCOPE_SYSTEM
,
759 .matches
= has_cpuid_feature
,
760 .sys_reg
= SYS_ID_AA64MMFR1_EL1
,
761 .field_pos
= ID_AA64MMFR1_PAN_SHIFT
,
762 .sign
= FTR_UNSIGNED
,
763 .min_field_value
= 1,
764 .enable
= cpu_enable_pan
,
766 #endif /* CONFIG_ARM64_PAN */
767 #if defined(CONFIG_AS_LSE) && defined(CONFIG_ARM64_LSE_ATOMICS)
769 .desc
= "LSE atomic instructions",
770 .capability
= ARM64_HAS_LSE_ATOMICS
,
771 .def_scope
= SCOPE_SYSTEM
,
772 .matches
= has_cpuid_feature
,
773 .sys_reg
= SYS_ID_AA64ISAR0_EL1
,
774 .field_pos
= ID_AA64ISAR0_ATOMICS_SHIFT
,
775 .sign
= FTR_UNSIGNED
,
776 .min_field_value
= 2,
778 #endif /* CONFIG_AS_LSE && CONFIG_ARM64_LSE_ATOMICS */
780 .desc
= "Software prefetching using PRFM",
781 .capability
= ARM64_HAS_NO_HW_PREFETCH
,
782 .def_scope
= SCOPE_SYSTEM
,
783 .matches
= has_no_hw_prefetch
,
785 #ifdef CONFIG_ARM64_UAO
787 .desc
= "User Access Override",
788 .capability
= ARM64_HAS_UAO
,
789 .def_scope
= SCOPE_SYSTEM
,
790 .matches
= has_cpuid_feature
,
791 .sys_reg
= SYS_ID_AA64MMFR2_EL1
,
792 .field_pos
= ID_AA64MMFR2_UAO_SHIFT
,
793 .min_field_value
= 1,
794 .enable
= cpu_enable_uao
,
796 #endif /* CONFIG_ARM64_UAO */
797 #ifdef CONFIG_ARM64_PAN
799 .capability
= ARM64_ALT_PAN_NOT_UAO
,
800 .def_scope
= SCOPE_SYSTEM
,
801 .matches
= cpufeature_pan_not_uao
,
803 #endif /* CONFIG_ARM64_PAN */
805 .desc
= "Virtualization Host Extensions",
806 .capability
= ARM64_HAS_VIRT_HOST_EXTN
,
807 .def_scope
= SCOPE_SYSTEM
,
808 .matches
= runs_at_el2
,
811 .desc
= "32-bit EL0 Support",
812 .capability
= ARM64_HAS_32BIT_EL0
,
813 .def_scope
= SCOPE_SYSTEM
,
814 .matches
= has_cpuid_feature
,
815 .sys_reg
= SYS_ID_AA64PFR0_EL1
,
816 .sign
= FTR_UNSIGNED
,
817 .field_pos
= ID_AA64PFR0_EL0_SHIFT
,
818 .min_field_value
= ID_AA64PFR0_EL0_32BIT_64BIT
,
821 .desc
= "Reduced HYP mapping offset",
822 .capability
= ARM64_HYP_OFFSET_LOW
,
823 .def_scope
= SCOPE_SYSTEM
,
824 .matches
= hyp_offset_low
,
829 #define HWCAP_CAP(reg, field, s, min_value, type, cap) \
832 .def_scope = SCOPE_SYSTEM, \
833 .matches = has_cpuid_feature, \
835 .field_pos = field, \
837 .min_field_value = min_value, \
838 .hwcap_type = type, \
842 static const struct arm64_cpu_capabilities arm64_elf_hwcaps
[] = {
843 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1
, ID_AA64ISAR0_AES_SHIFT
, FTR_UNSIGNED
, 2, CAP_HWCAP
, HWCAP_PMULL
),
844 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1
, ID_AA64ISAR0_AES_SHIFT
, FTR_UNSIGNED
, 1, CAP_HWCAP
, HWCAP_AES
),
845 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1
, ID_AA64ISAR0_SHA1_SHIFT
, FTR_UNSIGNED
, 1, CAP_HWCAP
, HWCAP_SHA1
),
846 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1
, ID_AA64ISAR0_SHA2_SHIFT
, FTR_UNSIGNED
, 1, CAP_HWCAP
, HWCAP_SHA2
),
847 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1
, ID_AA64ISAR0_CRC32_SHIFT
, FTR_UNSIGNED
, 1, CAP_HWCAP
, HWCAP_CRC32
),
848 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1
, ID_AA64ISAR0_ATOMICS_SHIFT
, FTR_UNSIGNED
, 2, CAP_HWCAP
, HWCAP_ATOMICS
),
849 HWCAP_CAP(SYS_ID_AA64PFR0_EL1
, ID_AA64PFR0_FP_SHIFT
, FTR_SIGNED
, 0, CAP_HWCAP
, HWCAP_FP
),
850 HWCAP_CAP(SYS_ID_AA64PFR0_EL1
, ID_AA64PFR0_FP_SHIFT
, FTR_SIGNED
, 1, CAP_HWCAP
, HWCAP_FPHP
),
851 HWCAP_CAP(SYS_ID_AA64PFR0_EL1
, ID_AA64PFR0_ASIMD_SHIFT
, FTR_SIGNED
, 0, CAP_HWCAP
, HWCAP_ASIMD
),
852 HWCAP_CAP(SYS_ID_AA64PFR0_EL1
, ID_AA64PFR0_ASIMD_SHIFT
, FTR_SIGNED
, 1, CAP_HWCAP
, HWCAP_ASIMDHP
),
856 static const struct arm64_cpu_capabilities compat_elf_hwcaps
[] = {
858 HWCAP_CAP(SYS_ID_ISAR5_EL1
, ID_ISAR5_AES_SHIFT
, FTR_UNSIGNED
, 2, CAP_COMPAT_HWCAP2
, COMPAT_HWCAP2_PMULL
),
859 HWCAP_CAP(SYS_ID_ISAR5_EL1
, ID_ISAR5_AES_SHIFT
, FTR_UNSIGNED
, 1, CAP_COMPAT_HWCAP2
, COMPAT_HWCAP2_AES
),
860 HWCAP_CAP(SYS_ID_ISAR5_EL1
, ID_ISAR5_SHA1_SHIFT
, FTR_UNSIGNED
, 1, CAP_COMPAT_HWCAP2
, COMPAT_HWCAP2_SHA1
),
861 HWCAP_CAP(SYS_ID_ISAR5_EL1
, ID_ISAR5_SHA2_SHIFT
, FTR_UNSIGNED
, 1, CAP_COMPAT_HWCAP2
, COMPAT_HWCAP2_SHA2
),
862 HWCAP_CAP(SYS_ID_ISAR5_EL1
, ID_ISAR5_CRC32_SHIFT
, FTR_UNSIGNED
, 1, CAP_COMPAT_HWCAP2
, COMPAT_HWCAP2_CRC32
),
867 static void __init
cap_set_elf_hwcap(const struct arm64_cpu_capabilities
*cap
)
869 switch (cap
->hwcap_type
) {
871 elf_hwcap
|= cap
->hwcap
;
874 case CAP_COMPAT_HWCAP
:
875 compat_elf_hwcap
|= (u32
)cap
->hwcap
;
877 case CAP_COMPAT_HWCAP2
:
878 compat_elf_hwcap2
|= (u32
)cap
->hwcap
;
887 /* Check if we have a particular HWCAP enabled */
888 static bool cpus_have_elf_hwcap(const struct arm64_cpu_capabilities
*cap
)
892 switch (cap
->hwcap_type
) {
894 rc
= (elf_hwcap
& cap
->hwcap
) != 0;
897 case CAP_COMPAT_HWCAP
:
898 rc
= (compat_elf_hwcap
& (u32
)cap
->hwcap
) != 0;
900 case CAP_COMPAT_HWCAP2
:
901 rc
= (compat_elf_hwcap2
& (u32
)cap
->hwcap
) != 0;
912 static void __init
setup_elf_hwcaps(const struct arm64_cpu_capabilities
*hwcaps
)
914 for (; hwcaps
->matches
; hwcaps
++)
915 if (hwcaps
->matches(hwcaps
, hwcaps
->def_scope
))
916 cap_set_elf_hwcap(hwcaps
);
919 void update_cpu_capabilities(const struct arm64_cpu_capabilities
*caps
,
922 for (; caps
->matches
; caps
++) {
923 if (!caps
->matches(caps
, caps
->def_scope
))
926 if (!cpus_have_cap(caps
->capability
) && caps
->desc
)
927 pr_info("%s %s\n", info
, caps
->desc
);
928 cpus_set_cap(caps
->capability
);
933 * Run through the enabled capabilities and enable() it on all active
936 void __init
enable_cpu_capabilities(const struct arm64_cpu_capabilities
*caps
)
938 for (; caps
->matches
; caps
++)
939 if (caps
->enable
&& cpus_have_cap(caps
->capability
))
940 on_each_cpu(caps
->enable
, NULL
, true);
944 * Flag to indicate if we have computed the system wide
945 * capabilities based on the boot time active CPUs. This
946 * will be used to determine if a new booting CPU should
947 * go through the verification process to make sure that it
948 * supports the system capabilities, without using a hotplug
951 static bool sys_caps_initialised
;
953 static inline void set_sys_caps_initialised(void)
955 sys_caps_initialised
= true;
959 * Check for CPU features that are used in early boot
960 * based on the Boot CPU value.
962 static void check_early_cpu_features(void)
965 verify_cpu_asid_bits();
969 verify_local_elf_hwcaps(const struct arm64_cpu_capabilities
*caps
)
972 for (; caps
->matches
; caps
++)
973 if (cpus_have_elf_hwcap(caps
) && !caps
->matches(caps
, SCOPE_LOCAL_CPU
)) {
974 pr_crit("CPU%d: missing HWCAP: %s\n",
975 smp_processor_id(), caps
->desc
);
981 verify_local_cpu_features(const struct arm64_cpu_capabilities
*caps
)
983 for (; caps
->matches
; caps
++) {
984 if (!cpus_have_cap(caps
->capability
))
987 * If the new CPU misses an advertised feature, we cannot proceed
988 * further, park the cpu.
990 if (!caps
->matches(caps
, SCOPE_LOCAL_CPU
)) {
991 pr_crit("CPU%d: missing feature: %s\n",
992 smp_processor_id(), caps
->desc
);
1001 * Run through the enabled system capabilities and enable() it on this CPU.
1002 * The capabilities were decided based on the available CPUs at the boot time.
1003 * Any new CPU should match the system wide status of the capability. If the
1004 * new CPU doesn't have a capability which the system now has enabled, we
1005 * cannot do anything to fix it up and could cause unexpected failures. So
1008 void verify_local_cpu_capabilities(void)
1011 check_early_cpu_features();
1014 * If we haven't computed the system capabilities, there is nothing
1017 if (!sys_caps_initialised
)
1020 verify_local_cpu_errata();
1021 verify_local_cpu_features(arm64_features
);
1022 verify_local_elf_hwcaps(arm64_elf_hwcaps
);
1023 if (system_supports_32bit_el0())
1024 verify_local_elf_hwcaps(compat_elf_hwcaps
);
1027 static void __init
setup_feature_capabilities(void)
1029 update_cpu_capabilities(arm64_features
, "detected feature:");
1030 enable_cpu_capabilities(arm64_features
);
1034 * Check if the current CPU has a given feature capability.
1035 * Should be called from non-preemptible context.
1037 bool this_cpu_has_cap(unsigned int cap
)
1039 const struct arm64_cpu_capabilities
*caps
;
1041 if (WARN_ON(preemptible()))
1044 for (caps
= arm64_features
; caps
->desc
; caps
++)
1045 if (caps
->capability
== cap
&& caps
->matches
)
1046 return caps
->matches(caps
, SCOPE_LOCAL_CPU
);
1051 void __init
setup_cpu_features(void)
1056 /* Set the CPU feature capabilies */
1057 setup_feature_capabilities();
1058 enable_errata_workarounds();
1059 setup_elf_hwcaps(arm64_elf_hwcaps
);
1061 if (system_supports_32bit_el0())
1062 setup_elf_hwcaps(compat_elf_hwcaps
);
1064 /* Advertise that we have computed the system capabilities */
1065 set_sys_caps_initialised();
1068 * Check for sane CTR_EL0.CWG value.
1070 cwg
= cache_type_cwg();
1071 cls
= cache_line_size();
1073 pr_warn("No Cache Writeback Granule information, assuming cache line size %d\n",
1075 if (L1_CACHE_BYTES
< cls
)
1076 pr_warn("L1_CACHE_BYTES smaller than the Cache Writeback Granule (%d < %d)\n",
1077 L1_CACHE_BYTES
, cls
);
1080 static bool __maybe_unused
1081 cpufeature_pan_not_uao(const struct arm64_cpu_capabilities
*entry
, int __unused
)
1083 return (cpus_have_cap(ARM64_HAS_PAN
) && !cpus_have_cap(ARM64_HAS_UAO
));