2 * Contains CPU feature definitions
4 * Copyright (C) 2015 ARM Ltd.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program. If not, see <http://www.gnu.org/licenses/>.
19 #define pr_fmt(fmt) "CPU features: " fmt
21 #include <linux/bsearch.h>
22 #include <linux/sort.h>
23 #include <linux/types.h>
25 #include <asm/cpufeature.h>
26 #include <asm/cpu_ops.h>
27 #include <asm/mmu_context.h>
28 #include <asm/processor.h>
29 #include <asm/sysreg.h>
32 unsigned long elf_hwcap __read_mostly
;
33 EXPORT_SYMBOL_GPL(elf_hwcap
);
36 #define COMPAT_ELF_HWCAP_DEFAULT \
37 (COMPAT_HWCAP_HALF|COMPAT_HWCAP_THUMB|\
38 COMPAT_HWCAP_FAST_MULT|COMPAT_HWCAP_EDSP|\
39 COMPAT_HWCAP_TLS|COMPAT_HWCAP_VFP|\
40 COMPAT_HWCAP_VFPv3|COMPAT_HWCAP_VFPv4|\
41 COMPAT_HWCAP_NEON|COMPAT_HWCAP_IDIV|\
43 unsigned int compat_elf_hwcap __read_mostly
= COMPAT_ELF_HWCAP_DEFAULT
;
44 unsigned int compat_elf_hwcap2 __read_mostly
;
47 DECLARE_BITMAP(cpu_hwcaps
, ARM64_NCAPS
);
49 #define __ARM64_FTR_BITS(SIGNED, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
56 .safe_val = SAFE_VAL, \
59 /* Define a feature with unsigned values */
60 #define ARM64_FTR_BITS(STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
61 __ARM64_FTR_BITS(FTR_UNSIGNED, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL)
63 /* Define a feature with a signed value */
64 #define S_ARM64_FTR_BITS(STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
65 __ARM64_FTR_BITS(FTR_SIGNED, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL)
67 #define ARM64_FTR_END \
72 /* meta feature for alternatives */
73 static bool __maybe_unused
74 cpufeature_pan_not_uao(const struct arm64_cpu_capabilities
*entry
, int __unused
);
77 static struct arm64_ftr_bits ftr_id_aa64isar0
[] = {
78 ARM64_FTR_BITS(FTR_STRICT
, FTR_EXACT
, 32, 32, 0),
79 ARM64_FTR_BITS(FTR_STRICT
, FTR_EXACT
, ID_AA64ISAR0_RDM_SHIFT
, 4, 0),
80 ARM64_FTR_BITS(FTR_STRICT
, FTR_EXACT
, 24, 4, 0),
81 ARM64_FTR_BITS(FTR_STRICT
, FTR_LOWER_SAFE
, ID_AA64ISAR0_ATOMICS_SHIFT
, 4, 0),
82 ARM64_FTR_BITS(FTR_STRICT
, FTR_LOWER_SAFE
, ID_AA64ISAR0_CRC32_SHIFT
, 4, 0),
83 ARM64_FTR_BITS(FTR_STRICT
, FTR_LOWER_SAFE
, ID_AA64ISAR0_SHA2_SHIFT
, 4, 0),
84 ARM64_FTR_BITS(FTR_STRICT
, FTR_LOWER_SAFE
, ID_AA64ISAR0_SHA1_SHIFT
, 4, 0),
85 ARM64_FTR_BITS(FTR_STRICT
, FTR_LOWER_SAFE
, ID_AA64ISAR0_AES_SHIFT
, 4, 0),
86 ARM64_FTR_BITS(FTR_STRICT
, FTR_EXACT
, 0, 4, 0), /* RAZ */
90 static struct arm64_ftr_bits ftr_id_aa64pfr0
[] = {
91 ARM64_FTR_BITS(FTR_STRICT
, FTR_EXACT
, 32, 32, 0),
92 ARM64_FTR_BITS(FTR_STRICT
, FTR_EXACT
, 28, 4, 0),
93 ARM64_FTR_BITS(FTR_STRICT
, FTR_EXACT
, ID_AA64PFR0_GIC_SHIFT
, 4, 0),
94 S_ARM64_FTR_BITS(FTR_STRICT
, FTR_LOWER_SAFE
, ID_AA64PFR0_ASIMD_SHIFT
, 4, ID_AA64PFR0_ASIMD_NI
),
95 S_ARM64_FTR_BITS(FTR_STRICT
, FTR_LOWER_SAFE
, ID_AA64PFR0_FP_SHIFT
, 4, ID_AA64PFR0_FP_NI
),
96 /* Linux doesn't care about the EL3 */
97 ARM64_FTR_BITS(FTR_NONSTRICT
, FTR_EXACT
, ID_AA64PFR0_EL3_SHIFT
, 4, 0),
98 ARM64_FTR_BITS(FTR_STRICT
, FTR_EXACT
, ID_AA64PFR0_EL2_SHIFT
, 4, 0),
99 ARM64_FTR_BITS(FTR_STRICT
, FTR_EXACT
, ID_AA64PFR0_EL1_SHIFT
, 4, ID_AA64PFR0_EL1_64BIT_ONLY
),
100 ARM64_FTR_BITS(FTR_STRICT
, FTR_EXACT
, ID_AA64PFR0_EL0_SHIFT
, 4, ID_AA64PFR0_EL0_64BIT_ONLY
),
104 static struct arm64_ftr_bits ftr_id_aa64mmfr0
[] = {
105 ARM64_FTR_BITS(FTR_STRICT
, FTR_EXACT
, 32, 32, 0),
106 S_ARM64_FTR_BITS(FTR_STRICT
, FTR_EXACT
, ID_AA64MMFR0_TGRAN4_SHIFT
, 4, ID_AA64MMFR0_TGRAN4_NI
),
107 S_ARM64_FTR_BITS(FTR_STRICT
, FTR_EXACT
, ID_AA64MMFR0_TGRAN64_SHIFT
, 4, ID_AA64MMFR0_TGRAN64_NI
),
108 ARM64_FTR_BITS(FTR_STRICT
, FTR_EXACT
, ID_AA64MMFR0_TGRAN16_SHIFT
, 4, ID_AA64MMFR0_TGRAN16_NI
),
109 ARM64_FTR_BITS(FTR_STRICT
, FTR_EXACT
, ID_AA64MMFR0_BIGENDEL0_SHIFT
, 4, 0),
110 /* Linux shouldn't care about secure memory */
111 ARM64_FTR_BITS(FTR_NONSTRICT
, FTR_EXACT
, ID_AA64MMFR0_SNSMEM_SHIFT
, 4, 0),
112 ARM64_FTR_BITS(FTR_STRICT
, FTR_EXACT
, ID_AA64MMFR0_BIGENDEL_SHIFT
, 4, 0),
113 ARM64_FTR_BITS(FTR_STRICT
, FTR_EXACT
, ID_AA64MMFR0_ASID_SHIFT
, 4, 0),
115 * Differing PARange is fine as long as all peripherals and memory are mapped
116 * within the minimum PARange of all CPUs
118 ARM64_FTR_BITS(FTR_NONSTRICT
, FTR_LOWER_SAFE
, ID_AA64MMFR0_PARANGE_SHIFT
, 4, 0),
122 static struct arm64_ftr_bits ftr_id_aa64mmfr1
[] = {
123 ARM64_FTR_BITS(FTR_STRICT
, FTR_EXACT
, 32, 32, 0),
124 ARM64_FTR_BITS(FTR_STRICT
, FTR_LOWER_SAFE
, ID_AA64MMFR1_PAN_SHIFT
, 4, 0),
125 ARM64_FTR_BITS(FTR_STRICT
, FTR_EXACT
, ID_AA64MMFR1_LOR_SHIFT
, 4, 0),
126 ARM64_FTR_BITS(FTR_STRICT
, FTR_EXACT
, ID_AA64MMFR1_HPD_SHIFT
, 4, 0),
127 ARM64_FTR_BITS(FTR_STRICT
, FTR_EXACT
, ID_AA64MMFR1_VHE_SHIFT
, 4, 0),
128 ARM64_FTR_BITS(FTR_STRICT
, FTR_EXACT
, ID_AA64MMFR1_VMIDBITS_SHIFT
, 4, 0),
129 ARM64_FTR_BITS(FTR_STRICT
, FTR_EXACT
, ID_AA64MMFR1_HADBS_SHIFT
, 4, 0),
133 static struct arm64_ftr_bits ftr_id_aa64mmfr2
[] = {
134 ARM64_FTR_BITS(FTR_STRICT
, FTR_EXACT
, ID_AA64MMFR2_LVA_SHIFT
, 4, 0),
135 ARM64_FTR_BITS(FTR_STRICT
, FTR_EXACT
, ID_AA64MMFR2_IESB_SHIFT
, 4, 0),
136 ARM64_FTR_BITS(FTR_STRICT
, FTR_EXACT
, ID_AA64MMFR2_LSM_SHIFT
, 4, 0),
137 ARM64_FTR_BITS(FTR_STRICT
, FTR_EXACT
, ID_AA64MMFR2_UAO_SHIFT
, 4, 0),
138 ARM64_FTR_BITS(FTR_STRICT
, FTR_EXACT
, ID_AA64MMFR2_CNP_SHIFT
, 4, 0),
142 static struct arm64_ftr_bits ftr_ctr
[] = {
143 ARM64_FTR_BITS(FTR_STRICT
, FTR_EXACT
, 31, 1, 1), /* RAO */
144 ARM64_FTR_BITS(FTR_STRICT
, FTR_EXACT
, 28, 3, 0),
145 ARM64_FTR_BITS(FTR_STRICT
, FTR_HIGHER_SAFE
, 24, 4, 0), /* CWG */
146 ARM64_FTR_BITS(FTR_STRICT
, FTR_LOWER_SAFE
, 20, 4, 0), /* ERG */
147 ARM64_FTR_BITS(FTR_STRICT
, FTR_LOWER_SAFE
, 16, 4, 1), /* DminLine */
149 * Linux can handle differing I-cache policies. Userspace JITs will
150 * make use of *minLine
152 ARM64_FTR_BITS(FTR_NONSTRICT
, FTR_EXACT
, 14, 2, 0), /* L1Ip */
153 ARM64_FTR_BITS(FTR_STRICT
, FTR_EXACT
, 4, 10, 0), /* RAZ */
154 ARM64_FTR_BITS(FTR_STRICT
, FTR_LOWER_SAFE
, 0, 4, 0), /* IminLine */
158 static struct arm64_ftr_bits ftr_id_mmfr0
[] = {
159 S_ARM64_FTR_BITS(FTR_STRICT
, FTR_EXACT
, 28, 4, 0xf), /* InnerShr */
160 ARM64_FTR_BITS(FTR_STRICT
, FTR_EXACT
, 24, 4, 0), /* FCSE */
161 ARM64_FTR_BITS(FTR_NONSTRICT
, FTR_LOWER_SAFE
, 20, 4, 0), /* AuxReg */
162 ARM64_FTR_BITS(FTR_STRICT
, FTR_EXACT
, 16, 4, 0), /* TCM */
163 ARM64_FTR_BITS(FTR_STRICT
, FTR_EXACT
, 12, 4, 0), /* ShareLvl */
164 S_ARM64_FTR_BITS(FTR_STRICT
, FTR_EXACT
, 8, 4, 0xf), /* OuterShr */
165 ARM64_FTR_BITS(FTR_STRICT
, FTR_EXACT
, 4, 4, 0), /* PMSA */
166 ARM64_FTR_BITS(FTR_STRICT
, FTR_EXACT
, 0, 4, 0), /* VMSA */
170 static struct arm64_ftr_bits ftr_id_aa64dfr0
[] = {
171 ARM64_FTR_BITS(FTR_STRICT
, FTR_EXACT
, 32, 32, 0),
172 ARM64_FTR_BITS(FTR_STRICT
, FTR_LOWER_SAFE
, ID_AA64DFR0_CTX_CMPS_SHIFT
, 4, 0),
173 ARM64_FTR_BITS(FTR_STRICT
, FTR_LOWER_SAFE
, ID_AA64DFR0_WRPS_SHIFT
, 4, 0),
174 ARM64_FTR_BITS(FTR_STRICT
, FTR_LOWER_SAFE
, ID_AA64DFR0_BRPS_SHIFT
, 4, 0),
175 S_ARM64_FTR_BITS(FTR_STRICT
, FTR_EXACT
, ID_AA64DFR0_PMUVER_SHIFT
, 4, 0),
176 ARM64_FTR_BITS(FTR_STRICT
, FTR_EXACT
, ID_AA64DFR0_TRACEVER_SHIFT
, 4, 0),
177 ARM64_FTR_BITS(FTR_STRICT
, FTR_EXACT
, ID_AA64DFR0_DEBUGVER_SHIFT
, 4, 0x6),
181 static struct arm64_ftr_bits ftr_mvfr2
[] = {
182 ARM64_FTR_BITS(FTR_STRICT
, FTR_EXACT
, 8, 24, 0), /* RAZ */
183 ARM64_FTR_BITS(FTR_STRICT
, FTR_EXACT
, 4, 4, 0), /* FPMisc */
184 ARM64_FTR_BITS(FTR_STRICT
, FTR_EXACT
, 0, 4, 0), /* SIMDMisc */
188 static struct arm64_ftr_bits ftr_dczid
[] = {
189 ARM64_FTR_BITS(FTR_STRICT
, FTR_EXACT
, 5, 27, 0), /* RAZ */
190 ARM64_FTR_BITS(FTR_STRICT
, FTR_EXACT
, 4, 1, 1), /* DZP */
191 ARM64_FTR_BITS(FTR_STRICT
, FTR_LOWER_SAFE
, 0, 4, 0), /* BS */
196 static struct arm64_ftr_bits ftr_id_isar5
[] = {
197 ARM64_FTR_BITS(FTR_STRICT
, FTR_EXACT
, ID_ISAR5_RDM_SHIFT
, 4, 0),
198 ARM64_FTR_BITS(FTR_STRICT
, FTR_EXACT
, 20, 4, 0), /* RAZ */
199 ARM64_FTR_BITS(FTR_STRICT
, FTR_EXACT
, ID_ISAR5_CRC32_SHIFT
, 4, 0),
200 ARM64_FTR_BITS(FTR_STRICT
, FTR_EXACT
, ID_ISAR5_SHA2_SHIFT
, 4, 0),
201 ARM64_FTR_BITS(FTR_STRICT
, FTR_EXACT
, ID_ISAR5_SHA1_SHIFT
, 4, 0),
202 ARM64_FTR_BITS(FTR_STRICT
, FTR_EXACT
, ID_ISAR5_AES_SHIFT
, 4, 0),
203 ARM64_FTR_BITS(FTR_STRICT
, FTR_EXACT
, ID_ISAR5_SEVL_SHIFT
, 4, 0),
207 static struct arm64_ftr_bits ftr_id_mmfr4
[] = {
208 ARM64_FTR_BITS(FTR_STRICT
, FTR_EXACT
, 8, 24, 0), /* RAZ */
209 ARM64_FTR_BITS(FTR_STRICT
, FTR_EXACT
, 4, 4, 0), /* ac2 */
210 ARM64_FTR_BITS(FTR_STRICT
, FTR_EXACT
, 0, 4, 0), /* RAZ */
214 static struct arm64_ftr_bits ftr_id_pfr0
[] = {
215 ARM64_FTR_BITS(FTR_STRICT
, FTR_EXACT
, 16, 16, 0), /* RAZ */
216 ARM64_FTR_BITS(FTR_STRICT
, FTR_EXACT
, 12, 4, 0), /* State3 */
217 ARM64_FTR_BITS(FTR_STRICT
, FTR_EXACT
, 8, 4, 0), /* State2 */
218 ARM64_FTR_BITS(FTR_STRICT
, FTR_EXACT
, 4, 4, 0), /* State1 */
219 ARM64_FTR_BITS(FTR_STRICT
, FTR_EXACT
, 0, 4, 0), /* State0 */
223 static struct arm64_ftr_bits ftr_id_dfr0
[] = {
224 ARM64_FTR_BITS(FTR_STRICT
, FTR_LOWER_SAFE
, 28, 4, 0),
225 S_ARM64_FTR_BITS(FTR_STRICT
, FTR_LOWER_SAFE
, 24, 4, 0xf), /* PerfMon */
226 ARM64_FTR_BITS(FTR_STRICT
, FTR_LOWER_SAFE
, 20, 4, 0),
227 ARM64_FTR_BITS(FTR_STRICT
, FTR_LOWER_SAFE
, 16, 4, 0),
228 ARM64_FTR_BITS(FTR_STRICT
, FTR_LOWER_SAFE
, 12, 4, 0),
229 ARM64_FTR_BITS(FTR_STRICT
, FTR_LOWER_SAFE
, 8, 4, 0),
230 ARM64_FTR_BITS(FTR_STRICT
, FTR_LOWER_SAFE
, 4, 4, 0),
231 ARM64_FTR_BITS(FTR_STRICT
, FTR_LOWER_SAFE
, 0, 4, 0),
236 * Common ftr bits for a 32bit register with all hidden, strict
237 * attributes, with 4bit feature fields and a default safe value of
238 * 0. Covers the following 32bit registers:
239 * id_isar[0-4], id_mmfr[1-3], id_pfr1, mvfr[0-1]
241 static struct arm64_ftr_bits ftr_generic_32bits
[] = {
242 ARM64_FTR_BITS(FTR_STRICT
, FTR_LOWER_SAFE
, 28, 4, 0),
243 ARM64_FTR_BITS(FTR_STRICT
, FTR_LOWER_SAFE
, 24, 4, 0),
244 ARM64_FTR_BITS(FTR_STRICT
, FTR_LOWER_SAFE
, 20, 4, 0),
245 ARM64_FTR_BITS(FTR_STRICT
, FTR_LOWER_SAFE
, 16, 4, 0),
246 ARM64_FTR_BITS(FTR_STRICT
, FTR_LOWER_SAFE
, 12, 4, 0),
247 ARM64_FTR_BITS(FTR_STRICT
, FTR_LOWER_SAFE
, 8, 4, 0),
248 ARM64_FTR_BITS(FTR_STRICT
, FTR_LOWER_SAFE
, 4, 4, 0),
249 ARM64_FTR_BITS(FTR_STRICT
, FTR_LOWER_SAFE
, 0, 4, 0),
253 static struct arm64_ftr_bits ftr_generic
[] = {
254 ARM64_FTR_BITS(FTR_STRICT
, FTR_EXACT
, 0, 64, 0),
258 static struct arm64_ftr_bits ftr_generic32
[] = {
259 ARM64_FTR_BITS(FTR_STRICT
, FTR_EXACT
, 0, 32, 0),
263 static struct arm64_ftr_bits ftr_aa64raz
[] = {
264 ARM64_FTR_BITS(FTR_STRICT
, FTR_EXACT
, 0, 64, 0),
268 #define ARM64_FTR_REG(id, table) \
272 .ftr_bits = &((table)[0]), \
275 static struct arm64_ftr_reg arm64_ftr_regs
[] = {
277 /* Op1 = 0, CRn = 0, CRm = 1 */
278 ARM64_FTR_REG(SYS_ID_PFR0_EL1
, ftr_id_pfr0
),
279 ARM64_FTR_REG(SYS_ID_PFR1_EL1
, ftr_generic_32bits
),
280 ARM64_FTR_REG(SYS_ID_DFR0_EL1
, ftr_id_dfr0
),
281 ARM64_FTR_REG(SYS_ID_MMFR0_EL1
, ftr_id_mmfr0
),
282 ARM64_FTR_REG(SYS_ID_MMFR1_EL1
, ftr_generic_32bits
),
283 ARM64_FTR_REG(SYS_ID_MMFR2_EL1
, ftr_generic_32bits
),
284 ARM64_FTR_REG(SYS_ID_MMFR3_EL1
, ftr_generic_32bits
),
286 /* Op1 = 0, CRn = 0, CRm = 2 */
287 ARM64_FTR_REG(SYS_ID_ISAR0_EL1
, ftr_generic_32bits
),
288 ARM64_FTR_REG(SYS_ID_ISAR1_EL1
, ftr_generic_32bits
),
289 ARM64_FTR_REG(SYS_ID_ISAR2_EL1
, ftr_generic_32bits
),
290 ARM64_FTR_REG(SYS_ID_ISAR3_EL1
, ftr_generic_32bits
),
291 ARM64_FTR_REG(SYS_ID_ISAR4_EL1
, ftr_generic_32bits
),
292 ARM64_FTR_REG(SYS_ID_ISAR5_EL1
, ftr_id_isar5
),
293 ARM64_FTR_REG(SYS_ID_MMFR4_EL1
, ftr_id_mmfr4
),
295 /* Op1 = 0, CRn = 0, CRm = 3 */
296 ARM64_FTR_REG(SYS_MVFR0_EL1
, ftr_generic_32bits
),
297 ARM64_FTR_REG(SYS_MVFR1_EL1
, ftr_generic_32bits
),
298 ARM64_FTR_REG(SYS_MVFR2_EL1
, ftr_mvfr2
),
300 /* Op1 = 0, CRn = 0, CRm = 4 */
301 ARM64_FTR_REG(SYS_ID_AA64PFR0_EL1
, ftr_id_aa64pfr0
),
302 ARM64_FTR_REG(SYS_ID_AA64PFR1_EL1
, ftr_aa64raz
),
304 /* Op1 = 0, CRn = 0, CRm = 5 */
305 ARM64_FTR_REG(SYS_ID_AA64DFR0_EL1
, ftr_id_aa64dfr0
),
306 ARM64_FTR_REG(SYS_ID_AA64DFR1_EL1
, ftr_generic
),
308 /* Op1 = 0, CRn = 0, CRm = 6 */
309 ARM64_FTR_REG(SYS_ID_AA64ISAR0_EL1
, ftr_id_aa64isar0
),
310 ARM64_FTR_REG(SYS_ID_AA64ISAR1_EL1
, ftr_aa64raz
),
312 /* Op1 = 0, CRn = 0, CRm = 7 */
313 ARM64_FTR_REG(SYS_ID_AA64MMFR0_EL1
, ftr_id_aa64mmfr0
),
314 ARM64_FTR_REG(SYS_ID_AA64MMFR1_EL1
, ftr_id_aa64mmfr1
),
315 ARM64_FTR_REG(SYS_ID_AA64MMFR2_EL1
, ftr_id_aa64mmfr2
),
317 /* Op1 = 3, CRn = 0, CRm = 0 */
318 ARM64_FTR_REG(SYS_CTR_EL0
, ftr_ctr
),
319 ARM64_FTR_REG(SYS_DCZID_EL0
, ftr_dczid
),
321 /* Op1 = 3, CRn = 14, CRm = 0 */
322 ARM64_FTR_REG(SYS_CNTFRQ_EL0
, ftr_generic32
),
325 static int search_cmp_ftr_reg(const void *id
, const void *regp
)
327 return (int)(unsigned long)id
- (int)((const struct arm64_ftr_reg
*)regp
)->sys_id
;
331 * get_arm64_ftr_reg - Lookup a feature register entry using its
332 * sys_reg() encoding. With the array arm64_ftr_regs sorted in the
333 * ascending order of sys_id , we use binary search to find a matching
336 * returns - Upon success, matching ftr_reg entry for id.
337 * - NULL on failure. It is upto the caller to decide
338 * the impact of a failure.
340 static struct arm64_ftr_reg
*get_arm64_ftr_reg(u32 sys_id
)
342 return bsearch((const void *)(unsigned long)sys_id
,
344 ARRAY_SIZE(arm64_ftr_regs
),
345 sizeof(arm64_ftr_regs
[0]),
349 static u64
arm64_ftr_set_value(struct arm64_ftr_bits
*ftrp
, s64 reg
, s64 ftr_val
)
351 u64 mask
= arm64_ftr_mask(ftrp
);
354 reg
|= (ftr_val
<< ftrp
->shift
) & mask
;
358 static s64
arm64_ftr_safe_value(struct arm64_ftr_bits
*ftrp
, s64
new, s64 cur
)
362 switch (ftrp
->type
) {
364 ret
= ftrp
->safe_val
;
367 ret
= new < cur
? new : cur
;
369 case FTR_HIGHER_SAFE
:
370 ret
= new > cur
? new : cur
;
379 static int __init
sort_cmp_ftr_regs(const void *a
, const void *b
)
381 return ((const struct arm64_ftr_reg
*)a
)->sys_id
-
382 ((const struct arm64_ftr_reg
*)b
)->sys_id
;
385 static void __init
swap_ftr_regs(void *a
, void *b
, int size
)
387 struct arm64_ftr_reg tmp
= *(struct arm64_ftr_reg
*)a
;
388 *(struct arm64_ftr_reg
*)a
= *(struct arm64_ftr_reg
*)b
;
389 *(struct arm64_ftr_reg
*)b
= tmp
;
392 static void __init
sort_ftr_regs(void)
394 /* Keep the array sorted so that we can do the binary search */
396 ARRAY_SIZE(arm64_ftr_regs
),
397 sizeof(arm64_ftr_regs
[0]),
403 * Initialise the CPU feature register from Boot CPU values.
404 * Also initiliases the strict_mask for the register.
406 static void __init
init_cpu_ftr_reg(u32 sys_reg
, u64
new)
409 u64 strict_mask
= ~0x0ULL
;
410 struct arm64_ftr_bits
*ftrp
;
411 struct arm64_ftr_reg
*reg
= get_arm64_ftr_reg(sys_reg
);
415 for (ftrp
= reg
->ftr_bits
; ftrp
->width
; ftrp
++) {
416 s64 ftr_new
= arm64_ftr_value(ftrp
, new);
418 val
= arm64_ftr_set_value(ftrp
, val
, ftr_new
);
420 strict_mask
&= ~arm64_ftr_mask(ftrp
);
423 reg
->strict_mask
= strict_mask
;
426 void __init
init_cpu_features(struct cpuinfo_arm64
*info
)
428 /* Before we start using the tables, make sure it is sorted */
431 init_cpu_ftr_reg(SYS_CTR_EL0
, info
->reg_ctr
);
432 init_cpu_ftr_reg(SYS_DCZID_EL0
, info
->reg_dczid
);
433 init_cpu_ftr_reg(SYS_CNTFRQ_EL0
, info
->reg_cntfrq
);
434 init_cpu_ftr_reg(SYS_ID_AA64DFR0_EL1
, info
->reg_id_aa64dfr0
);
435 init_cpu_ftr_reg(SYS_ID_AA64DFR1_EL1
, info
->reg_id_aa64dfr1
);
436 init_cpu_ftr_reg(SYS_ID_AA64ISAR0_EL1
, info
->reg_id_aa64isar0
);
437 init_cpu_ftr_reg(SYS_ID_AA64ISAR1_EL1
, info
->reg_id_aa64isar1
);
438 init_cpu_ftr_reg(SYS_ID_AA64MMFR0_EL1
, info
->reg_id_aa64mmfr0
);
439 init_cpu_ftr_reg(SYS_ID_AA64MMFR1_EL1
, info
->reg_id_aa64mmfr1
);
440 init_cpu_ftr_reg(SYS_ID_AA64MMFR2_EL1
, info
->reg_id_aa64mmfr2
);
441 init_cpu_ftr_reg(SYS_ID_AA64PFR0_EL1
, info
->reg_id_aa64pfr0
);
442 init_cpu_ftr_reg(SYS_ID_AA64PFR1_EL1
, info
->reg_id_aa64pfr1
);
444 if (id_aa64pfr0_32bit_el0(info
->reg_id_aa64pfr0
)) {
445 init_cpu_ftr_reg(SYS_ID_DFR0_EL1
, info
->reg_id_dfr0
);
446 init_cpu_ftr_reg(SYS_ID_ISAR0_EL1
, info
->reg_id_isar0
);
447 init_cpu_ftr_reg(SYS_ID_ISAR1_EL1
, info
->reg_id_isar1
);
448 init_cpu_ftr_reg(SYS_ID_ISAR2_EL1
, info
->reg_id_isar2
);
449 init_cpu_ftr_reg(SYS_ID_ISAR3_EL1
, info
->reg_id_isar3
);
450 init_cpu_ftr_reg(SYS_ID_ISAR4_EL1
, info
->reg_id_isar4
);
451 init_cpu_ftr_reg(SYS_ID_ISAR5_EL1
, info
->reg_id_isar5
);
452 init_cpu_ftr_reg(SYS_ID_MMFR0_EL1
, info
->reg_id_mmfr0
);
453 init_cpu_ftr_reg(SYS_ID_MMFR1_EL1
, info
->reg_id_mmfr1
);
454 init_cpu_ftr_reg(SYS_ID_MMFR2_EL1
, info
->reg_id_mmfr2
);
455 init_cpu_ftr_reg(SYS_ID_MMFR3_EL1
, info
->reg_id_mmfr3
);
456 init_cpu_ftr_reg(SYS_ID_PFR0_EL1
, info
->reg_id_pfr0
);
457 init_cpu_ftr_reg(SYS_ID_PFR1_EL1
, info
->reg_id_pfr1
);
458 init_cpu_ftr_reg(SYS_MVFR0_EL1
, info
->reg_mvfr0
);
459 init_cpu_ftr_reg(SYS_MVFR1_EL1
, info
->reg_mvfr1
);
460 init_cpu_ftr_reg(SYS_MVFR2_EL1
, info
->reg_mvfr2
);
465 static void update_cpu_ftr_reg(struct arm64_ftr_reg
*reg
, u64
new)
467 struct arm64_ftr_bits
*ftrp
;
469 for (ftrp
= reg
->ftr_bits
; ftrp
->width
; ftrp
++) {
470 s64 ftr_cur
= arm64_ftr_value(ftrp
, reg
->sys_val
);
471 s64 ftr_new
= arm64_ftr_value(ftrp
, new);
473 if (ftr_cur
== ftr_new
)
475 /* Find a safe value */
476 ftr_new
= arm64_ftr_safe_value(ftrp
, ftr_new
, ftr_cur
);
477 reg
->sys_val
= arm64_ftr_set_value(ftrp
, reg
->sys_val
, ftr_new
);
482 static int check_update_ftr_reg(u32 sys_id
, int cpu
, u64 val
, u64 boot
)
484 struct arm64_ftr_reg
*regp
= get_arm64_ftr_reg(sys_id
);
487 update_cpu_ftr_reg(regp
, val
);
488 if ((boot
& regp
->strict_mask
) == (val
& regp
->strict_mask
))
490 pr_warn("SANITY CHECK: Unexpected variation in %s. Boot CPU: %#016llx, CPU%d: %#016llx\n",
491 regp
->name
, boot
, cpu
, val
);
496 * Update system wide CPU feature registers with the values from a
497 * non-boot CPU. Also performs SANITY checks to make sure that there
498 * aren't any insane variations from that of the boot CPU.
500 void update_cpu_features(int cpu
,
501 struct cpuinfo_arm64
*info
,
502 struct cpuinfo_arm64
*boot
)
507 * The kernel can handle differing I-cache policies, but otherwise
508 * caches should look identical. Userspace JITs will make use of
511 taint
|= check_update_ftr_reg(SYS_CTR_EL0
, cpu
,
512 info
->reg_ctr
, boot
->reg_ctr
);
515 * Userspace may perform DC ZVA instructions. Mismatched block sizes
516 * could result in too much or too little memory being zeroed if a
517 * process is preempted and migrated between CPUs.
519 taint
|= check_update_ftr_reg(SYS_DCZID_EL0
, cpu
,
520 info
->reg_dczid
, boot
->reg_dczid
);
522 /* If different, timekeeping will be broken (especially with KVM) */
523 taint
|= check_update_ftr_reg(SYS_CNTFRQ_EL0
, cpu
,
524 info
->reg_cntfrq
, boot
->reg_cntfrq
);
527 * The kernel uses self-hosted debug features and expects CPUs to
528 * support identical debug features. We presently need CTX_CMPs, WRPs,
529 * and BRPs to be identical.
530 * ID_AA64DFR1 is currently RES0.
532 taint
|= check_update_ftr_reg(SYS_ID_AA64DFR0_EL1
, cpu
,
533 info
->reg_id_aa64dfr0
, boot
->reg_id_aa64dfr0
);
534 taint
|= check_update_ftr_reg(SYS_ID_AA64DFR1_EL1
, cpu
,
535 info
->reg_id_aa64dfr1
, boot
->reg_id_aa64dfr1
);
537 * Even in big.LITTLE, processors should be identical instruction-set
540 taint
|= check_update_ftr_reg(SYS_ID_AA64ISAR0_EL1
, cpu
,
541 info
->reg_id_aa64isar0
, boot
->reg_id_aa64isar0
);
542 taint
|= check_update_ftr_reg(SYS_ID_AA64ISAR1_EL1
, cpu
,
543 info
->reg_id_aa64isar1
, boot
->reg_id_aa64isar1
);
546 * Differing PARange support is fine as long as all peripherals and
547 * memory are mapped within the minimum PARange of all CPUs.
548 * Linux should not care about secure memory.
550 taint
|= check_update_ftr_reg(SYS_ID_AA64MMFR0_EL1
, cpu
,
551 info
->reg_id_aa64mmfr0
, boot
->reg_id_aa64mmfr0
);
552 taint
|= check_update_ftr_reg(SYS_ID_AA64MMFR1_EL1
, cpu
,
553 info
->reg_id_aa64mmfr1
, boot
->reg_id_aa64mmfr1
);
554 taint
|= check_update_ftr_reg(SYS_ID_AA64MMFR2_EL1
, cpu
,
555 info
->reg_id_aa64mmfr2
, boot
->reg_id_aa64mmfr2
);
558 * EL3 is not our concern.
559 * ID_AA64PFR1 is currently RES0.
561 taint
|= check_update_ftr_reg(SYS_ID_AA64PFR0_EL1
, cpu
,
562 info
->reg_id_aa64pfr0
, boot
->reg_id_aa64pfr0
);
563 taint
|= check_update_ftr_reg(SYS_ID_AA64PFR1_EL1
, cpu
,
564 info
->reg_id_aa64pfr1
, boot
->reg_id_aa64pfr1
);
567 * If we have AArch32, we care about 32-bit features for compat.
568 * If the system doesn't support AArch32, don't update them.
570 if (id_aa64pfr0_32bit_el0(read_system_reg(SYS_ID_AA64PFR0_EL1
)) &&
571 id_aa64pfr0_32bit_el0(info
->reg_id_aa64pfr0
)) {
573 taint
|= check_update_ftr_reg(SYS_ID_DFR0_EL1
, cpu
,
574 info
->reg_id_dfr0
, boot
->reg_id_dfr0
);
575 taint
|= check_update_ftr_reg(SYS_ID_ISAR0_EL1
, cpu
,
576 info
->reg_id_isar0
, boot
->reg_id_isar0
);
577 taint
|= check_update_ftr_reg(SYS_ID_ISAR1_EL1
, cpu
,
578 info
->reg_id_isar1
, boot
->reg_id_isar1
);
579 taint
|= check_update_ftr_reg(SYS_ID_ISAR2_EL1
, cpu
,
580 info
->reg_id_isar2
, boot
->reg_id_isar2
);
581 taint
|= check_update_ftr_reg(SYS_ID_ISAR3_EL1
, cpu
,
582 info
->reg_id_isar3
, boot
->reg_id_isar3
);
583 taint
|= check_update_ftr_reg(SYS_ID_ISAR4_EL1
, cpu
,
584 info
->reg_id_isar4
, boot
->reg_id_isar4
);
585 taint
|= check_update_ftr_reg(SYS_ID_ISAR5_EL1
, cpu
,
586 info
->reg_id_isar5
, boot
->reg_id_isar5
);
589 * Regardless of the value of the AuxReg field, the AIFSR, ADFSR, and
590 * ACTLR formats could differ across CPUs and therefore would have to
591 * be trapped for virtualization anyway.
593 taint
|= check_update_ftr_reg(SYS_ID_MMFR0_EL1
, cpu
,
594 info
->reg_id_mmfr0
, boot
->reg_id_mmfr0
);
595 taint
|= check_update_ftr_reg(SYS_ID_MMFR1_EL1
, cpu
,
596 info
->reg_id_mmfr1
, boot
->reg_id_mmfr1
);
597 taint
|= check_update_ftr_reg(SYS_ID_MMFR2_EL1
, cpu
,
598 info
->reg_id_mmfr2
, boot
->reg_id_mmfr2
);
599 taint
|= check_update_ftr_reg(SYS_ID_MMFR3_EL1
, cpu
,
600 info
->reg_id_mmfr3
, boot
->reg_id_mmfr3
);
601 taint
|= check_update_ftr_reg(SYS_ID_PFR0_EL1
, cpu
,
602 info
->reg_id_pfr0
, boot
->reg_id_pfr0
);
603 taint
|= check_update_ftr_reg(SYS_ID_PFR1_EL1
, cpu
,
604 info
->reg_id_pfr1
, boot
->reg_id_pfr1
);
605 taint
|= check_update_ftr_reg(SYS_MVFR0_EL1
, cpu
,
606 info
->reg_mvfr0
, boot
->reg_mvfr0
);
607 taint
|= check_update_ftr_reg(SYS_MVFR1_EL1
, cpu
,
608 info
->reg_mvfr1
, boot
->reg_mvfr1
);
609 taint
|= check_update_ftr_reg(SYS_MVFR2_EL1
, cpu
,
610 info
->reg_mvfr2
, boot
->reg_mvfr2
);
614 * Mismatched CPU features are a recipe for disaster. Don't even
615 * pretend to support them.
617 WARN_TAINT_ONCE(taint
, TAINT_CPU_OUT_OF_SPEC
,
618 "Unsupported CPU feature variation.\n");
621 u64
read_system_reg(u32 id
)
623 struct arm64_ftr_reg
*regp
= get_arm64_ftr_reg(id
);
625 /* We shouldn't get a request for an unsupported register */
627 return regp
->sys_val
;
631 * __raw_read_system_reg() - Used by a STARTING cpu before cpuinfo is populated.
632 * Read the system register on the current CPU
634 static u64
__raw_read_system_reg(u32 sys_id
)
637 case SYS_ID_PFR0_EL1
: return read_cpuid(ID_PFR0_EL1
);
638 case SYS_ID_PFR1_EL1
: return read_cpuid(ID_PFR1_EL1
);
639 case SYS_ID_DFR0_EL1
: return read_cpuid(ID_DFR0_EL1
);
640 case SYS_ID_MMFR0_EL1
: return read_cpuid(ID_MMFR0_EL1
);
641 case SYS_ID_MMFR1_EL1
: return read_cpuid(ID_MMFR1_EL1
);
642 case SYS_ID_MMFR2_EL1
: return read_cpuid(ID_MMFR2_EL1
);
643 case SYS_ID_MMFR3_EL1
: return read_cpuid(ID_MMFR3_EL1
);
644 case SYS_ID_ISAR0_EL1
: return read_cpuid(ID_ISAR0_EL1
);
645 case SYS_ID_ISAR1_EL1
: return read_cpuid(ID_ISAR1_EL1
);
646 case SYS_ID_ISAR2_EL1
: return read_cpuid(ID_ISAR2_EL1
);
647 case SYS_ID_ISAR3_EL1
: return read_cpuid(ID_ISAR3_EL1
);
648 case SYS_ID_ISAR4_EL1
: return read_cpuid(ID_ISAR4_EL1
);
649 case SYS_ID_ISAR5_EL1
: return read_cpuid(ID_ISAR4_EL1
);
650 case SYS_MVFR0_EL1
: return read_cpuid(MVFR0_EL1
);
651 case SYS_MVFR1_EL1
: return read_cpuid(MVFR1_EL1
);
652 case SYS_MVFR2_EL1
: return read_cpuid(MVFR2_EL1
);
654 case SYS_ID_AA64PFR0_EL1
: return read_cpuid(ID_AA64PFR0_EL1
);
655 case SYS_ID_AA64PFR1_EL1
: return read_cpuid(ID_AA64PFR0_EL1
);
656 case SYS_ID_AA64DFR0_EL1
: return read_cpuid(ID_AA64DFR0_EL1
);
657 case SYS_ID_AA64DFR1_EL1
: return read_cpuid(ID_AA64DFR0_EL1
);
658 case SYS_ID_AA64MMFR0_EL1
: return read_cpuid(ID_AA64MMFR0_EL1
);
659 case SYS_ID_AA64MMFR1_EL1
: return read_cpuid(ID_AA64MMFR1_EL1
);
660 case SYS_ID_AA64MMFR2_EL1
: return read_cpuid(ID_AA64MMFR2_EL1
);
661 case SYS_ID_AA64ISAR0_EL1
: return read_cpuid(ID_AA64ISAR0_EL1
);
662 case SYS_ID_AA64ISAR1_EL1
: return read_cpuid(ID_AA64ISAR1_EL1
);
664 case SYS_CNTFRQ_EL0
: return read_cpuid(CNTFRQ_EL0
);
665 case SYS_CTR_EL0
: return read_cpuid(CTR_EL0
);
666 case SYS_DCZID_EL0
: return read_cpuid(DCZID_EL0
);
673 #include <linux/irqchip/arm-gic-v3.h>
676 feature_matches(u64 reg
, const struct arm64_cpu_capabilities
*entry
)
678 int val
= cpuid_feature_extract_field(reg
, entry
->field_pos
, entry
->sign
);
680 return val
>= entry
->min_field_value
;
684 has_cpuid_feature(const struct arm64_cpu_capabilities
*entry
, int scope
)
688 WARN_ON(scope
== SCOPE_LOCAL_CPU
&& preemptible());
689 if (scope
== SCOPE_SYSTEM
)
690 val
= read_system_reg(entry
->sys_reg
);
692 val
= __raw_read_system_reg(entry
->sys_reg
);
694 return feature_matches(val
, entry
);
697 static bool has_useable_gicv3_cpuif(const struct arm64_cpu_capabilities
*entry
, int scope
)
701 if (!has_cpuid_feature(entry
, scope
))
704 has_sre
= gic_enable_sre();
706 pr_warn_once("%s present but disabled by higher exception level\n",
712 static bool has_no_hw_prefetch(const struct arm64_cpu_capabilities
*entry
, int __unused
)
714 u32 midr
= read_cpuid_id();
717 /* Cavium ThunderX pass 1.x and 2.x */
719 rv_max
= (1 << MIDR_VARIANT_SHIFT
) | MIDR_REVISION_MASK
;
721 return MIDR_IS_CPU_MODEL_RANGE(midr
, MIDR_THUNDERX
, rv_min
, rv_max
);
724 static bool runs_at_el2(const struct arm64_cpu_capabilities
*entry
, int __unused
)
726 return is_kernel_in_hyp_mode();
729 static bool hyp_offset_low(const struct arm64_cpu_capabilities
*entry
,
732 phys_addr_t idmap_addr
= virt_to_phys(__hyp_idmap_text_start
);
735 * Activate the lower HYP offset only if:
736 * - the idmap doesn't clash with it,
737 * - the kernel is not running at EL2.
739 return idmap_addr
> GENMASK(VA_BITS
- 2, 0) && !is_kernel_in_hyp_mode();
742 static const struct arm64_cpu_capabilities arm64_features
[] = {
744 .desc
= "GIC system register CPU interface",
745 .capability
= ARM64_HAS_SYSREG_GIC_CPUIF
,
746 .def_scope
= SCOPE_SYSTEM
,
747 .matches
= has_useable_gicv3_cpuif
,
748 .sys_reg
= SYS_ID_AA64PFR0_EL1
,
749 .field_pos
= ID_AA64PFR0_GIC_SHIFT
,
750 .sign
= FTR_UNSIGNED
,
751 .min_field_value
= 1,
753 #ifdef CONFIG_ARM64_PAN
755 .desc
= "Privileged Access Never",
756 .capability
= ARM64_HAS_PAN
,
757 .def_scope
= SCOPE_SYSTEM
,
758 .matches
= has_cpuid_feature
,
759 .sys_reg
= SYS_ID_AA64MMFR1_EL1
,
760 .field_pos
= ID_AA64MMFR1_PAN_SHIFT
,
761 .sign
= FTR_UNSIGNED
,
762 .min_field_value
= 1,
763 .enable
= cpu_enable_pan
,
765 #endif /* CONFIG_ARM64_PAN */
766 #if defined(CONFIG_AS_LSE) && defined(CONFIG_ARM64_LSE_ATOMICS)
768 .desc
= "LSE atomic instructions",
769 .capability
= ARM64_HAS_LSE_ATOMICS
,
770 .def_scope
= SCOPE_SYSTEM
,
771 .matches
= has_cpuid_feature
,
772 .sys_reg
= SYS_ID_AA64ISAR0_EL1
,
773 .field_pos
= ID_AA64ISAR0_ATOMICS_SHIFT
,
774 .sign
= FTR_UNSIGNED
,
775 .min_field_value
= 2,
777 #endif /* CONFIG_AS_LSE && CONFIG_ARM64_LSE_ATOMICS */
779 .desc
= "Software prefetching using PRFM",
780 .capability
= ARM64_HAS_NO_HW_PREFETCH
,
781 .def_scope
= SCOPE_SYSTEM
,
782 .matches
= has_no_hw_prefetch
,
784 #ifdef CONFIG_ARM64_UAO
786 .desc
= "User Access Override",
787 .capability
= ARM64_HAS_UAO
,
788 .def_scope
= SCOPE_SYSTEM
,
789 .matches
= has_cpuid_feature
,
790 .sys_reg
= SYS_ID_AA64MMFR2_EL1
,
791 .field_pos
= ID_AA64MMFR2_UAO_SHIFT
,
792 .min_field_value
= 1,
793 .enable
= cpu_enable_uao
,
795 #endif /* CONFIG_ARM64_UAO */
796 #ifdef CONFIG_ARM64_PAN
798 .capability
= ARM64_ALT_PAN_NOT_UAO
,
799 .def_scope
= SCOPE_SYSTEM
,
800 .matches
= cpufeature_pan_not_uao
,
802 #endif /* CONFIG_ARM64_PAN */
804 .desc
= "Virtualization Host Extensions",
805 .capability
= ARM64_HAS_VIRT_HOST_EXTN
,
806 .def_scope
= SCOPE_SYSTEM
,
807 .matches
= runs_at_el2
,
810 .desc
= "32-bit EL0 Support",
811 .capability
= ARM64_HAS_32BIT_EL0
,
812 .def_scope
= SCOPE_SYSTEM
,
813 .matches
= has_cpuid_feature
,
814 .sys_reg
= SYS_ID_AA64PFR0_EL1
,
815 .sign
= FTR_UNSIGNED
,
816 .field_pos
= ID_AA64PFR0_EL0_SHIFT
,
817 .min_field_value
= ID_AA64PFR0_EL0_32BIT_64BIT
,
820 .desc
= "Reduced HYP mapping offset",
821 .capability
= ARM64_HYP_OFFSET_LOW
,
822 .def_scope
= SCOPE_SYSTEM
,
823 .matches
= hyp_offset_low
,
828 #define HWCAP_CAP(reg, field, s, min_value, type, cap) \
831 .def_scope = SCOPE_SYSTEM, \
832 .matches = has_cpuid_feature, \
834 .field_pos = field, \
836 .min_field_value = min_value, \
837 .hwcap_type = type, \
841 static const struct arm64_cpu_capabilities arm64_elf_hwcaps
[] = {
842 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1
, ID_AA64ISAR0_AES_SHIFT
, FTR_UNSIGNED
, 2, CAP_HWCAP
, HWCAP_PMULL
),
843 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1
, ID_AA64ISAR0_AES_SHIFT
, FTR_UNSIGNED
, 1, CAP_HWCAP
, HWCAP_AES
),
844 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1
, ID_AA64ISAR0_SHA1_SHIFT
, FTR_UNSIGNED
, 1, CAP_HWCAP
, HWCAP_SHA1
),
845 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1
, ID_AA64ISAR0_SHA2_SHIFT
, FTR_UNSIGNED
, 1, CAP_HWCAP
, HWCAP_SHA2
),
846 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1
, ID_AA64ISAR0_CRC32_SHIFT
, FTR_UNSIGNED
, 1, CAP_HWCAP
, HWCAP_CRC32
),
847 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1
, ID_AA64ISAR0_ATOMICS_SHIFT
, FTR_UNSIGNED
, 2, CAP_HWCAP
, HWCAP_ATOMICS
),
848 HWCAP_CAP(SYS_ID_AA64PFR0_EL1
, ID_AA64PFR0_FP_SHIFT
, FTR_SIGNED
, 0, CAP_HWCAP
, HWCAP_FP
),
849 HWCAP_CAP(SYS_ID_AA64PFR0_EL1
, ID_AA64PFR0_FP_SHIFT
, FTR_SIGNED
, 1, CAP_HWCAP
, HWCAP_FPHP
),
850 HWCAP_CAP(SYS_ID_AA64PFR0_EL1
, ID_AA64PFR0_ASIMD_SHIFT
, FTR_SIGNED
, 0, CAP_HWCAP
, HWCAP_ASIMD
),
851 HWCAP_CAP(SYS_ID_AA64PFR0_EL1
, ID_AA64PFR0_ASIMD_SHIFT
, FTR_SIGNED
, 1, CAP_HWCAP
, HWCAP_ASIMDHP
),
855 static const struct arm64_cpu_capabilities compat_elf_hwcaps
[] = {
857 HWCAP_CAP(SYS_ID_ISAR5_EL1
, ID_ISAR5_AES_SHIFT
, FTR_UNSIGNED
, 2, CAP_COMPAT_HWCAP2
, COMPAT_HWCAP2_PMULL
),
858 HWCAP_CAP(SYS_ID_ISAR5_EL1
, ID_ISAR5_AES_SHIFT
, FTR_UNSIGNED
, 1, CAP_COMPAT_HWCAP2
, COMPAT_HWCAP2_AES
),
859 HWCAP_CAP(SYS_ID_ISAR5_EL1
, ID_ISAR5_SHA1_SHIFT
, FTR_UNSIGNED
, 1, CAP_COMPAT_HWCAP2
, COMPAT_HWCAP2_SHA1
),
860 HWCAP_CAP(SYS_ID_ISAR5_EL1
, ID_ISAR5_SHA2_SHIFT
, FTR_UNSIGNED
, 1, CAP_COMPAT_HWCAP2
, COMPAT_HWCAP2_SHA2
),
861 HWCAP_CAP(SYS_ID_ISAR5_EL1
, ID_ISAR5_CRC32_SHIFT
, FTR_UNSIGNED
, 1, CAP_COMPAT_HWCAP2
, COMPAT_HWCAP2_CRC32
),
866 static void __init
cap_set_elf_hwcap(const struct arm64_cpu_capabilities
*cap
)
868 switch (cap
->hwcap_type
) {
870 elf_hwcap
|= cap
->hwcap
;
873 case CAP_COMPAT_HWCAP
:
874 compat_elf_hwcap
|= (u32
)cap
->hwcap
;
876 case CAP_COMPAT_HWCAP2
:
877 compat_elf_hwcap2
|= (u32
)cap
->hwcap
;
886 /* Check if we have a particular HWCAP enabled */
887 static bool cpus_have_elf_hwcap(const struct arm64_cpu_capabilities
*cap
)
891 switch (cap
->hwcap_type
) {
893 rc
= (elf_hwcap
& cap
->hwcap
) != 0;
896 case CAP_COMPAT_HWCAP
:
897 rc
= (compat_elf_hwcap
& (u32
)cap
->hwcap
) != 0;
899 case CAP_COMPAT_HWCAP2
:
900 rc
= (compat_elf_hwcap2
& (u32
)cap
->hwcap
) != 0;
911 static void __init
setup_elf_hwcaps(const struct arm64_cpu_capabilities
*hwcaps
)
913 for (; hwcaps
->matches
; hwcaps
++)
914 if (hwcaps
->matches(hwcaps
, hwcaps
->def_scope
))
915 cap_set_elf_hwcap(hwcaps
);
918 void update_cpu_capabilities(const struct arm64_cpu_capabilities
*caps
,
921 for (; caps
->matches
; caps
++) {
922 if (!caps
->matches(caps
, caps
->def_scope
))
925 if (!cpus_have_cap(caps
->capability
) && caps
->desc
)
926 pr_info("%s %s\n", info
, caps
->desc
);
927 cpus_set_cap(caps
->capability
);
932 * Run through the enabled capabilities and enable() it on all active
935 void __init
enable_cpu_capabilities(const struct arm64_cpu_capabilities
*caps
)
937 for (; caps
->matches
; caps
++)
938 if (caps
->enable
&& cpus_have_cap(caps
->capability
))
939 on_each_cpu(caps
->enable
, NULL
, true);
943 * Flag to indicate if we have computed the system wide
944 * capabilities based on the boot time active CPUs. This
945 * will be used to determine if a new booting CPU should
946 * go through the verification process to make sure that it
947 * supports the system capabilities, without using a hotplug
950 static bool sys_caps_initialised
;
952 static inline void set_sys_caps_initialised(void)
954 sys_caps_initialised
= true;
958 * Check for CPU features that are used in early boot
959 * based on the Boot CPU value.
961 static void check_early_cpu_features(void)
964 verify_cpu_asid_bits();
968 verify_local_elf_hwcaps(const struct arm64_cpu_capabilities
*caps
)
971 for (; caps
->matches
; caps
++)
972 if (cpus_have_elf_hwcap(caps
) && !caps
->matches(caps
, SCOPE_LOCAL_CPU
)) {
973 pr_crit("CPU%d: missing HWCAP: %s\n",
974 smp_processor_id(), caps
->desc
);
980 verify_local_cpu_features(const struct arm64_cpu_capabilities
*caps
)
982 for (; caps
->matches
; caps
++) {
983 if (!cpus_have_cap(caps
->capability
))
986 * If the new CPU misses an advertised feature, we cannot proceed
987 * further, park the cpu.
989 if (!caps
->matches(caps
, SCOPE_LOCAL_CPU
)) {
990 pr_crit("CPU%d: missing feature: %s\n",
991 smp_processor_id(), caps
->desc
);
1000 * Run through the enabled system capabilities and enable() it on this CPU.
1001 * The capabilities were decided based on the available CPUs at the boot time.
1002 * Any new CPU should match the system wide status of the capability. If the
1003 * new CPU doesn't have a capability which the system now has enabled, we
1004 * cannot do anything to fix it up and could cause unexpected failures. So
1007 void verify_local_cpu_capabilities(void)
1010 check_early_cpu_features();
1013 * If we haven't computed the system capabilities, there is nothing
1016 if (!sys_caps_initialised
)
1019 verify_local_cpu_errata();
1020 verify_local_cpu_features(arm64_features
);
1021 verify_local_elf_hwcaps(arm64_elf_hwcaps
);
1022 if (system_supports_32bit_el0())
1023 verify_local_elf_hwcaps(compat_elf_hwcaps
);
1026 static void __init
setup_feature_capabilities(void)
1028 update_cpu_capabilities(arm64_features
, "detected feature:");
1029 enable_cpu_capabilities(arm64_features
);
1033 * Check if the current CPU has a given feature capability.
1034 * Should be called from non-preemptible context.
1036 bool this_cpu_has_cap(unsigned int cap
)
1038 const struct arm64_cpu_capabilities
*caps
;
1040 if (WARN_ON(preemptible()))
1043 for (caps
= arm64_features
; caps
->desc
; caps
++)
1044 if (caps
->capability
== cap
&& caps
->matches
)
1045 return caps
->matches(caps
, SCOPE_LOCAL_CPU
);
1050 void __init
setup_cpu_features(void)
1055 /* Set the CPU feature capabilies */
1056 setup_feature_capabilities();
1057 enable_errata_workarounds();
1058 setup_elf_hwcaps(arm64_elf_hwcaps
);
1060 if (system_supports_32bit_el0())
1061 setup_elf_hwcaps(compat_elf_hwcaps
);
1063 /* Advertise that we have computed the system capabilities */
1064 set_sys_caps_initialised();
1067 * Check for sane CTR_EL0.CWG value.
1069 cwg
= cache_type_cwg();
1070 cls
= cache_line_size();
1072 pr_warn("No Cache Writeback Granule information, assuming cache line size %d\n",
1074 if (L1_CACHE_BYTES
< cls
)
1075 pr_warn("L1_CACHE_BYTES smaller than the Cache Writeback Granule (%d < %d)\n",
1076 L1_CACHE_BYTES
, cls
);
1079 static bool __maybe_unused
1080 cpufeature_pan_not_uao(const struct arm64_cpu_capabilities
*entry
, int __unused
)
1082 return (cpus_have_cap(ARM64_HAS_PAN
) && !cpus_have_cap(ARM64_HAS_UAO
));