2 * Low-level exception handling code
4 * Copyright (C) 2012 ARM Ltd.
5 * Authors: Catalin Marinas <catalin.marinas@arm.com>
6 * Will Deacon <will.deacon@arm.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program. If not, see <http://www.gnu.org/licenses/>.
21 #include <linux/init.h>
22 #include <linux/linkage.h>
24 #include <asm/alternative.h>
25 #include <asm/assembler.h>
26 #include <asm/asm-offsets.h>
27 #include <asm/cpufeature.h>
28 #include <asm/errno.h>
31 #include <asm/memory.h>
32 #include <asm/thread_info.h>
33 #include <asm/unistd.h>
36 * Context tracking subsystem. Used to instrument transitions
37 * between user and kernel mode.
39 .macro ct_user_exit, syscall = 0
40 #ifdef CONFIG_CONTEXT_TRACKING
41 bl context_tracking_user_exit
44 * Save/restore needed during syscalls. Restore syscall arguments from
45 * the values already saved on stack during kernel_entry.
48 ldp x2, x3, [sp, #S_X2]
49 ldp x4, x5, [sp, #S_X4]
50 ldp x6, x7, [sp, #S_X6]
56 #ifdef CONFIG_CONTEXT_TRACKING
57 bl context_tracking_user_enter
70 .macro kernel_entry, el, regsize = 64
71 sub sp, sp, #S_FRAME_SIZE
73 mov w0, w0 // zero upper 32 bits of x0
75 stp x0, x1, [sp, #16 * 0]
76 stp x2, x3, [sp, #16 * 1]
77 stp x4, x5, [sp, #16 * 2]
78 stp x6, x7, [sp, #16 * 3]
79 stp x8, x9, [sp, #16 * 4]
80 stp x10, x11, [sp, #16 * 5]
81 stp x12, x13, [sp, #16 * 6]
82 stp x14, x15, [sp, #16 * 7]
83 stp x16, x17, [sp, #16 * 8]
84 stp x18, x19, [sp, #16 * 9]
85 stp x20, x21, [sp, #16 * 10]
86 stp x22, x23, [sp, #16 * 11]
87 stp x24, x25, [sp, #16 * 12]
88 stp x26, x27, [sp, #16 * 13]
89 stp x28, x29, [sp, #16 * 14]
94 and tsk, tsk, #~(THREAD_SIZE - 1) // Ensure MDSCR_EL1.SS is clear,
95 ldr x19, [tsk, #TI_FLAGS] // since we can unmask debug
96 disable_step_tsk x19, x20 // exceptions when scheduling.
98 mov x29, xzr // fp pointed to user-space
100 add x21, sp, #S_FRAME_SIZE
102 /* Save the task's original addr_limit and set USER_DS (TASK_SIZE_64) */
103 ldr x20, [tsk, #TI_ADDR_LIMIT]
104 str x20, [sp, #S_ORIG_ADDR_LIMIT]
105 mov x20, #TASK_SIZE_64
106 str x20, [tsk, #TI_ADDR_LIMIT]
107 ALTERNATIVE(nop, SET_PSTATE_UAO(0), ARM64_HAS_UAO, CONFIG_ARM64_UAO)
108 .endif /* \el == 0 */
111 stp lr, x21, [sp, #S_LR]
112 stp x22, x23, [sp, #S_PC]
115 * Set syscallno to -1 by default (overridden later if real syscall).
119 str x21, [sp, #S_SYSCALLNO]
123 * Set sp_el0 to current thread_info.
130 * Registers that may be useful after this macro is invoked:
134 * x23 - aborted PSTATE
138 .macro kernel_exit, el
140 /* Restore the task's original addr_limit. */
141 ldr x20, [sp, #S_ORIG_ADDR_LIMIT]
142 str x20, [tsk, #TI_ADDR_LIMIT]
144 /* No need to restore UAO, it will be restored from SPSR_EL1 */
147 ldp x21, x22, [sp, #S_PC] // load ELR, SPSR
150 ldr x23, [sp, #S_SP] // load return stack pointer
152 #ifdef CONFIG_ARM64_ERRATUM_845719
153 alternative_if_not ARM64_WORKAROUND_845719
156 #ifdef CONFIG_PID_IN_CONTEXTIDR
161 #ifdef CONFIG_PID_IN_CONTEXTIDR
162 mrs x29, contextidr_el1
163 msr contextidr_el1, x29
165 msr contextidr_el1, xzr
171 msr elr_el1, x21 // set up the return data
173 ldp x0, x1, [sp, #16 * 0]
174 ldp x2, x3, [sp, #16 * 1]
175 ldp x4, x5, [sp, #16 * 2]
176 ldp x6, x7, [sp, #16 * 3]
177 ldp x8, x9, [sp, #16 * 4]
178 ldp x10, x11, [sp, #16 * 5]
179 ldp x12, x13, [sp, #16 * 6]
180 ldp x14, x15, [sp, #16 * 7]
181 ldp x16, x17, [sp, #16 * 8]
182 ldp x18, x19, [sp, #16 * 9]
183 ldp x20, x21, [sp, #16 * 10]
184 ldp x22, x23, [sp, #16 * 11]
185 ldp x24, x25, [sp, #16 * 12]
186 ldp x26, x27, [sp, #16 * 13]
187 ldp x28, x29, [sp, #16 * 14]
189 add sp, sp, #S_FRAME_SIZE // restore sp
190 eret // return to kernel
193 .macro get_thread_info, rd
197 .macro irq_stack_entry
198 mov x19, sp // preserve the original sp
201 * Compare sp with the current thread_info, if the top
202 * ~(THREAD_SIZE - 1) bits match, we are on a task stack, and
203 * should switch to the irq stack.
205 and x25, x19, #~(THREAD_SIZE - 1)
209 this_cpu_ptr irq_stack, x25, x26
210 mov x26, #IRQ_STACK_START_SP
213 /* switch to the irq stack */
217 * Add a dummy stack frame, this non-standard format is fixed up
220 stp x29, x19, [sp, #-16]!
227 * x19 should be preserved between irq_stack_entry and
230 .macro irq_stack_exit
235 * These are the registers used in the syscall handler, and allow us to
236 * have in theory up to 7 arguments to a function - x0 to x6.
238 * x7 is reserved for the system call number in 32-bit mode.
240 sc_nr .req x25 // number of system calls
241 scno .req x26 // syscall number
242 stbl .req x27 // syscall table pointer
243 tsk .req x28 // current thread_info
246 * Interrupt handling.
249 ldr_l x1, handle_arch_irq
261 .pushsection ".entry.text", "ax"
265 ventry el1_sync_invalid // Synchronous EL1t
266 ventry el1_irq_invalid // IRQ EL1t
267 ventry el1_fiq_invalid // FIQ EL1t
268 ventry el1_error_invalid // Error EL1t
270 ventry el1_sync // Synchronous EL1h
271 ventry el1_irq // IRQ EL1h
272 ventry el1_fiq_invalid // FIQ EL1h
273 ventry el1_error_invalid // Error EL1h
275 ventry el0_sync // Synchronous 64-bit EL0
276 ventry el0_irq // IRQ 64-bit EL0
277 ventry el0_fiq_invalid // FIQ 64-bit EL0
278 ventry el0_error_invalid // Error 64-bit EL0
281 ventry el0_sync_compat // Synchronous 32-bit EL0
282 ventry el0_irq_compat // IRQ 32-bit EL0
283 ventry el0_fiq_invalid_compat // FIQ 32-bit EL0
284 ventry el0_error_invalid_compat // Error 32-bit EL0
286 ventry el0_sync_invalid // Synchronous 32-bit EL0
287 ventry el0_irq_invalid // IRQ 32-bit EL0
288 ventry el0_fiq_invalid // FIQ 32-bit EL0
289 ventry el0_error_invalid // Error 32-bit EL0
294 * Invalid mode handlers
296 .macro inv_entry, el, reason, regsize = 64
297 kernel_entry \el, \regsize
305 inv_entry 0, BAD_SYNC
306 ENDPROC(el0_sync_invalid)
310 ENDPROC(el0_irq_invalid)
314 ENDPROC(el0_fiq_invalid)
317 inv_entry 0, BAD_ERROR
318 ENDPROC(el0_error_invalid)
321 el0_fiq_invalid_compat:
322 inv_entry 0, BAD_FIQ, 32
323 ENDPROC(el0_fiq_invalid_compat)
325 el0_error_invalid_compat:
326 inv_entry 0, BAD_ERROR, 32
327 ENDPROC(el0_error_invalid_compat)
331 inv_entry 1, BAD_SYNC
332 ENDPROC(el1_sync_invalid)
336 ENDPROC(el1_irq_invalid)
340 ENDPROC(el1_fiq_invalid)
343 inv_entry 1, BAD_ERROR
344 ENDPROC(el1_error_invalid)
352 mrs x1, esr_el1 // read the syndrome register
353 lsr x24, x1, #ESR_ELx_EC_SHIFT // exception class
354 cmp x24, #ESR_ELx_EC_DABT_CUR // data abort in EL1
356 cmp x24, #ESR_ELx_EC_IABT_CUR // instruction abort in EL1
358 cmp x24, #ESR_ELx_EC_SYS64 // configurable trap
360 cmp x24, #ESR_ELx_EC_SP_ALIGN // stack alignment exception
362 cmp x24, #ESR_ELx_EC_PC_ALIGN // pc alignment exception
364 cmp x24, #ESR_ELx_EC_UNKNOWN // unknown exception in EL1
366 cmp x24, #ESR_ELx_EC_BREAKPT_CUR // debug exception in EL1
372 * Fall through to the Data abort case
376 * Data abort handling
380 // re-enable interrupts if they were enabled in the aborted context
381 tbnz x23, #7, 1f // PSR_I_BIT
384 mov x2, sp // struct pt_regs
387 // disable interrupts before pulling preserved data off the stack
392 * Stack or PC alignment exception handling
400 * Undefined instruction
407 * Debug exception handling
409 cmp x24, #ESR_ELx_EC_BRK64 // if BRK64
410 cinc x24, x24, eq // set bit '0'
411 tbz x24, #0, el1_inv // EL1 only
413 mov x2, sp // struct pt_regs
414 bl do_debug_exception
417 // TODO: add support for undefined instructions in kernel mode
429 #ifdef CONFIG_TRACE_IRQFLAGS
430 bl trace_hardirqs_off
435 #ifdef CONFIG_PREEMPT
436 ldr w24, [tsk, #TI_PREEMPT] // get preempt count
437 cbnz w24, 1f // preempt count != 0
438 ldr x0, [tsk, #TI_FLAGS] // get flags
439 tbz x0, #TIF_NEED_RESCHED, 1f // needs rescheduling?
443 #ifdef CONFIG_TRACE_IRQFLAGS
449 #ifdef CONFIG_PREEMPT
452 1: bl preempt_schedule_irq // irq en/disable is done inside
453 ldr x0, [tsk, #TI_FLAGS] // get new tasks TI_FLAGS
454 tbnz x0, #TIF_NEED_RESCHED, 1b // needs rescheduling?
464 mrs x25, esr_el1 // read the syndrome register
465 lsr x24, x25, #ESR_ELx_EC_SHIFT // exception class
466 cmp x24, #ESR_ELx_EC_SVC64 // SVC in 64-bit state
468 cmp x24, #ESR_ELx_EC_DABT_LOW // data abort in EL0
470 cmp x24, #ESR_ELx_EC_IABT_LOW // instruction abort in EL0
472 cmp x24, #ESR_ELx_EC_FP_ASIMD // FP/ASIMD access
474 cmp x24, #ESR_ELx_EC_FP_EXC64 // FP/ASIMD exception
476 cmp x24, #ESR_ELx_EC_SYS64 // configurable trap
478 cmp x24, #ESR_ELx_EC_SP_ALIGN // stack alignment exception
480 cmp x24, #ESR_ELx_EC_PC_ALIGN // pc alignment exception
482 cmp x24, #ESR_ELx_EC_UNKNOWN // unknown exception in EL0
484 cmp x24, #ESR_ELx_EC_BREAKPT_LOW // debug exception in EL0
492 mrs x25, esr_el1 // read the syndrome register
493 lsr x24, x25, #ESR_ELx_EC_SHIFT // exception class
494 cmp x24, #ESR_ELx_EC_SVC32 // SVC in 32-bit state
496 cmp x24, #ESR_ELx_EC_DABT_LOW // data abort in EL0
498 cmp x24, #ESR_ELx_EC_IABT_LOW // instruction abort in EL0
500 cmp x24, #ESR_ELx_EC_FP_ASIMD // FP/ASIMD access
502 cmp x24, #ESR_ELx_EC_FP_EXC32 // FP/ASIMD exception
504 cmp x24, #ESR_ELx_EC_PC_ALIGN // pc alignment exception
506 cmp x24, #ESR_ELx_EC_UNKNOWN // unknown exception in EL0
508 cmp x24, #ESR_ELx_EC_CP15_32 // CP15 MRC/MCR trap
510 cmp x24, #ESR_ELx_EC_CP15_64 // CP15 MRRC/MCRR trap
512 cmp x24, #ESR_ELx_EC_CP14_MR // CP14 MRC/MCR trap
514 cmp x24, #ESR_ELx_EC_CP14_LS // CP14 LDC/STC trap
516 cmp x24, #ESR_ELx_EC_CP14_64 // CP14 MRRC/MCRR trap
518 cmp x24, #ESR_ELx_EC_BREAKPT_LOW // debug exception in EL0
523 * AArch32 syscall handling
525 adrp stbl, compat_sys_call_table // load compat syscall table pointer
526 uxtw scno, w7 // syscall number in w7 (r7)
527 mov sc_nr, #__NR_compat_syscalls
538 * Data abort handling
541 // enable interrupts before calling the main handler
544 bic x0, x26, #(0xff << 56)
551 * Instruction abort handling
554 // enable interrupts before calling the main handler
564 * Floating Point or Advanced SIMD access
574 * Floating Point or Advanced SIMD exception
584 * Stack or PC alignment exception handling
587 // enable interrupts before calling the main handler
597 * Undefined instruction
599 // enable interrupts before calling the main handler
607 * System instructions, for trapped cache maintenance instructions
617 * Debug exception handling
619 tbnz x24, #0, el0_inv // EL0 only
623 bl do_debug_exception
642 #ifdef CONFIG_TRACE_IRQFLAGS
643 bl trace_hardirqs_off
649 #ifdef CONFIG_TRACE_IRQFLAGS
656 * Register switch for AArch64. The callee-saved registers need to be saved
657 * and restored. On entry:
658 * x0 = previous task_struct (must be preserved across the switch)
659 * x1 = next task_struct
660 * Previous and next are guaranteed not to be the same.
664 mov x10, #THREAD_CPU_CONTEXT
667 stp x19, x20, [x8], #16 // store callee-saved registers
668 stp x21, x22, [x8], #16
669 stp x23, x24, [x8], #16
670 stp x25, x26, [x8], #16
671 stp x27, x28, [x8], #16
672 stp x29, x9, [x8], #16
675 ldp x19, x20, [x8], #16 // restore callee-saved registers
676 ldp x21, x22, [x8], #16
677 ldp x23, x24, [x8], #16
678 ldp x25, x26, [x8], #16
679 ldp x27, x28, [x8], #16
680 ldp x29, x9, [x8], #16
683 and x9, x9, #~(THREAD_SIZE - 1)
686 ENDPROC(cpu_switch_to)
689 * This is the fast syscall return path. We do as little as possible here,
690 * and this includes saving x0 back into the kernel stack.
693 disable_irq // disable interrupts
694 str x0, [sp, #S_X0] // returned x0
695 ldr x1, [tsk, #TI_FLAGS] // re-check for syscall tracing
696 and x2, x1, #_TIF_SYSCALL_WORK
697 cbnz x2, ret_fast_syscall_trace
698 and x2, x1, #_TIF_WORK_MASK
699 cbnz x2, work_pending
700 enable_step_tsk x1, x2
702 ret_fast_syscall_trace:
703 enable_irq // enable interrupts
704 b __sys_trace_return_skipped // we already saved x0
707 * Ok, we need to do extra processing, enter the slow path.
710 tbnz x1, #TIF_NEED_RESCHED, work_resched
711 /* TIF_SIGPENDING, TIF_NOTIFY_RESUME or TIF_FOREIGN_FPSTATE case */
713 enable_irq // enable interrupts for do_notify_resume()
717 #ifdef CONFIG_TRACE_IRQFLAGS
718 bl trace_hardirqs_off // the IRQs are off here, inform the tracing code
723 * "slow" syscall return path.
726 disable_irq // disable interrupts
727 ldr x1, [tsk, #TI_FLAGS]
728 and x2, x1, #_TIF_WORK_MASK
729 cbnz x2, work_pending
730 enable_step_tsk x1, x2
735 * This is how we return from a fork.
739 cbz x19, 1f // not a kernel thread
742 1: get_thread_info tsk
744 ENDPROC(ret_from_fork)
751 adrp stbl, sys_call_table // load syscall table pointer
752 uxtw scno, w8 // syscall number in w8
753 mov sc_nr, #__NR_syscalls
754 el0_svc_naked: // compat entry point
755 stp x0, scno, [sp, #S_ORIG_X0] // save the original x0 and syscall number
759 ldr x16, [tsk, #TI_FLAGS] // check for syscall hooks
760 tst x16, #_TIF_SYSCALL_WORK
762 cmp scno, sc_nr // check upper syscall limit
764 ldr x16, [stbl, scno, lsl #3] // address in the syscall table
765 blr x16 // call sys_* routine
774 * This is the really slow path. We're going to be doing context
775 * switches, and waiting for our parent to respond.
778 mov w0, #-1 // set default errno for
779 cmp scno, x0 // user-issued syscall(-1)
784 bl syscall_trace_enter
785 cmp w0, #-1 // skip the syscall?
786 b.eq __sys_trace_return_skipped
787 uxtw scno, w0 // syscall number (possibly new)
788 mov x1, sp // pointer to regs
789 cmp scno, sc_nr // check upper syscall limit
791 ldp x0, x1, [sp] // restore the syscall args
792 ldp x2, x3, [sp, #S_X2]
793 ldp x4, x5, [sp, #S_X4]
794 ldp x6, x7, [sp, #S_X6]
795 ldr x16, [stbl, scno, lsl #3] // address in the syscall table
796 blr x16 // call sys_* routine
799 str x0, [sp, #S_X0] // save returned x0
800 __sys_trace_return_skipped:
802 bl syscall_trace_exit
810 .popsection // .entry.text
813 * Special system call wrappers.
815 ENTRY(sys_rt_sigreturn_wrapper)
818 ENDPROC(sys_rt_sigreturn_wrapper)