2 * Low-level CPU initialisation
3 * Based on arch/arm/kernel/head.S
5 * Copyright (C) 1994-2002 Russell King
6 * Copyright (C) 2003-2012 ARM Ltd.
7 * Authors: Catalin Marinas <catalin.marinas@arm.com>
8 * Will Deacon <will.deacon@arm.com>
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program. If not, see <http://www.gnu.org/licenses/>.
23 #include <linux/linkage.h>
24 #include <linux/init.h>
26 #include <asm/assembler.h>
27 #include <asm/ptrace.h>
28 #include <asm/asm-offsets.h>
29 #include <asm/memory.h>
30 #include <asm/thread_info.h>
31 #include <asm/pgtable-hwdef.h>
32 #include <asm/pgtable.h>
36 * swapper_pg_dir is the virtual address of the initial page table. We place
37 * the page tables 3 * PAGE_SIZE below KERNEL_RAM_VADDR. The idmap_pg_dir has
38 * 2 pages and is placed below swapper_pg_dir.
40 #define KERNEL_RAM_VADDR (PAGE_OFFSET + TEXT_OFFSET)
42 #if (KERNEL_RAM_VADDR & 0xfffff) != 0x80000
43 #error KERNEL_RAM_VADDR must start at 0xXXX80000
46 #define SWAPPER_DIR_SIZE (3 * PAGE_SIZE)
47 #define IDMAP_DIR_SIZE (2 * PAGE_SIZE)
50 .equ swapper_pg_dir, KERNEL_RAM_VADDR - SWAPPER_DIR_SIZE
53 .equ idmap_pg_dir, swapper_pg_dir - IDMAP_DIR_SIZE
55 .macro pgtbl, ttb0, ttb1, phys
56 add \ttb1, \phys, #TEXT_OFFSET - SWAPPER_DIR_SIZE
57 sub \ttb0, \ttb1, #IDMAP_DIR_SIZE
60 #ifdef CONFIG_ARM64_64K_PAGES
61 #define BLOCK_SHIFT PAGE_SHIFT
62 #define BLOCK_SIZE PAGE_SIZE
64 #define BLOCK_SHIFT SECTION_SHIFT
65 #define BLOCK_SIZE SECTION_SIZE
68 #define KERNEL_START KERNEL_RAM_VADDR
69 #define KERNEL_END _end
72 * Initial memory map attributes.
75 #define PTE_FLAGS PTE_TYPE_PAGE | PTE_AF
76 #define PMD_FLAGS PMD_TYPE_SECT | PMD_SECT_AF
78 #define PTE_FLAGS PTE_TYPE_PAGE | PTE_AF | PTE_SHARED
79 #define PMD_FLAGS PMD_TYPE_SECT | PMD_SECT_AF | PMD_SECT_S
82 #ifdef CONFIG_ARM64_64K_PAGES
83 #define MM_MMUFLAGS PTE_ATTRINDX(MT_NORMAL) | PTE_FLAGS
84 #define IO_MMUFLAGS PTE_ATTRINDX(MT_DEVICE_nGnRE) | PTE_XN | PTE_FLAGS
86 #define MM_MMUFLAGS PMD_ATTRINDX(MT_NORMAL) | PMD_FLAGS
87 #define IO_MMUFLAGS PMD_ATTRINDX(MT_DEVICE_nGnRE) | PMD_SECT_XN | PMD_FLAGS
91 * Kernel startup entry point.
92 * ---------------------------
94 * The requirements are:
95 * MMU = off, D-cache = off, I-cache = on or off,
96 * x0 = physical address to the FDT blob.
98 * This code is mostly position independent so you call this at
99 * __pa(PAGE_OFFSET + TEXT_OFFSET).
101 * Note that the callee-saved registers are used for storing variables
102 * that are useful before the MMU is enabled. The allocations are described
103 * in the entry routines.
108 * DO NOT MODIFY. Image header expected by Linux boot-loaders.
110 b stext // branch to kernel start, magic
112 .quad TEXT_OFFSET // Image load offset from start of RAM
117 mov x21, x0 // x21=FDT
118 bl el2_setup // Drop to EL1
119 mrs x22, midr_el1 // x22=cpuid
121 bl lookup_processor_type
122 mov x23, x0 // x23=current cpu_table
123 cbz x23, __error_p // invalid processor (x23=0)?
124 bl __calc_phys_offset // x24=PHYS_OFFSET, x28=PHYS_OFFSET-PAGE_OFFSET
126 bl __create_page_tables // x25=TTBR0, x26=TTBR1
128 * The following calls CPU specific code in a position independent
129 * manner. See arch/arm64/mm/proc.S for details. x23 = base of
130 * cpu_info structure selected by lookup_processor_type above.
131 * On return, the CPU will be ready for the MMU to be turned on and
132 * the TCR will have been set.
134 ldr x27, __switch_data // address to jump to after
135 // MMU has been enabled
136 adr lr, __enable_mmu // return (PIC) address
137 ldr x12, [x23, #CPU_INFO_SETUP]
138 add x12, x12, x28 // __virt_to_phys
139 br x12 // initialise processor
143 * If we're fortunate enough to boot at EL2, ensure that the world is
144 * sane before dropping to EL1.
148 cmp x0, #PSR_MODE_EL2t
149 ccmp x0, #PSR_MODE_EL2h, #0x4, ne
153 /* Hyp configuration. */
154 1: mov x0, #(1 << 31) // 64-bit EL1
157 /* Generic timers. */
159 orr x0, x0, #3 // Enable EL1 physical timers
162 /* Populate ID registers. */
169 mov x0, #0x0800 // Set/clear RES{1,0} bits
170 movk x0, #0x30d0, lsl #16
173 /* Coprocessor traps. */
175 msr cptr_el2, x0 // Disable copro. traps to EL2
178 msr hstr_el2, xzr // Disable CP15 traps to EL2
182 mov x0, #(PSR_F_BIT | PSR_I_BIT | PSR_A_BIT | PSR_D_BIT |\
194 .pushsection .smp.pen.text, "ax"
197 .quad secondary_holding_pen_release
200 * This provides a "holding pen" for platforms to hold all secondary
201 * cores are held until we're ready for them to initialise.
203 ENTRY(secondary_holding_pen)
204 bl el2_setup // Drop to EL1
206 and x0, x0, #15 // CPU number
213 b.eq secondary_startup
216 ENDPROC(secondary_holding_pen)
219 ENTRY(secondary_startup)
221 * Common entry point for secondary CPUs.
223 mrs x22, midr_el1 // x22=cpuid
225 bl lookup_processor_type
226 mov x23, x0 // x23=current cpu_table
227 cbz x23, __error_p // invalid processor (x23=0)?
229 bl __calc_phys_offset // x24=phys offset
230 pgtbl x25, x26, x24 // x25=TTBR0, x26=TTBR1
231 ldr x12, [x23, #CPU_INFO_SETUP]
232 add x12, x12, x28 // __virt_to_phys
233 blr x12 // initialise processor
235 ldr x21, =secondary_data
236 ldr x27, =__secondary_switched // address to jump to after enabling the MMU
238 ENDPROC(secondary_startup)
240 ENTRY(__secondary_switched)
241 ldr x0, [x21] // get secondary_data.stack
244 b secondary_start_kernel
245 ENDPROC(__secondary_switched)
246 #endif /* CONFIG_SMP */
249 * Setup common bits before finally enabling the MMU. Essentially this is just
250 * loading the page table pointer and vector base registers.
252 * On entry to this code, x0 must contain the SCTLR_EL1 value for turning on
258 msr ttbr0_el1, x25 // load TTBR0
259 msr ttbr1_el1, x26 // load TTBR1
262 ENDPROC(__enable_mmu)
265 * Enable the MMU. This completely changes the structure of the visible memory
266 * space. You will not be able to trace execution through this.
268 * x0 = system control register
269 * x27 = *virtual* address to jump to upon completion
271 * other registers depend on the function called upon completion
278 ENDPROC(__turn_mmu_on)
281 * Calculate the start of physical memory.
286 sub x28, x0, x1 // x28 = PHYS_OFFSET - PAGE_OFFSET
287 add x24, x2, x28 // x24 = PHYS_OFFSET
289 ENDPROC(__calc_phys_offset)
296 * Macro to populate the PGD for the corresponding block entry in the next
297 * level (tbl) for the given virtual address.
299 * Preserves: pgd, tbl, virt
300 * Corrupts: tmp1, tmp2
302 .macro create_pgd_entry, pgd, tbl, virt, tmp1, tmp2
303 lsr \tmp1, \virt, #PGDIR_SHIFT
304 and \tmp1, \tmp1, #PTRS_PER_PGD - 1 // PGD index
305 orr \tmp2, \tbl, #3 // PGD entry table type
306 str \tmp2, [\pgd, \tmp1, lsl #3]
310 * Macro to populate block entries in the page table for the start..end
311 * virtual range (inclusive).
313 * Preserves: tbl, flags
314 * Corrupts: phys, start, end, pstate
316 .macro create_block_map, tbl, flags, phys, start, end, idmap=0
317 lsr \phys, \phys, #BLOCK_SHIFT
319 and \start, \phys, #PTRS_PER_PTE - 1 // table index
321 lsr \start, \start, #BLOCK_SHIFT
322 and \start, \start, #PTRS_PER_PTE - 1 // table index
324 orr \phys, \flags, \phys, lsl #BLOCK_SHIFT // table entry
326 lsr \end, \end, #BLOCK_SHIFT
327 and \end, \end, #PTRS_PER_PTE - 1 // table end index
329 9999: str \phys, [\tbl, \start, lsl #3] // store the entry
331 add \start, \start, #1 // next entry
332 add \phys, \phys, #BLOCK_SIZE // next block
339 * Setup the initial page tables. We only setup the barest amount which is
340 * required to get the kernel running. The following sections are required:
341 * - identity mapping to enable the MMU (low address, TTBR0)
342 * - first few MB of the kernel linear mapping to jump to once the MMU has
343 * been enabled, including the FDT blob (TTBR1)
345 __create_page_tables:
346 pgtbl x25, x26, x24 // idmap_pg_dir and swapper_pg_dir addresses
349 * Clear the idmap and swapper page tables.
352 add x6, x26, #SWAPPER_DIR_SIZE
353 1: stp xzr, xzr, [x0], #16
354 stp xzr, xzr, [x0], #16
355 stp xzr, xzr, [x0], #16
356 stp xzr, xzr, [x0], #16
363 * Create the identity mapping.
365 add x0, x25, #PAGE_SIZE // section table address
366 adr x3, __turn_mmu_on // virtual/physical address
367 create_pgd_entry x25, x0, x3, x5, x6
368 create_block_map x0, x7, x3, x5, x5, idmap=1
371 * Map the kernel image (starting with PHYS_OFFSET).
373 add x0, x26, #PAGE_SIZE // section table address
375 create_pgd_entry x26, x0, x5, x3, x6
376 ldr x6, =KERNEL_END - 1
377 mov x3, x24 // phys offset
378 create_block_map x0, x7, x3, x5, x6
381 * Map the FDT blob (maximum 2MB; must be within 512MB of
384 mov x3, x21 // FDT phys address
385 and x3, x3, #~((1 << 21) - 1) // 2MB aligned
387 sub x5, x3, x24 // subtract PHYS_OFFSET
388 tst x5, #~((1 << 29) - 1) // within 512MB?
389 csel x21, xzr, x21, ne // zero the FDT pointer
391 add x5, x5, x6 // __va(FDT blob)
392 add x6, x5, #1 << 21 // 2MB for the FDT blob
393 sub x6, x6, #1 // inclusive range
394 create_block_map x0, x7, x3, x5, x6
397 ENDPROC(__create_page_tables)
401 .type __switch_data, %object
403 .quad __mmap_switched
404 .quad __data_loc // x4
406 .quad __bss_start // x6
408 .quad processor_id // x4
409 .quad __fdt_pointer // x5
410 .quad memstart_addr // x6
411 .quad init_thread_union + THREAD_START_SP // sp
414 * The following fragment of code is executed with the MMU on in MMU mode, and
415 * uses absolute addresses; this is not position independent.
418 adr x3, __switch_data + 8
420 ldp x4, x5, [x3], #16
421 ldp x6, x7, [x3], #16
422 cmp x4, x5 // Copy data segment if needed
423 1: ccmp x5, x6, #4, ne
431 str xzr, [x6], #8 // Clear BSS
434 ldp x4, x5, [x3], #16
438 str x22, [x4] // Save processor ID
439 str x21, [x5] // Save FDT pointer
440 str x24, [x6] // Save PHYS_OFFSET
443 ENDPROC(__mmap_switched)
446 * Exception handling. Something went wrong and we can't proceed. We ought to
447 * tell the user, but since we don't have any guarantee that we're even
448 * running on the right architecture, we do virtually nothing.
459 * This function gets the processor ID in w0 and searches the cpu_table[] for
460 * a match. It returns a pointer to the struct cpu_info it found. The
461 * cpu_table[] must end with an empty (all zeros) structure.
463 * This routine can be called via C code and it needs to work with the MMU
464 * both disabled and enabled (the offset is calculated automatically).
466 ENTRY(lookup_processor_type)
467 adr x1, __lookup_processor_type_data
469 sub x1, x1, x2 // get offset between VA and PA
470 add x3, x3, x1 // convert VA to PA
472 ldp w5, w6, [x3] // load cpu_id_val and cpu_id_mask
473 cbz w5, 2f // end of list?
477 add x3, x3, #CPU_INFO_SZ
480 mov x3, #0 // unknown processor
484 ENDPROC(lookup_processor_type)
487 .type __lookup_processor_type_data, %object
488 __lookup_processor_type_data:
491 .size __lookup_processor_type_data, . - __lookup_processor_type_data
494 * Determine validity of the x21 FDT pointer.
495 * The dtb must be 8-byte aligned and live in the first 512M of memory.