arch/arm64/kernel/kuser32.S

   1 /*
   2  * Low-level user helpers placed in the vectors page for AArch32.
   3  * Based on the kuser helpers in arch/arm/kernel/entry-armv.S.
   4  *
   5  * Copyright (C) 2005-2011 Nicolas Pitre <nico@fluxnic.net>
   6  * Copyright (C) 2012 ARM Ltd.
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  19  *
  20  *
  21  * AArch32 user helpers.
  22  *
  23  * Each segment is 32-byte aligned and will be moved to the top of the high
  24  * vector page.  New segments (if ever needed) must be added in front of
  25  * existing ones.  This mechanism should be used only for things that are
  26  * really small and justified, and not be abused freely.
  27  *
  28  * See Documentation/arm/kernel_user_helpers.txt for formal definitions.
  29  */
  30
  31 #include <asm/unistd32.h>
  32
  33         .align  5
  34         .globl  __kuser_helper_start
  35 __kuser_helper_start:
  36
  37 __kuser_cmpxchg64:                      // 0xffff0f60
  38         .inst   0xe92d00f0              //      push            {r4, r5, r6, r7}
  39         .inst   0xe1c040d0              //      ldrd            r4, r5, [r0]
  40         .inst   0xe1c160d0              //      ldrd            r6, r7, [r1]
  41         .inst   0xe1b20e9f              // 1:   ldaexd          r0, r1, [r2]
  42         .inst   0xe0303004              //      eors            r3, r0, r4
  43         .inst   0x00313005              //      eoreqs          r3, r1, r5
  44         .inst   0x01a23e96              //      stlexdeq        r3, r6, [r2]
  45         .inst   0x03330001              //      teqeq           r3, #1
  46         .inst   0x0afffff9              //      beq             1b
  47         .inst   0xe2730000              //      rsbs            r0, r3, #0
  48         .inst   0xe8bd00f0              //      pop             {r4, r5, r6, r7}
  49         .inst   0xe12fff1e              //      bx              lr
  50
  51         .align  5
  52 __kuser_memory_barrier:                 // 0xffff0fa0
  53         .inst   0xf57ff05b              //      dmb             ish
  54         .inst   0xe12fff1e              //      bx              lr
  55
  56         .align  5
  57 __kuser_cmpxchg:                        // 0xffff0fc0
  58         .inst   0xe1923e9f              // 1:   ldaex           r3, [r2]
  59         .inst   0xe0533000              //      subs            r3, r3, r0
  60         .inst   0x01823e91              //      stlexeq         r3, r1, [r2]
  61         .inst   0x03330001              //      teqeq           r3, #1
  62         .inst   0x0afffffa              //      beq             1b
  63         .inst   0xe2730000              //      rsbs            r0, r3, #0
  64         .inst   0xe12fff1e              //      bx              lr
  65
  66         .align  5
  67 __kuser_get_tls:                        // 0xffff0fe0
  68         .inst   0xee1d0f70              //      mrc             p15, 0, r0, c13, c0, 3
  69         .inst   0xe12fff1e              //      bx              lr
  70         .rep    5
  71         .word   0
  72         .endr
  73
  74 __kuser_helper_version:                 // 0xffff0ffc
  75         .word   ((__kuser_helper_end - __kuser_helper_start) >> 5)
  76         .globl  __kuser_helper_end
  77 __kuser_helper_end:
  78
  79 /*
  80  * AArch32 sigreturn code
  81  *
  82  * For ARM syscalls, the syscall number has to be loaded into r7.
  83  * We do not support an OABI userspace.
  84  *
  85  * For Thumb syscalls, we also pass the syscall number via r7. We therefore
  86  * need two 16-bit instructions.
  87  */
  88         .globl __aarch32_sigret_code_start
  89 __aarch32_sigret_code_start:
  90
  91         /*
  92          * ARM Code
  93          */
  94         .byte   __NR_compat_sigreturn, 0x70, 0xa0, 0xe3 // mov  r7, #__NR_compat_sigreturn
  95         .byte   __NR_compat_sigreturn, 0x00, 0x00, 0xef // svc  #__NR_compat_sigreturn
  96
  97         /*
  98          * Thumb code
  99          */
 100         .byte   __NR_compat_sigreturn, 0x27                     // svc  #__NR_compat_sigreturn
 101         .byte   __NR_compat_sigreturn, 0xdf                     // mov  r7, #__NR_compat_sigreturn
 102
 103         /*
 104          * ARM code
 105          */
 106         .byte   __NR_compat_rt_sigreturn, 0x70, 0xa0, 0xe3      // mov  r7, #__NR_compat_rt_sigreturn
 107         .byte   __NR_compat_rt_sigreturn, 0x00, 0x00, 0xef      // svc  #__NR_compat_rt_sigreturn
 108
 109         /*
 110          * Thumb code
 111          */
 112         .byte   __NR_compat_rt_sigreturn, 0x27                  // svc  #__NR_compat_rt_sigreturn
 113         .byte   __NR_compat_rt_sigreturn, 0xdf                  // mov  r7, #__NR_compat_rt_sigreturn
 114
 115         .globl __aarch32_sigret_code_end
 116 __aarch32_sigret_code_end: