2 * Based on arch/arm/kernel/setup.c
4 * Copyright (C) 1995-2001 Russell King
5 * Copyright (C) 2012 ARM Ltd.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program. If not, see <http://www.gnu.org/licenses/>.
20 #include <linux/acpi.h>
21 #include <linux/export.h>
22 #include <linux/kernel.h>
23 #include <linux/stddef.h>
24 #include <linux/ioport.h>
25 #include <linux/delay.h>
26 #include <linux/utsname.h>
27 #include <linux/initrd.h>
28 #include <linux/console.h>
29 #include <linux/cache.h>
30 #include <linux/bootmem.h>
31 #include <linux/screen_info.h>
32 #include <linux/init.h>
33 #include <linux/kexec.h>
34 #include <linux/crash_dump.h>
35 #include <linux/root_dev.h>
36 #include <linux/cpu.h>
37 #include <linux/interrupt.h>
38 #include <linux/smp.h>
40 #include <linux/proc_fs.h>
41 #include <linux/memblock.h>
42 #include <linux/of_iommu.h>
43 #include <linux/of_fdt.h>
44 #include <linux/of_platform.h>
45 #include <linux/efi.h>
46 #include <linux/psci.h>
49 #include <asm/fixmap.h>
51 #include <asm/cputype.h>
53 #include <asm/cpufeature.h>
54 #include <asm/cpu_ops.h>
55 #include <asm/kasan.h>
57 #include <asm/sections.h>
58 #include <asm/setup.h>
59 #include <asm/smp_plat.h>
60 #include <asm/cacheflush.h>
61 #include <asm/tlbflush.h>
62 #include <asm/traps.h>
63 #include <asm/memblock.h>
65 #include <asm/xen/hypervisor.h>
66 #include <asm/mmu_context.h>
68 phys_addr_t __fdt_pointer __initdata
;
71 * Standard memory resources
73 static struct resource mem_res
[] = {
75 .name
= "Kernel code",
78 .flags
= IORESOURCE_SYSTEM_RAM
81 .name
= "Kernel data",
84 .flags
= IORESOURCE_SYSTEM_RAM
88 #define kernel_code mem_res[0]
89 #define kernel_data mem_res[1]
92 * The recorded values of x0 .. x3 upon kernel entry.
94 u64 __cacheline_aligned boot_args
[4];
96 void __init
smp_setup_processor_id(void)
98 u64 mpidr
= read_cpuid_mpidr() & MPIDR_HWID_BITMASK
;
99 cpu_logical_map(0) = mpidr
;
102 * clear __my_cpu_offset on boot CPU to avoid hang caused by
103 * using percpu variable early, for example, lockdep will
104 * access percpu variable inside lock_release
106 set_my_cpu_offset(0);
107 pr_info("Booting Linux on physical CPU 0x%lx\n", (unsigned long)mpidr
);
110 bool arch_match_cpu_phys_id(int cpu
, u64 phys_id
)
112 return phys_id
== cpu_logical_map(cpu
);
115 struct mpidr_hash mpidr_hash
;
117 * smp_build_mpidr_hash - Pre-compute shifts required at each affinity
118 * level in order to build a linear index from an
119 * MPIDR value. Resulting algorithm is a collision
120 * free hash carried out through shifting and ORing
122 static void __init
smp_build_mpidr_hash(void)
124 u32 i
, affinity
, fs
[4], bits
[4], ls
;
127 * Pre-scan the list of MPIDRS and filter out bits that do
128 * not contribute to affinity levels, ie they never toggle.
130 for_each_possible_cpu(i
)
131 mask
|= (cpu_logical_map(i
) ^ cpu_logical_map(0));
132 pr_debug("mask of set bits %#llx\n", mask
);
134 * Find and stash the last and first bit set at all affinity levels to
135 * check how many bits are required to represent them.
137 for (i
= 0; i
< 4; i
++) {
138 affinity
= MPIDR_AFFINITY_LEVEL(mask
, i
);
140 * Find the MSB bit and LSB bits position
141 * to determine how many bits are required
142 * to express the affinity level.
145 fs
[i
] = affinity
? ffs(affinity
) - 1 : 0;
146 bits
[i
] = ls
- fs
[i
];
149 * An index can be created from the MPIDR_EL1 by isolating the
150 * significant bits at each affinity level and by shifting
151 * them in order to compress the 32 bits values space to a
152 * compressed set of values. This is equivalent to hashing
153 * the MPIDR_EL1 through shifting and ORing. It is a collision free
154 * hash though not minimal since some levels might contain a number
155 * of CPUs that is not an exact power of 2 and their bit
156 * representation might contain holes, eg MPIDR_EL1[7:0] = {0x2, 0x80}.
158 mpidr_hash
.shift_aff
[0] = MPIDR_LEVEL_SHIFT(0) + fs
[0];
159 mpidr_hash
.shift_aff
[1] = MPIDR_LEVEL_SHIFT(1) + fs
[1] - bits
[0];
160 mpidr_hash
.shift_aff
[2] = MPIDR_LEVEL_SHIFT(2) + fs
[2] -
162 mpidr_hash
.shift_aff
[3] = MPIDR_LEVEL_SHIFT(3) +
163 fs
[3] - (bits
[2] + bits
[1] + bits
[0]);
164 mpidr_hash
.mask
= mask
;
165 mpidr_hash
.bits
= bits
[3] + bits
[2] + bits
[1] + bits
[0];
166 pr_debug("MPIDR hash: aff0[%u] aff1[%u] aff2[%u] aff3[%u] mask[%#llx] bits[%u]\n",
167 mpidr_hash
.shift_aff
[0],
168 mpidr_hash
.shift_aff
[1],
169 mpidr_hash
.shift_aff
[2],
170 mpidr_hash
.shift_aff
[3],
174 * 4x is an arbitrary value used to warn on a hash table much bigger
175 * than expected on most systems.
177 if (mpidr_hash_size() > 4 * num_possible_cpus())
178 pr_warn("Large number of MPIDR hash buckets detected\n");
181 static void __init
setup_machine_fdt(phys_addr_t dt_phys
)
183 void *dt_virt
= fixmap_remap_fdt(dt_phys
);
185 if (!dt_virt
|| !early_init_dt_scan(dt_virt
)) {
187 "Error: invalid device tree blob at physical address %pa (virtual address 0x%p)\n"
188 "The dtb must be 8-byte aligned and must not exceed 2 MB in size\n"
189 "\nPlease check your bootloader.",
196 dump_stack_set_arch_desc("%s (DT)", of_flat_dt_get_machine_name());
199 static void __init
request_standard_resources(void)
201 struct memblock_region
*region
;
202 struct resource
*res
;
204 kernel_code
.start
= virt_to_phys(_text
);
205 kernel_code
.end
= virt_to_phys(__init_begin
- 1);
206 kernel_data
.start
= virt_to_phys(_sdata
);
207 kernel_data
.end
= virt_to_phys(_end
- 1);
209 for_each_memblock(memory
, region
) {
210 res
= alloc_bootmem_low(sizeof(*res
));
211 res
->name
= "System RAM";
212 res
->start
= __pfn_to_phys(memblock_region_memory_base_pfn(region
));
213 res
->end
= __pfn_to_phys(memblock_region_memory_end_pfn(region
)) - 1;
214 res
->flags
= IORESOURCE_SYSTEM_RAM
| IORESOURCE_BUSY
;
216 request_resource(&iomem_resource
, res
);
218 if (kernel_code
.start
>= res
->start
&&
219 kernel_code
.end
<= res
->end
)
220 request_resource(res
, &kernel_code
);
221 if (kernel_data
.start
>= res
->start
&&
222 kernel_data
.end
<= res
->end
)
223 request_resource(res
, &kernel_data
);
227 u64 __cpu_logical_map
[NR_CPUS
] = { [0 ... NR_CPUS
-1] = INVALID_HWID
};
229 void __init
setup_arch(char **cmdline_p
)
231 pr_info("Boot CPU: AArch64 Processor [%08x]\n", read_cpuid_id());
233 sprintf(init_utsname()->machine
, ELF_PLATFORM
);
234 init_mm
.start_code
= (unsigned long) _text
;
235 init_mm
.end_code
= (unsigned long) _etext
;
236 init_mm
.end_data
= (unsigned long) _edata
;
237 init_mm
.brk
= (unsigned long) _end
;
239 *cmdline_p
= boot_command_line
;
242 early_ioremap_init();
244 setup_machine_fdt(__fdt_pointer
);
249 * Unmask asynchronous aborts after bringing up possible earlycon.
250 * (Report possible System Errors once we can report this occurred)
252 local_async_enable();
255 * TTBR0 is only used for the identity mapping at this stage. Make it
256 * point to zero page to avoid speculatively fetching new entries.
258 cpu_uninstall_idmap();
261 arm64_memblock_init();
263 /* Parse the ACPI tables for possible boot-time configuration */
264 acpi_boot_table_init();
269 unflatten_device_tree();
275 request_standard_resources();
277 early_ioremap_reset();
286 cpu_read_bootcpu_ops();
288 smp_build_mpidr_hash();
291 #if defined(CONFIG_VGA_CONSOLE)
292 conswitchp
= &vga_con
;
293 #elif defined(CONFIG_DUMMY_CONSOLE)
294 conswitchp
= &dummy_con
;
297 if (boot_args
[1] || boot_args
[2] || boot_args
[3]) {
298 pr_err("WARNING: x1-x3 nonzero in violation of boot protocol:\n"
299 "\tx1: %016llx\n\tx2: %016llx\n\tx3: %016llx\n"
300 "This indicates a broken bootloader or old kernel\n",
301 boot_args
[1], boot_args
[2], boot_args
[3]);
305 static int __init
arm64_device_init(void)
307 if (of_have_populated_dt()) {
309 of_platform_populate(NULL
, of_default_bus_match_table
,
311 } else if (acpi_disabled
) {
312 pr_crit("Device tree not populated\n");
316 arch_initcall_sync(arm64_device_init
);
318 static int __init
topology_init(void)
322 for_each_online_node(i
)
323 register_one_node(i
);
325 for_each_possible_cpu(i
) {
326 struct cpu
*cpu
= &per_cpu(cpu_data
.cpu
, i
);
327 cpu
->hotpluggable
= 1;
328 register_cpu(cpu
, i
);
333 subsys_initcall(topology_init
);
336 * Dump out kernel offset information on panic.
338 static int dump_kernel_offset(struct notifier_block
*self
, unsigned long v
,
341 u64
const kaslr_offset
= kimage_vaddr
- KIMAGE_VADDR
;
343 if (IS_ENABLED(CONFIG_RANDOMIZE_BASE
) && kaslr_offset
> 0) {
344 pr_emerg("Kernel Offset: 0x%llx from 0x%lx\n",
345 kaslr_offset
, KIMAGE_VADDR
);
347 pr_emerg("Kernel Offset: disabled\n");
352 static struct notifier_block kernel_offset_notifier
= {
353 .notifier_call
= dump_kernel_offset
356 static int __init
register_kernel_offset_dumper(void)
358 atomic_notifier_chain_register(&panic_notifier_list
,
359 &kernel_offset_notifier
);
362 __initcall(register_kernel_offset_dumper
);