arch/arm64/kernel/setup.c

   1 /*
   2  * Based on arch/arm/kernel/setup.c
   3  *
   4  * Copyright (C) 1995-2001 Russell King
   5  * Copyright (C) 2012 ARM Ltd.
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include <linux/acpi.h>
  21 #include <linux/export.h>
  22 #include <linux/kernel.h>
  23 #include <linux/stddef.h>
  24 #include <linux/ioport.h>
  25 #include <linux/delay.h>
  26 #include <linux/utsname.h>
  27 #include <linux/initrd.h>
  28 #include <linux/console.h>
  29 #include <linux/cache.h>
  30 #include <linux/bootmem.h>
  31 #include <linux/screen_info.h>
  32 #include <linux/init.h>
  33 #include <linux/kexec.h>
  34 #include <linux/crash_dump.h>
  35 #include <linux/root_dev.h>
  36 #include <linux/cpu.h>
  37 #include <linux/interrupt.h>
  38 #include <linux/smp.h>
  39 #include <linux/fs.h>
  40 #include <linux/proc_fs.h>
  41 #include <linux/memblock.h>
  42 #include <linux/of_fdt.h>
  43 #include <linux/efi.h>
  44 #include <linux/psci.h>
  45
  46 #include <asm/acpi.h>
  47 #include <asm/fixmap.h>
  48 #include <asm/cpu.h>
  49 #include <asm/cputype.h>
  50 #include <asm/elf.h>
  51 #include <asm/cpufeature.h>
  52 #include <asm/cpu_ops.h>
  53 #include <asm/kasan.h>
  54 #include <asm/numa.h>
  55 #include <asm/sections.h>
  56 #include <asm/setup.h>
  57 #include <asm/smp_plat.h>
  58 #include <asm/cacheflush.h>
  59 #include <asm/tlbflush.h>
  60 #include <asm/traps.h>
  61 #include <asm/memblock.h>
  62 #include <asm/efi.h>
  63 #include <asm/xen/hypervisor.h>
  64 #include <asm/mmu_context.h>
  65
  66 phys_addr_t __fdt_pointer __initdata;
  67
  68 /*
  69  * Standard memory resources
  70  */
  71 static struct resource mem_res[] = {
  72         {
  73                 .name = "Kernel code",
  74                 .start = 0,
  75                 .end = 0,
  76                 .flags = IORESOURCE_SYSTEM_RAM
  77         },
  78         {
  79                 .name = "Kernel data",
  80                 .start = 0,
  81                 .end = 0,
  82                 .flags = IORESOURCE_SYSTEM_RAM
  83         }
  84 };
  85
  86 #define kernel_code mem_res[0]
  87 #define kernel_data mem_res[1]
  88
  89 /*
  90  * The recorded values of x0 .. x3 upon kernel entry.
  91  */
  92 u64 __cacheline_aligned boot_args[4];
  93
  94 void __init smp_setup_processor_id(void)
  95 {
  96         u64 mpidr = read_cpuid_mpidr() & MPIDR_HWID_BITMASK;
  97         cpu_logical_map(0) = mpidr;
  98
  99         /*
 100          * clear __my_cpu_offset on boot CPU to avoid hang caused by
 101          * using percpu variable early, for example, lockdep will
 102          * access percpu variable inside lock_release
 103          */
 104         set_my_cpu_offset(0);
 105         pr_info("Booting Linux on physical CPU 0x%lx\n", (unsigned long)mpidr);
 106 }
 107
 108 bool arch_match_cpu_phys_id(int cpu, u64 phys_id)
 109 {
 110         return phys_id == cpu_logical_map(cpu);
 111 }
 112
 113 struct mpidr_hash mpidr_hash;
 114 /**
 115  * smp_build_mpidr_hash - Pre-compute shifts required at each affinity
 116  *                        level in order to build a linear index from an
 117  *                        MPIDR value. Resulting algorithm is a collision
 118  *                        free hash carried out through shifting and ORing
 119  */
 120 static void __init smp_build_mpidr_hash(void)
 121 {
 122         u32 i, affinity, fs[4], bits[4], ls;
 123         u64 mask = 0;
 124         /*
 125          * Pre-scan the list of MPIDRS and filter out bits that do
 126          * not contribute to affinity levels, ie they never toggle.
 127          */
 128         for_each_possible_cpu(i)
 129                 mask |= (cpu_logical_map(i) ^ cpu_logical_map(0));
 130         pr_debug("mask of set bits %#llx\n", mask);
 131         /*
 132          * Find and stash the last and first bit set at all affinity levels to
 133          * check how many bits are required to represent them.
 134          */
 135         for (i = 0; i < 4; i++) {
 136                 affinity = MPIDR_AFFINITY_LEVEL(mask, i);
 137                 /*
 138                  * Find the MSB bit and LSB bits position
 139                  * to determine how many bits are required
 140                  * to express the affinity level.
 141                  */
 142                 ls = fls(affinity);
 143                 fs[i] = affinity ? ffs(affinity) - 1 : 0;
 144                 bits[i] = ls - fs[i];
 145         }
 146         /*
 147          * An index can be created from the MPIDR_EL1 by isolating the
 148          * significant bits at each affinity level and by shifting
 149          * them in order to compress the 32 bits values space to a
 150          * compressed set of values. This is equivalent to hashing
 151          * the MPIDR_EL1 through shifting and ORing. It is a collision free
 152          * hash though not minimal since some levels might contain a number
 153          * of CPUs that is not an exact power of 2 and their bit
 154          * representation might contain holes, eg MPIDR_EL1[7:0] = {0x2, 0x80}.
 155          */
 156         mpidr_hash.shift_aff[0] = MPIDR_LEVEL_SHIFT(0) + fs[0];
 157         mpidr_hash.shift_aff[1] = MPIDR_LEVEL_SHIFT(1) + fs[1] - bits[0];
 158         mpidr_hash.shift_aff[2] = MPIDR_LEVEL_SHIFT(2) + fs[2] -
 159                                                 (bits[1] + bits[0]);
 160         mpidr_hash.shift_aff[3] = MPIDR_LEVEL_SHIFT(3) +
 161                                   fs[3] - (bits[2] + bits[1] + bits[0]);
 162         mpidr_hash.mask = mask;
 163         mpidr_hash.bits = bits[3] + bits[2] + bits[1] + bits[0];
 164         pr_debug("MPIDR hash: aff0[%u] aff1[%u] aff2[%u] aff3[%u] mask[%#llx] bits[%u]\n",
 165                 mpidr_hash.shift_aff[0],
 166                 mpidr_hash.shift_aff[1],
 167                 mpidr_hash.shift_aff[2],
 168                 mpidr_hash.shift_aff[3],
 169                 mpidr_hash.mask,
 170                 mpidr_hash.bits);
 171         /*
 172          * 4x is an arbitrary value used to warn on a hash table much bigger
 173          * than expected on most systems.
 174          */
 175         if (mpidr_hash_size() > 4 * num_possible_cpus())
 176                 pr_warn("Large number of MPIDR hash buckets detected\n");
 177 }
 178
 179 static void __init setup_machine_fdt(phys_addr_t dt_phys)
 180 {
 181         void *dt_virt = fixmap_remap_fdt(dt_phys);
 182
 183         if (!dt_virt || !early_init_dt_scan(dt_virt)) {
 184                 pr_crit("\n"
 185                         "Error: invalid device tree blob at physical address %pa (virtual address 0x%p)\n"
 186                         "The dtb must be 8-byte aligned and must not exceed 2 MB in size\n"
 187                         "\nPlease check your bootloader.",
 188                         &dt_phys, dt_virt);
 189
 190                 while (true)
 191                         cpu_relax();
 192         }
 193
 194         dump_stack_set_arch_desc("%s (DT)", of_flat_dt_get_machine_name());
 195 }
 196
 197 static void __init request_standard_resources(void)
 198 {
 199         struct memblock_region *region;
 200         struct resource *res;
 201
 202         kernel_code.start   = virt_to_phys(_text);
 203         kernel_code.end     = virt_to_phys(__init_begin - 1);
 204         kernel_data.start   = virt_to_phys(_sdata);
 205         kernel_data.end     = virt_to_phys(_end - 1);
 206
 207         for_each_memblock(memory, region) {
 208                 res = alloc_bootmem_low(sizeof(*res));
 209                 res->name  = "System RAM";
 210                 res->start = __pfn_to_phys(memblock_region_memory_base_pfn(region));
 211                 res->end = __pfn_to_phys(memblock_region_memory_end_pfn(region)) - 1;
 212                 res->flags = IORESOURCE_SYSTEM_RAM | IORESOURCE_BUSY;
 213
 214                 request_resource(&iomem_resource, res);
 215
 216                 if (kernel_code.start >= res->start &&
 217                     kernel_code.end <= res->end)
 218                         request_resource(res, &kernel_code);
 219                 if (kernel_data.start >= res->start &&
 220                     kernel_data.end <= res->end)
 221                         request_resource(res, &kernel_data);
 222         }
 223 }
 224
 225 u64 __cpu_logical_map[NR_CPUS] = { [0 ... NR_CPUS-1] = INVALID_HWID };
 226
 227 void __init setup_arch(char **cmdline_p)
 228 {
 229         pr_info("Boot CPU: AArch64 Processor [%08x]\n", read_cpuid_id());
 230
 231         sprintf(init_utsname()->machine, ELF_PLATFORM);
 232         init_mm.start_code = (unsigned long) _text;
 233         init_mm.end_code   = (unsigned long) _etext;
 234         init_mm.end_data   = (unsigned long) _edata;
 235         init_mm.brk        = (unsigned long) _end;
 236
 237         *cmdline_p = boot_command_line;
 238
 239         early_fixmap_init();
 240         early_ioremap_init();
 241
 242         setup_machine_fdt(__fdt_pointer);
 243
 244         parse_early_param();
 245
 246         /*
 247          *  Unmask asynchronous aborts after bringing up possible earlycon.
 248          * (Report possible System Errors once we can report this occurred)
 249          */
 250         local_async_enable();
 251
 252         /*
 253          * TTBR0 is only used for the identity mapping at this stage. Make it
 254          * point to zero page to avoid speculatively fetching new entries.
 255          */
 256         cpu_uninstall_idmap();
 257
 258         xen_early_init();
 259         efi_init();
 260         arm64_memblock_init();
 261
 262         paging_init();
 263
 264         acpi_table_upgrade();
 265
 266         /* Parse the ACPI tables for possible boot-time configuration */
 267         acpi_boot_table_init();
 268
 269         if (acpi_disabled)
 270                 unflatten_device_tree();
 271
 272         bootmem_init();
 273
 274         kasan_init();
 275
 276         request_standard_resources();
 277
 278         early_ioremap_reset();
 279
 280         if (acpi_disabled)
 281                 psci_dt_init();
 282         else
 283                 psci_acpi_init();
 284
 285         cpu_read_bootcpu_ops();
 286         smp_init_cpus();
 287         smp_build_mpidr_hash();
 288
 289 #ifdef CONFIG_VT
 290 #if defined(CONFIG_VGA_CONSOLE)
 291         conswitchp = &vga_con;
 292 #elif defined(CONFIG_DUMMY_CONSOLE)
 293         conswitchp = &dummy_con;
 294 #endif
 295 #endif
 296         if (boot_args[1] || boot_args[2] || boot_args[3]) {
 297                 pr_err("WARNING: x1-x3 nonzero in violation of boot protocol:\n"
 298                         "\tx1: %016llx\n\tx2: %016llx\n\tx3: %016llx\n"
 299                         "This indicates a broken bootloader or old kernel\n",
 300                         boot_args[1], boot_args[2], boot_args[3]);
 301         }
 302 }
 303
 304 static int __init topology_init(void)
 305 {
 306         int i;
 307
 308         for_each_online_node(i)
 309                 register_one_node(i);
 310
 311         for_each_possible_cpu(i) {
 312                 struct cpu *cpu = &per_cpu(cpu_data.cpu, i);
 313                 cpu->hotpluggable = 1;
 314                 register_cpu(cpu, i);
 315         }
 316
 317         return 0;
 318 }
 319 subsys_initcall(topology_init);
 320
 321 /*
 322  * Dump out kernel offset information on panic.
 323  */
 324 static int dump_kernel_offset(struct notifier_block *self, unsigned long v,
 325                               void *p)
 326 {
 327         u64 const kaslr_offset = kimage_vaddr - KIMAGE_VADDR;
 328
 329         if (IS_ENABLED(CONFIG_RANDOMIZE_BASE) && kaslr_offset > 0) {
 330                 pr_emerg("Kernel Offset: 0x%llx from 0x%lx\n",
 331                          kaslr_offset, KIMAGE_VADDR);
 332         } else {
 333                 pr_emerg("Kernel Offset: disabled\n");
 334         }
 335         return 0;
 336 }
 337
 338 static struct notifier_block kernel_offset_notifier = {
 339         .notifier_call = dump_kernel_offset
 340 };
 341
 342 static int __init register_kernel_offset_dumper(void)
 343 {
 344         atomic_notifier_chain_register(&panic_notifier_list,
 345                                        &kernel_offset_notifier);
 346         return 0;
 347 }
 348 __initcall(register_kernel_offset_dumper);