arch/arm64/kernel/smp.c

   1 /*
   2  * SMP initialisation and IPI support
   3  * Based on arch/arm/kernel/smp.c
   4  *
   5  * Copyright (C) 2012 ARM Ltd.
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include <linux/delay.h>
  21 #include <linux/init.h>
  22 #include <linux/spinlock.h>
  23 #include <linux/sched.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/cache.h>
  26 #include <linux/profile.h>
  27 #include <linux/errno.h>
  28 #include <linux/mm.h>
  29 #include <linux/err.h>
  30 #include <linux/cpu.h>
  31 #include <linux/smp.h>
  32 #include <linux/seq_file.h>
  33 #include <linux/irq.h>
  34 #include <linux/percpu.h>
  35 #include <linux/clockchips.h>
  36 #include <linux/completion.h>
  37 #include <linux/of.h>
  38
  39 #include <asm/atomic.h>
  40 #include <asm/cacheflush.h>
  41 #include <asm/cputype.h>
  42 #include <asm/cpu_ops.h>
  43 #include <asm/mmu_context.h>
  44 #include <asm/pgtable.h>
  45 #include <asm/pgalloc.h>
  46 #include <asm/processor.h>
  47 #include <asm/smp_plat.h>
  48 #include <asm/sections.h>
  49 #include <asm/tlbflush.h>
  50 #include <asm/ptrace.h>
  51
  52 /*
  53  * as from 2.5, kernels no longer have an init_tasks structure
  54  * so we need some other way of telling a new secondary core
  55  * where to place its SVC stack
  56  */
  57 struct secondary_data secondary_data;
  58 volatile unsigned long secondary_holding_pen_release = INVALID_HWID;
  59
  60 enum ipi_msg_type {
  61         IPI_RESCHEDULE,
  62         IPI_CALL_FUNC,
  63         IPI_CALL_FUNC_SINGLE,
  64         IPI_CPU_STOP,
  65 };
  66
  67 static DEFINE_RAW_SPINLOCK(boot_lock);
  68
  69 /*
  70  * Write secondary_holding_pen_release in a way that is guaranteed to be
  71  * visible to all observers, irrespective of whether they're taking part
  72  * in coherency or not.  This is necessary for the hotplug code to work
  73  * reliably.
  74  */
  75 static void write_pen_release(u64 val)
  76 {
  77         void *start = (void *)&secondary_holding_pen_release;
  78         unsigned long size = sizeof(secondary_holding_pen_release);
  79
  80         secondary_holding_pen_release = val;
  81         __flush_dcache_area(start, size);
  82 }
  83
  84 /*
  85  * Boot a secondary CPU, and assign it the specified idle task.
  86  * This also gives us the initial stack to use for this CPU.
  87  */
  88 static int boot_secondary(unsigned int cpu, struct task_struct *idle)
  89 {
  90         unsigned long timeout;
  91
  92         /*
  93          * Set synchronisation state between this boot processor
  94          * and the secondary one
  95          */
  96         raw_spin_lock(&boot_lock);
  97
  98         /*
  99          * Update the pen release flag.
 100          */
 101         write_pen_release(cpu_logical_map(cpu));
 102
 103         /*
 104          * Send an event, causing the secondaries to read pen_release.
 105          */
 106         sev();
 107
 108         timeout = jiffies + (1 * HZ);
 109         while (time_before(jiffies, timeout)) {
 110                 if (secondary_holding_pen_release == INVALID_HWID)
 111                         break;
 112                 udelay(10);
 113         }
 114
 115         /*
 116          * Now the secondary core is starting up let it run its
 117          * calibrations, then wait for it to finish
 118          */
 119         raw_spin_unlock(&boot_lock);
 120
 121         return secondary_holding_pen_release != INVALID_HWID ? -ENOSYS : 0;
 122 }
 123
 124 static DECLARE_COMPLETION(cpu_running);
 125
 126 int __cpu_up(unsigned int cpu, struct task_struct *idle)
 127 {
 128         int ret;
 129
 130         /*
 131          * We need to tell the secondary core where to find its stack and the
 132          * page tables.
 133          */
 134         secondary_data.stack = task_stack_page(idle) + THREAD_START_SP;
 135         __flush_dcache_area(&secondary_data, sizeof(secondary_data));
 136
 137         /*
 138          * Now bring the CPU into our world.
 139          */
 140         ret = boot_secondary(cpu, idle);
 141         if (ret == 0) {
 142                 /*
 143                  * CPU was successfully started, wait for it to come online or
 144                  * time out.
 145                  */
 146                 wait_for_completion_timeout(&cpu_running,
 147                                             msecs_to_jiffies(1000));
 148
 149                 if (!cpu_online(cpu)) {
 150                         pr_crit("CPU%u: failed to come online\n", cpu);
 151                         ret = -EIO;
 152                 }
 153         } else {
 154                 pr_err("CPU%u: failed to boot: %d\n", cpu, ret);
 155         }
 156
 157         secondary_data.stack = NULL;
 158
 159         return ret;
 160 }
 161
 162 /*
 163  * This is the secondary CPU boot entry.  We're using this CPUs
 164  * idle thread stack, but a set of temporary page tables.
 165  */
 166 asmlinkage void secondary_start_kernel(void)
 167 {
 168         struct mm_struct *mm = &init_mm;
 169         unsigned int cpu = smp_processor_id();
 170
 171         printk("CPU%u: Booted secondary processor\n", cpu);
 172
 173         /*
 174          * All kernel threads share the same mm context; grab a
 175          * reference and switch to it.
 176          */
 177         atomic_inc(&mm->mm_count);
 178         current->active_mm = mm;
 179         cpumask_set_cpu(cpu, mm_cpumask(mm));
 180
 181         /*
 182          * TTBR0 is only used for the identity mapping at this stage. Make it
 183          * point to zero page to avoid speculatively fetching new entries.
 184          */
 185         cpu_set_reserved_ttbr0();
 186         flush_tlb_all();
 187
 188         preempt_disable();
 189         trace_hardirqs_off();
 190
 191         /*
 192          * Let the primary processor know we're out of the
 193          * pen, then head off into the C entry point
 194          */
 195         write_pen_release(INVALID_HWID);
 196
 197         /*
 198          * Synchronise with the boot thread.
 199          */
 200         raw_spin_lock(&boot_lock);
 201         raw_spin_unlock(&boot_lock);
 202
 203         /*
 204          * OK, now it's safe to let the boot CPU continue.  Wait for
 205          * the CPU migration code to notice that the CPU is online
 206          * before we continue.
 207          */
 208         set_cpu_online(cpu, true);
 209         complete(&cpu_running);
 210
 211         /*
 212          * Enable GIC and timers.
 213          */
 214         notify_cpu_starting(cpu);
 215
 216         local_irq_enable();
 217         local_fiq_enable();
 218
 219         /*
 220          * OK, it's off to the idle thread for us
 221          */
 222         cpu_startup_entry(CPUHP_ONLINE);
 223 }
 224
 225 void __init smp_cpus_done(unsigned int max_cpus)
 226 {
 227         pr_info("SMP: Total of %d processors activated.\n", num_online_cpus());
 228 }
 229
 230 void __init smp_prepare_boot_cpu(void)
 231 {
 232 }
 233
 234 static void (*smp_cross_call)(const struct cpumask *, unsigned int);
 235
 236 /*
 237  * Enumerate the possible CPU set from the device tree and build the
 238  * cpu logical map array containing MPIDR values related to logical
 239  * cpus. Assumes that cpu_logical_map(0) has already been initialized.
 240  */
 241 void __init smp_init_cpus(void)
 242 {
 243         const char *enable_method;
 244         struct device_node *dn = NULL;
 245         unsigned int i, cpu = 1;
 246         bool bootcpu_valid = false;
 247
 248         while ((dn = of_find_node_by_type(dn, "cpu"))) {
 249                 const u32 *cell;
 250                 u64 hwid;
 251
 252                 /*
 253                  * A cpu node with missing "reg" property is
 254                  * considered invalid to build a cpu_logical_map
 255                  * entry.
 256                  */
 257                 cell = of_get_property(dn, "reg", NULL);
 258                 if (!cell) {
 259                         pr_err("%s: missing reg property\n", dn->full_name);
 260                         goto next;
 261                 }
 262                 hwid = of_read_number(cell, of_n_addr_cells(dn));
 263
 264                 /*
 265                  * Non affinity bits must be set to 0 in the DT
 266                  */
 267                 if (hwid & ~MPIDR_HWID_BITMASK) {
 268                         pr_err("%s: invalid reg property\n", dn->full_name);
 269                         goto next;
 270                 }
 271
 272                 /*
 273                  * Duplicate MPIDRs are a recipe for disaster. Scan
 274                  * all initialized entries and check for
 275                  * duplicates. If any is found just ignore the cpu.
 276                  * cpu_logical_map was initialized to INVALID_HWID to
 277                  * avoid matching valid MPIDR values.
 278                  */
 279                 for (i = 1; (i < cpu) && (i < NR_CPUS); i++) {
 280                         if (cpu_logical_map(i) == hwid) {
 281                                 pr_err("%s: duplicate cpu reg properties in the DT\n",
 282                                         dn->full_name);
 283                                 goto next;
 284                         }
 285                 }
 286
 287                 /*
 288                  * The numbering scheme requires that the boot CPU
 289                  * must be assigned logical id 0. Record it so that
 290                  * the logical map built from DT is validated and can
 291                  * be used.
 292                  */
 293                 if (hwid == cpu_logical_map(0)) {
 294                         if (bootcpu_valid) {
 295                                 pr_err("%s: duplicate boot cpu reg property in DT\n",
 296                                         dn->full_name);
 297                                 goto next;
 298                         }
 299
 300                         bootcpu_valid = true;
 301
 302                         /*
 303                          * cpu_logical_map has already been
 304                          * initialized and the boot cpu doesn't need
 305                          * the enable-method so continue without
 306                          * incrementing cpu.
 307                          */
 308                         continue;
 309                 }
 310
 311                 if (cpu >= NR_CPUS)
 312                         goto next;
 313
 314                 /*
 315                  * We currently support only the "spin-table" enable-method.
 316                  */
 317                 enable_method = of_get_property(dn, "enable-method", NULL);
 318                 if (!enable_method) {
 319                         pr_err("%s: missing enable-method property\n",
 320                                 dn->full_name);
 321                         goto next;
 322                 }
 323
 324                 cpu_ops[cpu] = cpu_get_ops(enable_method);
 325
 326                 if (!cpu_ops[cpu]) {
 327                         pr_err("%s: invalid enable-method property: %s\n",
 328                                dn->full_name, enable_method);
 329                         goto next;
 330                 }
 331
 332                 if (cpu_ops[cpu]->cpu_init(dn, cpu))
 333                         goto next;
 334
 335                 pr_debug("cpu logical map 0x%llx\n", hwid);
 336                 cpu_logical_map(cpu) = hwid;
 337 next:
 338                 cpu++;
 339         }
 340
 341         /* sanity check */
 342         if (cpu > NR_CPUS)
 343                 pr_warning("no. of cores (%d) greater than configured maximum of %d - clipping\n",
 344                            cpu, NR_CPUS);
 345
 346         if (!bootcpu_valid) {
 347                 pr_err("DT missing boot CPU MPIDR, not enabling secondaries\n");
 348                 return;
 349         }
 350
 351         /*
 352          * All the cpus that made it to the cpu_logical_map have been
 353          * validated so set them as possible cpus.
 354          */
 355         for (i = 0; i < NR_CPUS; i++)
 356                 if (cpu_logical_map(i) != INVALID_HWID)
 357                         set_cpu_possible(i, true);
 358 }
 359
 360 void __init smp_prepare_cpus(unsigned int max_cpus)
 361 {
 362         int err;
 363         unsigned int cpu, ncores = num_possible_cpus();
 364
 365         /*
 366          * are we trying to boot more cores than exist?
 367          */
 368         if (max_cpus > ncores)
 369                 max_cpus = ncores;
 370
 371         /* Don't bother if we're effectively UP */
 372         if (max_cpus <= 1)
 373                 return;
 374
 375         /*
 376          * Initialise the present map (which describes the set of CPUs
 377          * actually populated at the present time) and release the
 378          * secondaries from the bootloader.
 379          *
 380          * Make sure we online at most (max_cpus - 1) additional CPUs.
 381          */
 382         max_cpus--;
 383         for_each_possible_cpu(cpu) {
 384                 if (max_cpus == 0)
 385                         break;
 386
 387                 if (cpu == smp_processor_id())
 388                         continue;
 389
 390                 if (!cpu_ops[cpu])
 391                         continue;
 392
 393                 err = cpu_ops[cpu]->cpu_prepare(cpu);
 394                 if (err)
 395                         continue;
 396
 397                 set_cpu_present(cpu, true);
 398                 max_cpus--;
 399         }
 400 }
 401
 402
 403 void __init set_smp_cross_call(void (*fn)(const struct cpumask *, unsigned int))
 404 {
 405         smp_cross_call = fn;
 406 }
 407
 408 void arch_send_call_function_ipi_mask(const struct cpumask *mask)
 409 {
 410         smp_cross_call(mask, IPI_CALL_FUNC);
 411 }
 412
 413 void arch_send_call_function_single_ipi(int cpu)
 414 {
 415         smp_cross_call(cpumask_of(cpu), IPI_CALL_FUNC_SINGLE);
 416 }
 417
 418 static const char *ipi_types[NR_IPI] = {
 419 #define S(x,s)  [x - IPI_RESCHEDULE] = s
 420         S(IPI_RESCHEDULE, "Rescheduling interrupts"),
 421         S(IPI_CALL_FUNC, "Function call interrupts"),
 422         S(IPI_CALL_FUNC_SINGLE, "Single function call interrupts"),
 423         S(IPI_CPU_STOP, "CPU stop interrupts"),
 424 };
 425
 426 void show_ipi_list(struct seq_file *p, int prec)
 427 {
 428         unsigned int cpu, i;
 429
 430         for (i = 0; i < NR_IPI; i++) {
 431                 seq_printf(p, "%*s%u:%s", prec - 1, "IPI", i + IPI_RESCHEDULE,
 432                            prec >= 4 ? " " : "");
 433                 for_each_present_cpu(cpu)
 434                         seq_printf(p, "%10u ",
 435                                    __get_irq_stat(cpu, ipi_irqs[i]));
 436                 seq_printf(p, "      %s\n", ipi_types[i]);
 437         }
 438 }
 439
 440 u64 smp_irq_stat_cpu(unsigned int cpu)
 441 {
 442         u64 sum = 0;
 443         int i;
 444
 445         for (i = 0; i < NR_IPI; i++)
 446                 sum += __get_irq_stat(cpu, ipi_irqs[i]);
 447
 448         return sum;
 449 }
 450
 451 static DEFINE_RAW_SPINLOCK(stop_lock);
 452
 453 /*
 454  * ipi_cpu_stop - handle IPI from smp_send_stop()
 455  */
 456 static void ipi_cpu_stop(unsigned int cpu)
 457 {
 458         if (system_state == SYSTEM_BOOTING ||
 459             system_state == SYSTEM_RUNNING) {
 460                 raw_spin_lock(&stop_lock);
 461                 pr_crit("CPU%u: stopping\n", cpu);
 462                 dump_stack();
 463                 raw_spin_unlock(&stop_lock);
 464         }
 465
 466         set_cpu_online(cpu, false);
 467
 468         local_fiq_disable();
 469         local_irq_disable();
 470
 471         while (1)
 472                 cpu_relax();
 473 }
 474
 475 /*
 476  * Main handler for inter-processor interrupts
 477  */
 478 void handle_IPI(int ipinr, struct pt_regs *regs)
 479 {
 480         unsigned int cpu = smp_processor_id();
 481         struct pt_regs *old_regs = set_irq_regs(regs);
 482
 483         if (ipinr >= IPI_RESCHEDULE && ipinr < IPI_RESCHEDULE + NR_IPI)
 484                 __inc_irq_stat(cpu, ipi_irqs[ipinr - IPI_RESCHEDULE]);
 485
 486         switch (ipinr) {
 487         case IPI_RESCHEDULE:
 488                 scheduler_ipi();
 489                 break;
 490
 491         case IPI_CALL_FUNC:
 492                 irq_enter();
 493                 generic_smp_call_function_interrupt();
 494                 irq_exit();
 495                 break;
 496
 497         case IPI_CALL_FUNC_SINGLE:
 498                 irq_enter();
 499                 generic_smp_call_function_single_interrupt();
 500                 irq_exit();
 501                 break;
 502
 503         case IPI_CPU_STOP:
 504                 irq_enter();
 505                 ipi_cpu_stop(cpu);
 506                 irq_exit();
 507                 break;
 508
 509         default:
 510                 pr_crit("CPU%u: Unknown IPI message 0x%x\n", cpu, ipinr);
 511                 break;
 512         }
 513         set_irq_regs(old_regs);
 514 }
 515
 516 void smp_send_reschedule(int cpu)
 517 {
 518         smp_cross_call(cpumask_of(cpu), IPI_RESCHEDULE);
 519 }
 520
 521 void smp_send_stop(void)
 522 {
 523         unsigned long timeout;
 524
 525         if (num_online_cpus() > 1) {
 526                 cpumask_t mask;
 527
 528                 cpumask_copy(&mask, cpu_online_mask);
 529                 cpu_clear(smp_processor_id(), mask);
 530
 531                 smp_cross_call(&mask, IPI_CPU_STOP);
 532         }
 533
 534         /* Wait up to one second for other CPUs to stop */
 535         timeout = USEC_PER_SEC;
 536         while (num_online_cpus() > 1 && timeout--)
 537                 udelay(1);
 538
 539         if (num_online_cpus() > 1)
 540                 pr_warning("SMP: failed to stop secondary CPUs\n");
 541 }
 542
 543 /*
 544  * not supported here
 545  */
 546 int setup_profiling_timer(unsigned int multiplier)
 547 {
 548         return -EINVAL;
 549 }