arch/arm64/mm/proc.S

   1 /*
   2  * Based on arch/arm/mm/proc.S
   3  *
   4  * Copyright (C) 2001 Deep Blue Solutions Ltd.
   5  * Copyright (C) 2012 ARM Ltd.
   6  * Author: Catalin Marinas <catalin.marinas@arm.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  19  */
  20
  21 #include <linux/init.h>
  22 #include <linux/linkage.h>
  23 #include <asm/assembler.h>
  24 #include <asm/asm-offsets.h>
  25 #include <asm/hwcap.h>
  26 #include <asm/pgtable-hwdef.h>
  27 #include <asm/pgtable.h>
  28
  29 #include "proc-macros.S"
  30
  31 #ifdef CONFIG_ARM64_64K_PAGES
  32 #define TCR_TG_FLAGS    TCR_TG0_64K | TCR_TG1_64K
  33 #elif defined(CONFIG_ARM64_16K_PAGES)
  34 #define TCR_TG_FLAGS    TCR_TG0_16K | TCR_TG1_16K
  35 #else /* CONFIG_ARM64_4K_PAGES */
  36 #define TCR_TG_FLAGS    TCR_TG0_4K | TCR_TG1_4K
  37 #endif
  38
  39 #define TCR_SMP_FLAGS   TCR_SHARED
  40
  41 /* PTWs cacheable, inner/outer WBWA */
  42 #define TCR_CACHE_FLAGS TCR_IRGN_WBWA | TCR_ORGN_WBWA
  43
  44 #define MAIR(attr, mt)  ((attr) << ((mt) * 8))
  45
  46 /*
  47  *      cpu_do_idle()
  48  *
  49  *      Idle the processor (wait for interrupt).
  50  */
  51 ENTRY(cpu_do_idle)
  52         dsb     sy                              // WFI may enter a low-power mode
  53         wfi
  54         ret
  55 ENDPROC(cpu_do_idle)
  56
  57 #ifdef CONFIG_CPU_PM
  58 /**
  59  * cpu_do_suspend - save CPU registers context
  60  *
  61  * x0: virtual address of context pointer
  62  */
  63 ENTRY(cpu_do_suspend)
  64         mrs     x2, tpidr_el0
  65         mrs     x3, tpidrro_el0
  66         mrs     x4, contextidr_el1
  67         mrs     x5, mair_el1
  68         mrs     x6, cpacr_el1
  69         mrs     x7, ttbr1_el1
  70         mrs     x8, tcr_el1
  71         mrs     x9, vbar_el1
  72         mrs     x10, mdscr_el1
  73         mrs     x11, oslsr_el1
  74         mrs     x12, sctlr_el1
  75         stp     x2, x3, [x0]
  76         stp     x4, x5, [x0, #16]
  77         stp     x6, x7, [x0, #32]
  78         stp     x8, x9, [x0, #48]
  79         stp     x10, x11, [x0, #64]
  80         str     x12, [x0, #80]
  81         ret
  82 ENDPROC(cpu_do_suspend)
  83
  84 /**
  85  * cpu_do_resume - restore CPU register context
  86  *
  87  * x0: Physical address of context pointer
  88  * x1: ttbr0_el1 to be restored
  89  *
  90  * Returns:
  91  *      sctlr_el1 value in x0
  92  */
  93 ENTRY(cpu_do_resume)
  94         /*
  95          * Invalidate local tlb entries before turning on MMU
  96          */
  97         tlbi    vmalle1
  98         ldp     x2, x3, [x0]
  99         ldp     x4, x5, [x0, #16]
 100         ldp     x6, x7, [x0, #32]
 101         ldp     x8, x9, [x0, #48]
 102         ldp     x10, x11, [x0, #64]
 103         ldr     x12, [x0, #80]
 104         msr     tpidr_el0, x2
 105         msr     tpidrro_el0, x3
 106         msr     contextidr_el1, x4
 107         msr     mair_el1, x5
 108         msr     cpacr_el1, x6
 109         msr     ttbr0_el1, x1
 110         msr     ttbr1_el1, x7
 111         tcr_set_idmap_t0sz x8, x7
 112         msr     tcr_el1, x8
 113         msr     vbar_el1, x9
 114         msr     mdscr_el1, x10
 115         /*
 116          * Restore oslsr_el1 by writing oslar_el1
 117          */
 118         ubfx    x11, x11, #1, #1
 119         msr     oslar_el1, x11
 120         reset_pmuserenr_el0 x0                  // Disable PMU access from EL0
 121         mov     x0, x12
 122         dsb     nsh             // Make sure local tlb invalidation completed
 123         isb
 124         ret
 125 ENDPROC(cpu_do_resume)
 126 #endif
 127
 128 /*
 129  *      cpu_do_switch_mm(pgd_phys, tsk)
 130  *
 131  *      Set the translation table base pointer to be pgd_phys.
 132  *
 133  *      - pgd_phys - physical address of new TTB
 134  */
 135 ENTRY(cpu_do_switch_mm)
 136         mmid    x1, x1                          // get mm->context.id
 137         bfi     x0, x1, #48, #16                // set the ASID
 138         msr     ttbr0_el1, x0                   // set TTBR0
 139         isb
 140         ret
 141 ENDPROC(cpu_do_switch_mm)
 142
 143 /*
 144  *      __cpu_setup
 145  *
 146  *      Initialise the processor for turning the MMU on.  Return in x0 the
 147  *      value of the SCTLR_EL1 register.
 148  */
 149 ENTRY(__cpu_setup)
 150         tlbi    vmalle1                         // Invalidate local TLB
 151         dsb     nsh
 152
 153         mov     x0, #3 << 20
 154         msr     cpacr_el1, x0                   // Enable FP/ASIMD
 155         mov     x0, #1 << 12                    // Reset mdscr_el1 and disable
 156         msr     mdscr_el1, x0                   // access to the DCC from EL0
 157         reset_pmuserenr_el0 x0                  // Disable PMU access from EL0
 158         /*
 159          * Memory region attributes for LPAE:
 160          *
 161          *   n = AttrIndx[2:0]
 162          *                      n       MAIR
 163          *   DEVICE_nGnRnE      000     00000000
 164          *   DEVICE_nGnRE       001     00000100
 165          *   DEVICE_GRE         010     00001100
 166          *   NORMAL_NC          011     01000100
 167          *   NORMAL             100     11111111
 168          *   NORMAL_WT          101     10111011
 169          */
 170         ldr     x5, =MAIR(0x00, MT_DEVICE_nGnRnE) | \
 171                      MAIR(0x04, MT_DEVICE_nGnRE) | \
 172                      MAIR(0x0c, MT_DEVICE_GRE) | \
 173                      MAIR(0x44, MT_NORMAL_NC) | \
 174                      MAIR(0xff, MT_NORMAL) | \
 175                      MAIR(0xbb, MT_NORMAL_WT)
 176         msr     mair_el1, x5
 177         /*
 178          * Prepare SCTLR
 179          */
 180         adr     x5, crval
 181         ldp     w5, w6, [x5]
 182         mrs     x0, sctlr_el1
 183         bic     x0, x0, x5                      // clear bits
 184         orr     x0, x0, x6                      // set bits
 185         /*
 186          * Set/prepare TCR and TTBR. We use 512GB (39-bit) address range for
 187          * both user and kernel.
 188          */
 189         ldr     x10, =TCR_TxSZ(VA_BITS) | TCR_CACHE_FLAGS | TCR_SMP_FLAGS | \
 190                         TCR_TG_FLAGS | TCR_ASID16 | TCR_TBI0
 191         tcr_set_idmap_t0sz      x10, x9
 192
 193         /*
 194          * Read the PARange bits from ID_AA64MMFR0_EL1 and set the IPS bits in
 195          * TCR_EL1.
 196          */
 197         mrs     x9, ID_AA64MMFR0_EL1
 198         bfi     x10, x9, #32, #3
 199 #ifdef CONFIG_ARM64_HW_AFDBM
 200         /*
 201          * Hardware update of the Access and Dirty bits.
 202          */
 203         mrs     x9, ID_AA64MMFR1_EL1
 204         and     x9, x9, #0xf
 205         cbz     x9, 2f
 206         cmp     x9, #2
 207         b.lt    1f
 208         orr     x10, x10, #TCR_HD               // hardware Dirty flag update
 209 1:      orr     x10, x10, #TCR_HA               // hardware Access flag update
 210 2:
 211 #endif  /* CONFIG_ARM64_HW_AFDBM */
 212         msr     tcr_el1, x10
 213         ret                                     // return to head.S
 214 ENDPROC(__cpu_setup)
 215
 216         /*
 217          * We set the desired value explicitly, including those of the
 218          * reserved bits. The values of bits EE & E0E were set early in
 219          * el2_setup, which are left untouched below.
 220          *
 221          *                 n n            T
 222          *       U E      WT T UD     US IHBS
 223          *       CE0      XWHW CZ     ME TEEA S
 224          * .... .IEE .... NEAI TE.I ..AD DEN0 ACAM
 225          * 0011 0... 1101 ..0. ..0. 10.. .0.. .... < hardware reserved
 226          * .... .1.. .... 01.1 11.1 ..01 0.01 1101 < software settings
 227          */
 228         .type   crval, #object
 229 crval:
 230         .word   0xfcffffff                      // clear
 231         .word   0x34d5d91d                      // set