arch/blackfin/Kconfig

   1 #
   2 # For a description of the syntax of this configuration file,
   3 # see Documentation/kbuild/kconfig-language.txt.
   4 #
   5
   6 mainmenu "Blackfin Kernel Configuration"
   7
   8 config MMU
   9         bool
  10         default n
  11
  12 config FPU
  13         bool
  14         default n
  15
  16 config RWSEM_GENERIC_SPINLOCK
  17         bool
  18         default y
  19
  20 config RWSEM_XCHGADD_ALGORITHM
  21         bool
  22         default n
  23
  24 config BLACKFIN
  25         bool
  26         default y
  27         select HAVE_IDE
  28         select HAVE_OPROFILE
  29         select ARCH_WANT_OPTIONAL_GPIOLIB
  30
  31 config ZONE_DMA
  32         bool
  33         default y
  34
  35 config GENERIC_FIND_NEXT_BIT
  36         bool
  37         default y
  38
  39 config GENERIC_HWEIGHT
  40         bool
  41         default y
  42
  43 config GENERIC_HARDIRQS
  44         bool
  45         default y
  46
  47 config GENERIC_IRQ_PROBE
  48         bool
  49         default y
  50
  51 config GENERIC_GPIO
  52         bool
  53         default y
  54
  55 config FORCE_MAX_ZONEORDER
  56         int
  57         default "14"
  58
  59 config GENERIC_CALIBRATE_DELAY
  60         bool
  61         default y
  62
  63 source "init/Kconfig"
  64
  65 source "kernel/Kconfig.preempt"
  66
  67 source "kernel/Kconfig.freezer"
  68
  69 menu "Blackfin Processor Options"
  70
  71 comment "Processor and Board Settings"
  72
  73 choice
  74         prompt "CPU"
  75         default BF533
  76
  77 config BF512
  78         bool "BF512"
  79         help
  80           BF512 Processor Support.
  81
  82 config BF514
  83         bool "BF514"
  84         help
  85           BF514 Processor Support.
  86
  87 config BF516
  88         bool "BF516"
  89         help
  90           BF516 Processor Support.
  91
  92 config BF518
  93         bool "BF518"
  94         help
  95           BF518 Processor Support.
  96
  97 config BF522
  98         bool "BF522"
  99         help
 100           BF522 Processor Support.
 101
 102 config BF523
 103         bool "BF523"
 104         help
 105           BF523 Processor Support.
 106
 107 config BF524
 108         bool "BF524"
 109         help
 110           BF524 Processor Support.
 111
 112 config BF525
 113         bool "BF525"
 114         help
 115           BF525 Processor Support.
 116
 117 config BF526
 118         bool "BF526"
 119         help
 120           BF526 Processor Support.
 121
 122 config BF527
 123         bool "BF527"
 124         help
 125           BF527 Processor Support.
 126
 127 config BF531
 128         bool "BF531"
 129         help
 130           BF531 Processor Support.
 131
 132 config BF532
 133         bool "BF532"
 134         help
 135           BF532 Processor Support.
 136
 137 config BF533
 138         bool "BF533"
 139         help
 140           BF533 Processor Support.
 141
 142 config BF534
 143         bool "BF534"
 144         help
 145           BF534 Processor Support.
 146
 147 config BF536
 148         bool "BF536"
 149         help
 150           BF536 Processor Support.
 151
 152 config BF537
 153         bool "BF537"
 154         help
 155           BF537 Processor Support.
 156
 157 config BF538
 158         bool "BF538"
 159         help
 160           BF538 Processor Support.
 161
 162 config BF539
 163         bool "BF539"
 164         help
 165           BF539 Processor Support.
 166
 167 config BF542
 168         bool "BF542"
 169         help
 170           BF542 Processor Support.
 171
 172 config BF542M
 173         bool "BF542m"
 174         help
 175           BF542 Processor Support.
 176
 177 config BF544
 178         bool "BF544"
 179         help
 180           BF544 Processor Support.
 181
 182 config BF544M
 183         bool "BF544m"
 184         help
 185           BF544 Processor Support.
 186
 187 config BF547
 188         bool "BF547"
 189         help
 190           BF547 Processor Support.
 191
 192 config BF547M
 193         bool "BF547m"
 194         help
 195           BF547 Processor Support.
 196
 197 config BF548
 198         bool "BF548"
 199         help
 200           BF548 Processor Support.
 201
 202 config BF548M
 203         bool "BF548m"
 204         help
 205           BF548 Processor Support.
 206
 207 config BF549
 208         bool "BF549"
 209         help
 210           BF549 Processor Support.
 211
 212 config BF549M
 213         bool "BF549m"
 214         help
 215           BF549 Processor Support.
 216
 217 config BF561
 218         bool "BF561"
 219         help
 220           BF561 Processor Support.
 221
 222 endchoice
 223
 224 config SMP
 225         depends on BF561
 226         bool "Symmetric multi-processing support"
 227         ---help---
 228           This enables support for systems with more than one CPU,
 229           like the dual core BF561. If you have a system with only one
 230           CPU, say N. If you have a system with more than one CPU, say Y.
 231
 232           If you don't know what to do here, say N.
 233
 234 config NR_CPUS
 235         int
 236         depends on SMP
 237         default 2 if BF561
 238
 239 config IRQ_PER_CPU
 240         bool
 241         depends on SMP
 242         default y
 243
 244 config TICK_SOURCE_SYSTMR0
 245         bool
 246         select BFIN_GPTIMERS
 247         depends on SMP
 248         default y
 249
 250 config BF_REV_MIN
 251         int
 252         default 0 if (BF51x || BF52x || (BF54x && !BF54xM))
 253         default 2 if (BF537 || BF536 || BF534)
 254         default 3 if (BF561 || BF533 || BF532 || BF531 || BF54xM)
 255         default 4 if (BF538 || BF539)
 256
 257 config BF_REV_MAX
 258         int
 259         default 2 if (BF51x || BF52x || (BF54x && !BF54xM))
 260         default 3 if (BF537 || BF536 || BF534 || BF54xM)
 261         default 5 if (BF561 || BF538 || BF539)
 262         default 6 if (BF533 || BF532 || BF531)
 263
 264 choice
 265         prompt "Silicon Rev"
 266         default BF_REV_0_1 if (BF51x || BF52x || (BF54x && !BF54xM))
 267         default BF_REV_0_2 if (BF534 || BF536 || BF537)
 268         default BF_REV_0_3 if (BF531 || BF532 || BF533 || BF54xM || BF561)
 269
 270 config BF_REV_0_0
 271         bool "0.0"
 272         depends on (BF51x || BF52x || (BF54x && !BF54xM))
 273
 274 config BF_REV_0_1
 275         bool "0.1"
 276         depends on (BF52x || (BF54x && !BF54xM))
 277
 278 config BF_REV_0_2
 279         bool "0.2"
 280         depends on (BF52x || BF537 || BF536 || BF534 || (BF54x && !BF54xM))
 281
 282 config BF_REV_0_3
 283         bool "0.3"
 284         depends on (BF54xM || BF561 || BF537 || BF536 || BF534 || BF533 || BF532 || BF531)
 285
 286 config BF_REV_0_4
 287         bool "0.4"
 288         depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539)
 289
 290 config BF_REV_0_5
 291         bool "0.5"
 292         depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539)
 293
 294 config BF_REV_0_6
 295         bool "0.6"
 296         depends on (BF533 || BF532 || BF531)
 297
 298 config BF_REV_ANY
 299         bool "any"
 300
 301 config BF_REV_NONE
 302         bool "none"
 303
 304 endchoice
 305
 306 config BF51x
 307         bool
 308         depends on (BF512 || BF514 || BF516 || BF518)
 309         default y
 310
 311 config BF52x
 312         bool
 313         depends on (BF522 || BF523 || BF524 || BF525 || BF526 || BF527)
 314         default y
 315
 316 config BF53x
 317         bool
 318         depends on (BF531 || BF532 || BF533 || BF534 || BF536 || BF537)
 319         default y
 320
 321 config BF54xM
 322         bool
 323         depends on (BF542M || BF544M || BF547M || BF548M || BF549M)
 324         default y
 325
 326 config BF54x
 327         bool
 328         depends on (BF542 || BF544 || BF547 || BF548 || BF549 || BF54xM)
 329         default y
 330
 331 config MEM_GENERIC_BOARD
 332         bool
 333         depends on GENERIC_BOARD
 334         default y
 335
 336 config MEM_MT48LC64M4A2FB_7E
 337         bool
 338         depends on (BFIN533_STAMP)
 339         default y
 340
 341 config MEM_MT48LC16M16A2TG_75
 342         bool
 343         depends on (BFIN533_EZKIT || BFIN561_EZKIT \
 344                 || BFIN533_BLUETECHNIX_CM || BFIN537_BLUETECHNIX_CM \
 345                 || H8606_HVSISTEMAS || BFIN527_BLUETECHNIX_CM)
 346         default y
 347
 348 config MEM_MT48LC32M8A2_75
 349         bool
 350         depends on (BFIN537_STAMP || PNAV10 || BFIN538_EZKIT)
 351         default y
 352
 353 config MEM_MT48LC8M32B2B5_7
 354         bool
 355         depends on (BFIN561_BLUETECHNIX_CM)
 356         default y
 357
 358 config MEM_MT48LC32M16A2TG_75
 359         bool
 360         depends on (BFIN527_EZKIT || BFIN532_IP0X || BLACKSTAMP || BFIN526_EZBRD)
 361         default y
 362
 363 config MEM_MT48LC32M8A2_75
 364         bool
 365         depends on (BFIN518F_EZBRD)
 366         default y
 367
 368 source "arch/blackfin/mach-bf518/Kconfig"
 369 source "arch/blackfin/mach-bf527/Kconfig"
 370 source "arch/blackfin/mach-bf533/Kconfig"
 371 source "arch/blackfin/mach-bf561/Kconfig"
 372 source "arch/blackfin/mach-bf537/Kconfig"
 373 source "arch/blackfin/mach-bf538/Kconfig"
 374 source "arch/blackfin/mach-bf548/Kconfig"
 375
 376 menu "Board customizations"
 377
 378 config CMDLINE_BOOL
 379         bool "Default bootloader kernel arguments"
 380
 381 config CMDLINE
 382         string "Initial kernel command string"
 383         depends on CMDLINE_BOOL
 384         default "console=ttyBF0,57600"
 385         help
 386           If you don't have a boot loader capable of passing a command line string
 387           to the kernel, you may specify one here. As a minimum, you should specify
 388           the memory size and the root device (e.g., mem=8M, root=/dev/nfs).
 389
 390 config BOOT_LOAD
 391         hex "Kernel load address for booting"
 392         default "0x1000"
 393         range 0x1000 0x20000000
 394         help
 395           This option allows you to set the load address of the kernel.
 396           This can be useful if you are on a board which has a small amount
 397           of memory or you wish to reserve some memory at the beginning of
 398           the address space.
 399
 400           Note that you need to keep this value above 4k (0x1000) as this
 401           memory region is used to capture NULL pointer references as well
 402           as some core kernel functions.
 403
 404 config ROM_BASE
 405         hex "Kernel ROM Base"
 406         depends on ROMKERNEL
 407         default "0x20040000"
 408         range 0x20000000 0x20400000 if !(BF54x || BF561)
 409         range 0x20000000 0x30000000 if (BF54x || BF561)
 410         help
 411
 412 comment "Clock/PLL Setup"
 413
 414 config CLKIN_HZ
 415         int "Frequency of the crystal on the board in Hz"
 416         default "11059200" if BFIN533_STAMP
 417         default "27000000" if BFIN533_EZKIT
 418         default "25000000" if (BFIN537_STAMP || BFIN527_EZKIT || H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD || BFIN538_EZKIT || BFIN518F-EZBRD)
 419         default "30000000" if BFIN561_EZKIT
 420         default "24576000" if PNAV10
 421         default "10000000" if BFIN532_IP0X
 422         help
 423           The frequency of CLKIN crystal oscillator on the board in Hz.
 424           Warning: This value should match the crystal on the board. Otherwise,
 425           peripherals won't work properly.
 426
 427 config BFIN_KERNEL_CLOCK
 428         bool "Re-program Clocks while Kernel boots?"
 429         default n
 430         help
 431           This option decides if kernel clocks are re-programed from the
 432           bootloader settings. If the clocks are not set, the SDRAM settings
 433           are also not changed, and the Bootloader does 100% of the hardware
 434           configuration.
 435
 436 config PLL_BYPASS
 437         bool "Bypass PLL"
 438         depends on BFIN_KERNEL_CLOCK
 439         default n
 440
 441 config CLKIN_HALF
 442         bool "Half Clock In"
 443         depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
 444         default n
 445         help
 446           If this is set the clock will be divided by 2, before it goes to the PLL.
 447
 448 config VCO_MULT
 449         int "VCO Multiplier"
 450         depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
 451         range 1 64
 452         default "22" if BFIN533_EZKIT
 453         default "45" if BFIN533_STAMP
 454         default "20" if (BFIN537_STAMP || BFIN527_EZKIT || BFIN548_EZKIT || BFIN548_BLUETECHNIX_CM || BFIN538_EZKIT)
 455         default "22" if BFIN533_BLUETECHNIX_CM
 456         default "20" if (BFIN537_BLUETECHNIX_CM || BFIN527_BLUETECHNIX_CM || BFIN561_BLUETECHNIX_CM)
 457         default "20" if BFIN561_EZKIT
 458         default "16" if (H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD || BFIN518F_EZBRD)
 459         help
 460           This controls the frequency of the on-chip PLL. This can be between 1 and 64.
 461           PLL Frequency = (Crystal Frequency) * (this setting)
 462
 463 choice
 464         prompt "Core Clock Divider"
 465         depends on BFIN_KERNEL_CLOCK
 466         default CCLK_DIV_1
 467         help
 468           This sets the frequency of the core. It can be 1, 2, 4 or 8
 469           Core Frequency = (PLL frequency) / (this setting)
 470
 471 config CCLK_DIV_1
 472         bool "1"
 473
 474 config CCLK_DIV_2
 475         bool "2"
 476
 477 config CCLK_DIV_4
 478         bool "4"
 479
 480 config CCLK_DIV_8
 481         bool "8"
 482 endchoice
 483
 484 config SCLK_DIV
 485         int "System Clock Divider"
 486         depends on BFIN_KERNEL_CLOCK
 487         range 1 15
 488         default 5
 489         help
 490           This sets the frequency of the system clock (including SDRAM or DDR).
 491           This can be between 1 and 15
 492           System Clock = (PLL frequency) / (this setting)
 493
 494 choice
 495         prompt "DDR SDRAM Chip Type"
 496         depends on BFIN_KERNEL_CLOCK
 497         depends on BF54x
 498         default MEM_MT46V32M16_5B
 499
 500 config MEM_MT46V32M16_6T
 501         bool "MT46V32M16_6T"
 502
 503 config MEM_MT46V32M16_5B
 504         bool "MT46V32M16_5B"
 505 endchoice
 506
 507 choice
 508         prompt "DDR/SDRAM Timing"
 509         depends on BFIN_KERNEL_CLOCK
 510         default BFIN_KERNEL_CLOCK_MEMINIT_CALC
 511         help
 512           This option allows you to specify Blackfin SDRAM/DDR Timing parameters
 513           The calculated SDRAM timing parameters may not be 100%
 514           accurate - This option is therefore marked experimental.
 515
 516 config BFIN_KERNEL_CLOCK_MEMINIT_CALC
 517         bool "Calculate Timings (EXPERIMENTAL)"
 518         depends on EXPERIMENTAL
 519
 520 config BFIN_KERNEL_CLOCK_MEMINIT_SPEC
 521         bool "Provide accurate Timings based on target SCLK"
 522         help
 523           Please consult the Blackfin Hardware Reference Manuals as well
 524           as the memory device datasheet.
 525           http://docs.blackfin.uclinux.org/doku.php?id=bfin:sdram
 526 endchoice
 527
 528 menu "Memory Init Control"
 529         depends on BFIN_KERNEL_CLOCK_MEMINIT_SPEC
 530
 531 config MEM_DDRCTL0
 532         depends on BF54x
 533         hex "DDRCTL0"
 534         default 0x0
 535
 536 config MEM_DDRCTL1
 537         depends on BF54x
 538         hex "DDRCTL1"
 539         default 0x0
 540
 541 config MEM_DDRCTL2
 542         depends on BF54x
 543         hex "DDRCTL2"
 544         default 0x0
 545
 546 config MEM_EBIU_DDRQUE
 547         depends on BF54x
 548         hex "DDRQUE"
 549         default 0x0
 550
 551 config MEM_SDRRC
 552         depends on !BF54x
 553         hex "SDRRC"
 554         default 0x0
 555
 556 config MEM_SDGCTL
 557         depends on !BF54x
 558         hex "SDGCTL"
 559         default 0x0
 560 endmenu
 561
 562 #
 563 # Max & Min Speeds for various Chips
 564 #
 565 config MAX_VCO_HZ
 566         int
 567         default 400000000 if BF512
 568         default 400000000 if BF514
 569         default 400000000 if BF516
 570         default 400000000 if BF518
 571         default 600000000 if BF522
 572         default 400000000 if BF523
 573         default 400000000 if BF524
 574         default 600000000 if BF525
 575         default 400000000 if BF526
 576         default 600000000 if BF527
 577         default 400000000 if BF531
 578         default 400000000 if BF532
 579         default 750000000 if BF533
 580         default 500000000 if BF534
 581         default 400000000 if BF536
 582         default 600000000 if BF537
 583         default 533333333 if BF538
 584         default 533333333 if BF539
 585         default 600000000 if BF542
 586         default 533333333 if BF544
 587         default 600000000 if BF547
 588         default 600000000 if BF548
 589         default 533333333 if BF549
 590         default 600000000 if BF561
 591
 592 config MIN_VCO_HZ
 593         int
 594         default 50000000
 595
 596 config MAX_SCLK_HZ
 597         int
 598         default 133333333
 599
 600 config MIN_SCLK_HZ
 601         int
 602         default 27000000
 603
 604 comment "Kernel Timer/Scheduler"
 605
 606 source kernel/Kconfig.hz
 607
 608 config GENERIC_TIME
 609         bool "Generic time"
 610         depends on !SMP
 611         default y
 612
 613 config GENERIC_CLOCKEVENTS
 614         bool "Generic clock events"
 615         depends on GENERIC_TIME
 616         default y
 617
 618 config CYCLES_CLOCKSOURCE
 619         bool "Use 'CYCLES' as a clocksource (EXPERIMENTAL)"
 620         depends on EXPERIMENTAL
 621         depends on GENERIC_CLOCKEVENTS
 622         depends on !BFIN_SCRATCH_REG_CYCLES
 623         default n
 624         help
 625           If you say Y here, you will enable support for using the 'cycles'
 626           registers as a clock source.  Doing so means you will be unable to
 627           safely write to the 'cycles' register during runtime.  You will
 628           still be able to read it (such as for performance monitoring), but
 629           writing the registers will most likely crash the kernel.
 630
 631 source kernel/time/Kconfig
 632
 633 comment "Misc"
 634
 635 choice
 636         prompt "Blackfin Exception Scratch Register"
 637         default BFIN_SCRATCH_REG_RETN
 638         help
 639           Select the resource to reserve for the Exception handler:
 640             - RETN: Non-Maskable Interrupt (NMI)
 641             - RETE: Exception Return (JTAG/ICE)
 642             - CYCLES: Performance counter
 643
 644           If you are unsure, please select "RETN".
 645
 646 config BFIN_SCRATCH_REG_RETN
 647         bool "RETN"
 648         help
 649           Use the RETN register in the Blackfin exception handler
 650           as a stack scratch register.  This means you cannot
 651           safely use NMI on the Blackfin while running Linux, but
 652           you can debug the system with a JTAG ICE and use the
 653           CYCLES performance registers.
 654
 655           If you are unsure, please select "RETN".
 656
 657 config BFIN_SCRATCH_REG_RETE
 658         bool "RETE"
 659         help
 660           Use the RETE register in the Blackfin exception handler
 661           as a stack scratch register.  This means you cannot
 662           safely use a JTAG ICE while debugging a Blackfin board,
 663           but you can safely use the CYCLES performance registers
 664           and the NMI.
 665
 666           If you are unsure, please select "RETN".
 667
 668 config BFIN_SCRATCH_REG_CYCLES
 669         bool "CYCLES"
 670         help
 671           Use the CYCLES register in the Blackfin exception handler
 672           as a stack scratch register.  This means you cannot
 673           safely use the CYCLES performance registers on a Blackfin
 674           board at anytime, but you can debug the system with a JTAG
 675           ICE and use the NMI.
 676
 677           If you are unsure, please select "RETN".
 678
 679 endchoice
 680
 681 endmenu
 682
 683
 684 menu "Blackfin Kernel Optimizations"
 685         depends on !SMP
 686
 687 comment "Memory Optimizations"
 688
 689 config I_ENTRY_L1
 690         bool "Locate interrupt entry code in L1 Memory"
 691         default y
 692         help
 693           If enabled, interrupt entry code (STORE/RESTORE CONTEXT) is linked
 694           into L1 instruction memory. (less latency)
 695
 696 config EXCPT_IRQ_SYSC_L1
 697         bool "Locate entire ASM lowlevel exception / interrupt - Syscall and CPLB handler code in L1 Memory"
 698         default y
 699         help
 700           If enabled, the entire ASM lowlevel exception and interrupt entry code
 701           (STORE/RESTORE CONTEXT) is linked into L1 instruction memory.
 702           (less latency)
 703
 704 config DO_IRQ_L1
 705         bool "Locate frequently called do_irq dispatcher function in L1 Memory"
 706         default y
 707         help
 708           If enabled, the frequently called do_irq dispatcher function is linked
 709           into L1 instruction memory. (less latency)
 710
 711 config CORE_TIMER_IRQ_L1
 712         bool "Locate frequently called timer_interrupt() function in L1 Memory"
 713         default y
 714         help
 715           If enabled, the frequently called timer_interrupt() function is linked
 716           into L1 instruction memory. (less latency)
 717
 718 config IDLE_L1
 719         bool "Locate frequently idle function in L1 Memory"
 720         default y
 721         help
 722           If enabled, the frequently called idle function is linked
 723           into L1 instruction memory. (less latency)
 724
 725 config SCHEDULE_L1
 726         bool "Locate kernel schedule function in L1 Memory"
 727         default y
 728         help
 729           If enabled, the frequently called kernel schedule is linked
 730           into L1 instruction memory. (less latency)
 731
 732 config ARITHMETIC_OPS_L1
 733         bool "Locate kernel owned arithmetic functions in L1 Memory"
 734         default y
 735         help
 736           If enabled, arithmetic functions are linked
 737           into L1 instruction memory. (less latency)
 738
 739 config ACCESS_OK_L1
 740         bool "Locate access_ok function in L1 Memory"
 741         default y
 742         help
 743           If enabled, the access_ok function is linked
 744           into L1 instruction memory. (less latency)
 745
 746 config MEMSET_L1
 747         bool "Locate memset function in L1 Memory"
 748         default y
 749         help
 750           If enabled, the memset function is linked
 751           into L1 instruction memory. (less latency)
 752
 753 config MEMCPY_L1
 754         bool "Locate memcpy function in L1 Memory"
 755         default y
 756         help
 757           If enabled, the memcpy function is linked
 758           into L1 instruction memory. (less latency)
 759
 760 config SYS_BFIN_SPINLOCK_L1
 761         bool "Locate sys_bfin_spinlock function in L1 Memory"
 762         default y
 763         help
 764           If enabled, sys_bfin_spinlock function is linked
 765           into L1 instruction memory. (less latency)
 766
 767 config IP_CHECKSUM_L1
 768         bool "Locate IP Checksum function in L1 Memory"
 769         default n
 770         help
 771           If enabled, the IP Checksum function is linked
 772           into L1 instruction memory. (less latency)
 773
 774 config CACHELINE_ALIGNED_L1
 775         bool "Locate cacheline_aligned data to L1 Data Memory"
 776         default y if !BF54x
 777         default n if BF54x
 778         depends on !BF531
 779         help
 780           If enabled, cacheline_anligned data is linked
 781           into L1 data memory. (less latency)
 782
 783 config SYSCALL_TAB_L1
 784         bool "Locate Syscall Table L1 Data Memory"
 785         default n
 786         depends on !BF531
 787         help
 788           If enabled, the Syscall LUT is linked
 789           into L1 data memory. (less latency)
 790
 791 config CPLB_SWITCH_TAB_L1
 792         bool "Locate CPLB Switch Tables L1 Data Memory"
 793         default n
 794         depends on !BF531
 795         help
 796           If enabled, the CPLB Switch Tables are linked
 797           into L1 data memory. (less latency)
 798
 799 config APP_STACK_L1
 800         bool "Support locating application stack in L1 Scratch Memory"
 801         default y
 802         help
 803           If enabled the application stack can be located in L1
 804           scratch memory (less latency).
 805
 806           Currently only works with FLAT binaries.
 807
 808 config EXCEPTION_L1_SCRATCH
 809         bool "Locate exception stack in L1 Scratch Memory"
 810         default n
 811         depends on !APP_STACK_L1 && !SYSCALL_TAB_L1
 812         help
 813           Whenever an exception occurs, use the L1 Scratch memory for
 814           stack storage.  You cannot place the stacks of FLAT binaries
 815           in L1 when using this option.
 816
 817           If you don't use L1 Scratch, then you should say Y here.
 818
 819 comment "Speed Optimizations"
 820 config BFIN_INS_LOWOVERHEAD
 821         bool "ins[bwl] low overhead, higher interrupt latency"
 822         default y
 823         help
 824           Reads on the Blackfin are speculative. In Blackfin terms, this means
 825           they can be interrupted at any time (even after they have been issued
 826           on to the external bus), and re-issued after the interrupt occurs.
 827           For memory - this is not a big deal, since memory does not change if
 828           it sees a read.
 829
 830           If a FIFO is sitting on the end of the read, it will see two reads,
 831           when the core only sees one since the FIFO receives both the read
 832           which is cancelled (and not delivered to the core) and the one which
 833           is re-issued (which is delivered to the core).
 834
 835           To solve this, interrupts are turned off before reads occur to
 836           I/O space. This option controls which the overhead/latency of
 837           controlling interrupts during this time
 838            "n" turns interrupts off every read
 839                 (higher overhead, but lower interrupt latency)
 840            "y" turns interrupts off every loop
 841                 (low overhead, but longer interrupt latency)
 842
 843           default behavior is to leave this set to on (type "Y"). If you are experiencing
 844           interrupt latency issues, it is safe and OK to turn this off.
 845
 846 endmenu
 847
 848 choice
 849         prompt "Kernel executes from"
 850         help
 851           Choose the memory type that the kernel will be running in.
 852
 853 config RAMKERNEL
 854         bool "RAM"
 855         help
 856           The kernel will be resident in RAM when running.
 857
 858 config ROMKERNEL
 859         bool "ROM"
 860         help
 861           The kernel will be resident in FLASH/ROM when running.
 862
 863 endchoice
 864
 865 source "mm/Kconfig"
 866
 867 config BFIN_GPTIMERS
 868         tristate "Enable Blackfin General Purpose Timers API"
 869         default n
 870         help
 871           Enable support for the General Purpose Timers API.  If you
 872           are unsure, say N.
 873
 874           To compile this driver as a module, choose M here: the module
 875           will be called gptimers.ko.
 876
 877 choice
 878         prompt "Uncached DMA region"
 879         default DMA_UNCACHED_1M
 880 config DMA_UNCACHED_4M
 881         bool "Enable 4M DMA region"
 882 config DMA_UNCACHED_2M
 883         bool "Enable 2M DMA region"
 884 config DMA_UNCACHED_1M
 885         bool "Enable 1M DMA region"
 886 config DMA_UNCACHED_NONE
 887         bool "Disable DMA region"
 888 endchoice
 889
 890
 891 comment "Cache Support"
 892 config BFIN_ICACHE
 893         bool "Enable ICACHE"
 894 config BFIN_DCACHE
 895         bool "Enable DCACHE"
 896 config BFIN_DCACHE_BANKA
 897         bool "Enable only 16k BankA DCACHE - BankB is SRAM"
 898         depends on BFIN_DCACHE && !BF531
 899         default n
 900 config BFIN_ICACHE_LOCK
 901         bool "Enable Instruction Cache Locking"
 902
 903 choice
 904         prompt "Policy"
 905         depends on BFIN_DCACHE
 906         default BFIN_WB if !SMP
 907         default BFIN_WT if SMP
 908 config BFIN_WB
 909         bool "Write back"
 910         depends on !SMP
 911         help
 912           Write Back Policy:
 913             Cached data will be written back to SDRAM only when needed.
 914             This can give a nice increase in performance, but beware of
 915             broken drivers that do not properly invalidate/flush their
 916             cache.
 917
 918           Write Through Policy:
 919             Cached data will always be written back to SDRAM when the
 920             cache is updated.  This is a completely safe setting, but
 921             performance is worse than Write Back.
 922
 923           If you are unsure of the options and you want to be safe,
 924           then go with Write Through.
 925
 926 config BFIN_WT
 927         bool "Write through"
 928         help
 929           Write Back Policy:
 930             Cached data will be written back to SDRAM only when needed.
 931             This can give a nice increase in performance, but beware of
 932             broken drivers that do not properly invalidate/flush their
 933             cache.
 934
 935           Write Through Policy:
 936             Cached data will always be written back to SDRAM when the
 937             cache is updated.  This is a completely safe setting, but
 938             performance is worse than Write Back.
 939
 940           If you are unsure of the options and you want to be safe,
 941           then go with Write Through.
 942
 943 endchoice
 944
 945 config BFIN_L2_CACHEABLE
 946         bool "Cache L2 SRAM"
 947         depends on (BFIN_DCACHE || BFIN_ICACHE) && (BF54x || (BF561 && !SMP))
 948         default n
 949         help
 950           Select to make L2 SRAM cacheable in L1 data and instruction cache.
 951
 952 config MPU
 953         bool "Enable the memory protection unit (EXPERIMENTAL)"
 954         default n
 955         help
 956           Use the processor's MPU to protect applications from accessing
 957           memory they do not own.  This comes at a performance penalty
 958           and is recommended only for debugging.
 959
 960 comment "Asynchonous Memory Configuration"
 961
 962 menu "EBIU_AMGCTL Global Control"
 963 config C_AMCKEN
 964         bool "Enable CLKOUT"
 965         default y
 966
 967 config C_CDPRIO
 968         bool "DMA has priority over core for ext. accesses"
 969         default n
 970
 971 config C_B0PEN
 972         depends on BF561
 973         bool "Bank 0 16 bit packing enable"
 974         default y
 975
 976 config C_B1PEN
 977         depends on BF561
 978         bool "Bank 1 16 bit packing enable"
 979         default y
 980
 981 config C_B2PEN
 982         depends on BF561
 983         bool "Bank 2 16 bit packing enable"
 984         default y
 985
 986 config C_B3PEN
 987         depends on BF561
 988         bool "Bank 3 16 bit packing enable"
 989         default n
 990
 991 choice
 992         prompt"Enable Asynchonous Memory Banks"
 993         default C_AMBEN_ALL
 994
 995 config C_AMBEN
 996         bool "Disable All Banks"
 997
 998 config C_AMBEN_B0
 999         bool "Enable Bank 0"
1000
1001 config C_AMBEN_B0_B1
1002         bool "Enable Bank 0 & 1"
1003
1004 config C_AMBEN_B0_B1_B2
1005         bool "Enable Bank 0 & 1 & 2"
1006
1007 config C_AMBEN_ALL
1008         bool "Enable All Banks"
1009 endchoice
1010 endmenu
1011
1012 menu "EBIU_AMBCTL Control"
1013 config BANK_0
1014         hex "Bank 0"
1015         default 0x7BB0
1016
1017 config BANK_1
1018         hex "Bank 1"
1019         default 0x7BB0
1020         default 0x5558 if BF54x
1021
1022 config BANK_2
1023         hex "Bank 2"
1024         default 0x7BB0
1025
1026 config BANK_3
1027         hex "Bank 3"
1028         default 0x99B3
1029 endmenu
1030
1031 config EBIU_MBSCTLVAL
1032         hex "EBIU Bank Select Control Register"
1033         depends on BF54x
1034         default 0
1035
1036 config EBIU_MODEVAL
1037         hex "Flash Memory Mode Control Register"
1038         depends on BF54x
1039         default 1
1040
1041 config EBIU_FCTLVAL
1042         hex "Flash Memory Bank Control Register"
1043         depends on BF54x
1044         default 6
1045 endmenu
1046
1047 #############################################################################
1048 menu "Bus options (PCI, PCMCIA, EISA, MCA, ISA)"
1049
1050 config PCI
1051         bool "PCI support"
1052         depends on BROKEN
1053         help
1054           Support for PCI bus.
1055
1056 source "drivers/pci/Kconfig"
1057
1058 config HOTPLUG
1059         bool "Support for hot-pluggable device"
1060           help
1061           Say Y here if you want to plug devices into your computer while
1062           the system is running, and be able to use them quickly.  In many
1063           cases, the devices can likewise be unplugged at any time too.
1064
1065           One well known example of this is PCMCIA- or PC-cards, credit-card
1066           size devices such as network cards, modems or hard drives which are
1067           plugged into slots found on all modern laptop computers.  Another
1068           example, used on modern desktops as well as laptops, is USB.
1069
1070           Enable HOTPLUG and build a modular kernel.  Get agent software
1071           (from <http://linux-hotplug.sourceforge.net/>) and install it.
1072           Then your kernel will automatically call out to a user mode "policy
1073           agent" (/sbin/hotplug) to load modules and set up software needed
1074           to use devices as you hotplug them.
1075
1076 source "drivers/pcmcia/Kconfig"
1077
1078 source "drivers/pci/hotplug/Kconfig"
1079
1080 endmenu
1081
1082 menu "Executable file formats"
1083
1084 source "fs/Kconfig.binfmt"
1085
1086 endmenu
1087
1088 menu "Power management options"
1089 source "kernel/power/Kconfig"
1090
1091 config ARCH_SUSPEND_POSSIBLE
1092         def_bool y
1093         depends on !SMP
1094
1095 choice
1096         prompt "Standby Power Saving Mode"
1097         depends on PM
1098         default PM_BFIN_SLEEP_DEEPER
1099 config  PM_BFIN_SLEEP_DEEPER
1100         bool "Sleep Deeper"
1101         help
1102           Sleep "Deeper" Mode (High Power Savings) - This mode reduces dynamic
1103           power dissipation by disabling the clock to the processor core (CCLK).
1104           Furthermore, Standby sets the internal power supply voltage (VDDINT)
1105           to 0.85 V to provide the greatest power savings, while preserving the
1106           processor state.
1107           The PLL and system clock (SCLK) continue to operate at a very low
1108           frequency of about 3.3 MHz. To preserve data integrity in the SDRAM,
1109           the SDRAM is put into Self Refresh Mode. Typically an external event
1110           such as GPIO interrupt or RTC activity wakes up the processor.
1111           Various Peripherals such as UART, SPORT, PPI may not function as
1112           normal during Sleep Deeper, due to the reduced SCLK frequency.
1113           When in the sleep mode, system DMA access to L1 memory is not supported.
1114
1115           If unsure, select "Sleep Deeper".
1116
1117 config  PM_BFIN_SLEEP
1118         bool "Sleep"
1119         help
1120           Sleep Mode (High Power Savings) - The sleep mode reduces power
1121           dissipation by disabling the clock to the processor core (CCLK).
1122           The PLL and system clock (SCLK), however, continue to operate in
1123           this mode. Typically an external event or RTC activity will wake
1124           up the processor. When in the sleep mode, system DMA access to L1
1125           memory is not supported.
1126
1127           If unsure, select "Sleep Deeper".
1128 endchoice
1129
1130 config PM_WAKEUP_BY_GPIO
1131         bool "Allow Wakeup from Standby by GPIO"
1132         depends on PM && !BF54x
1133
1134 config PM_WAKEUP_GPIO_NUMBER
1135         int "GPIO number"
1136         range 0 47
1137         depends on PM_WAKEUP_BY_GPIO
1138         default 2
1139
1140 choice
1141         prompt "GPIO Polarity"
1142         depends on PM_WAKEUP_BY_GPIO
1143         default PM_WAKEUP_GPIO_POLAR_H
1144 config  PM_WAKEUP_GPIO_POLAR_H
1145         bool "Active High"
1146 config  PM_WAKEUP_GPIO_POLAR_L
1147         bool "Active Low"
1148 config  PM_WAKEUP_GPIO_POLAR_EDGE_F
1149         bool "Falling EDGE"
1150 config  PM_WAKEUP_GPIO_POLAR_EDGE_R
1151         bool "Rising EDGE"
1152 config  PM_WAKEUP_GPIO_POLAR_EDGE_B
1153         bool "Both EDGE"
1154 endchoice
1155
1156 comment "Possible Suspend Mem / Hibernate Wake-Up Sources"
1157         depends on PM
1158
1159 config PM_BFIN_WAKE_PH6
1160         bool "Allow Wake-Up from on-chip PHY or PH6 GP"
1161         depends on PM && (BF51x || BF52x || BF534 || BF536 || BF537)
1162         default n
1163         help
1164           Enable PHY and PH6 GP Wake-Up (Voltage Regulator Power-Up)
1165
1166 config PM_BFIN_WAKE_GP
1167         bool "Allow Wake-Up from GPIOs"
1168         depends on PM && BF54x
1169         default n
1170         help
1171           Enable General-Purpose Wake-Up (Voltage Regulator Power-Up)
1172           (all processors, except ADSP-BF549). This option sets
1173           the general-purpose wake-up enable (GPWE) control bit to enable
1174           wake-up upon detection of an active low signal on the /GPW (PH7) pin.
1175           On ADSP-BF549 this option enables the the same functionality on the
1176           /MRXON pin also PH7.
1177
1178 endmenu
1179
1180 menu "CPU Frequency scaling"
1181
1182 source "drivers/cpufreq/Kconfig"
1183
1184 config BFIN_CPU_FREQ
1185         bool
1186         depends on CPU_FREQ
1187         select CPU_FREQ_TABLE
1188         default y
1189
1190 config CPU_VOLTAGE
1191         bool "CPU Voltage scaling"
1192         depends on EXPERIMENTAL
1193         depends on CPU_FREQ
1194         default n
1195         help
1196           Say Y here if you want CPU voltage scaling according to the CPU frequency.
1197           This option violates the PLL BYPASS recommendation in the Blackfin Processor
1198           manuals. There is a theoretical risk that during VDDINT transitions
1199           the PLL may unlock.
1200
1201 endmenu
1202
1203 source "net/Kconfig"
1204
1205 source "drivers/Kconfig"
1206
1207 source "fs/Kconfig"
1208
1209 source "arch/blackfin/Kconfig.debug"
1210
1211 source "security/Kconfig"
1212
1213 source "crypto/Kconfig"
1214
1215 source "lib/Kconfig"