arch/blackfin/Kconfig

   1 #
   2 # For a description of the syntax of this configuration file,
   3 # see Documentation/kbuild/kconfig-language.txt.
   4 #
   5
   6 mainmenu "Blackfin Kernel Configuration"
   7
   8 config MMU
   9         bool
  10         default n
  11
  12 config FPU
  13         bool
  14         default n
  15
  16 config RWSEM_GENERIC_SPINLOCK
  17         bool
  18         default y
  19
  20 config RWSEM_XCHGADD_ALGORITHM
  21         bool
  22         default n
  23
  24 config BLACKFIN
  25         bool
  26         default y
  27         select HAVE_IDE
  28         select HAVE_OPROFILE
  29
  30 config ZONE_DMA
  31         bool
  32         default y
  33
  34 config GENERIC_FIND_NEXT_BIT
  35         bool
  36         default y
  37
  38 config GENERIC_HWEIGHT
  39         bool
  40         default y
  41
  42 config GENERIC_HARDIRQS
  43         bool
  44         default y
  45
  46 config GENERIC_IRQ_PROBE
  47         bool
  48         default y
  49
  50 config GENERIC_TIME
  51         bool
  52         default n
  53
  54 config GENERIC_GPIO
  55         bool
  56         default y
  57
  58 config FORCE_MAX_ZONEORDER
  59         int
  60         default "14"
  61
  62 config GENERIC_CALIBRATE_DELAY
  63         bool
  64         default y
  65
  66 config HARDWARE_PM
  67         def_bool y
  68         depends on OPROFILE
  69
  70 source "init/Kconfig"
  71 source "kernel/Kconfig.preempt"
  72
  73 menu "Blackfin Processor Options"
  74
  75 comment "Processor and Board Settings"
  76
  77 choice
  78         prompt "CPU"
  79         default BF533
  80
  81 config BF522
  82         bool "BF522"
  83         help
  84           BF522 Processor Support.
  85
  86 config BF523
  87         bool "BF523"
  88         help
  89           BF523 Processor Support.
  90
  91 config BF524
  92         bool "BF524"
  93         help
  94           BF524 Processor Support.
  95
  96 config BF525
  97         bool "BF525"
  98         help
  99           BF525 Processor Support.
 100
 101 config BF526
 102         bool "BF526"
 103         help
 104           BF526 Processor Support.
 105
 106 config BF527
 107         bool "BF527"
 108         help
 109           BF527 Processor Support.
 110
 111 config BF531
 112         bool "BF531"
 113         help
 114           BF531 Processor Support.
 115
 116 config BF532
 117         bool "BF532"
 118         help
 119           BF532 Processor Support.
 120
 121 config BF533
 122         bool "BF533"
 123         help
 124           BF533 Processor Support.
 125
 126 config BF534
 127         bool "BF534"
 128         help
 129           BF534 Processor Support.
 130
 131 config BF536
 132         bool "BF536"
 133         help
 134           BF536 Processor Support.
 135
 136 config BF537
 137         bool "BF537"
 138         help
 139           BF537 Processor Support.
 140
 141 config BF542
 142         bool "BF542"
 143         help
 144           BF542 Processor Support.
 145
 146 config BF544
 147         bool "BF544"
 148         help
 149           BF544 Processor Support.
 150
 151 config BF547
 152         bool "BF547"
 153         help
 154           BF547 Processor Support.
 155
 156 config BF548
 157         bool "BF548"
 158         help
 159           BF548 Processor Support.
 160
 161 config BF549
 162         bool "BF549"
 163         help
 164           BF549 Processor Support.
 165
 166 config BF561
 167         bool "BF561"
 168         help
 169           Not Supported Yet - Work in progress - BF561 Processor Support.
 170
 171 endchoice
 172
 173 choice
 174         prompt "Silicon Rev"
 175         default BF_REV_0_1 if BF527
 176         default BF_REV_0_2 if BF537
 177         default BF_REV_0_3 if BF533
 178         default BF_REV_0_0 if BF549
 179
 180 config BF_REV_0_0
 181         bool "0.0"
 182         depends on (BF52x || BF54x)
 183
 184 config BF_REV_0_1
 185         bool "0.1"
 186         depends on (BF52x || BF54x)
 187
 188 config BF_REV_0_2
 189         bool "0.2"
 190         depends on (BF537 || BF536 || BF534)
 191
 192 config BF_REV_0_3
 193         bool "0.3"
 194         depends on (BF561 || BF537 || BF536 || BF534 || BF533 || BF532 || BF531)
 195
 196 config BF_REV_0_4
 197         bool "0.4"
 198         depends on (BF561 || BF533 || BF532 || BF531)
 199
 200 config BF_REV_0_5
 201         bool "0.5"
 202         depends on (BF561 || BF533 || BF532 || BF531)
 203
 204 config BF_REV_ANY
 205         bool "any"
 206
 207 config BF_REV_NONE
 208         bool "none"
 209
 210 endchoice
 211
 212 config BF52x
 213         bool
 214         depends on (BF522 || BF523 || BF524 || BF525 || BF526 || BF527)
 215         default y
 216
 217 config BF53x
 218         bool
 219         depends on (BF531 || BF532 || BF533 || BF534 || BF536 || BF537)
 220         default y
 221
 222 config BF54x
 223         bool
 224         depends on (BF542 || BF544 || BF547 || BF548 || BF549)
 225         default y
 226
 227 config BFIN_DUAL_CORE
 228         bool
 229         depends on (BF561)
 230         default y
 231
 232 config BFIN_SINGLE_CORE
 233         bool
 234         depends on !BFIN_DUAL_CORE
 235         default y
 236
 237 config MEM_GENERIC_BOARD
 238         bool
 239         depends on GENERIC_BOARD
 240         default y
 241
 242 config MEM_MT48LC64M4A2FB_7E
 243         bool
 244         depends on (BFIN533_STAMP)
 245         default y
 246
 247 config MEM_MT48LC16M16A2TG_75
 248         bool
 249         depends on (BFIN533_EZKIT || BFIN561_EZKIT \
 250                 || BFIN533_BLUETECHNIX_CM || BFIN537_BLUETECHNIX_CM \
 251                 || H8606_HVSISTEMAS)
 252         default y
 253
 254 config MEM_MT48LC32M8A2_75
 255         bool
 256         depends on (BFIN537_STAMP || PNAV10)
 257         default y
 258
 259 config MEM_MT48LC8M32B2B5_7
 260         bool
 261         depends on (BFIN561_BLUETECHNIX_CM)
 262         default y
 263
 264 config MEM_MT48LC32M16A2TG_75
 265         bool
 266         depends on (BFIN527_EZKIT)
 267         default y
 268
 269 source "arch/blackfin/mach-bf527/Kconfig"
 270 source "arch/blackfin/mach-bf533/Kconfig"
 271 source "arch/blackfin/mach-bf561/Kconfig"
 272 source "arch/blackfin/mach-bf537/Kconfig"
 273 source "arch/blackfin/mach-bf548/Kconfig"
 274
 275 menu "Board customizations"
 276
 277 config CMDLINE_BOOL
 278         bool "Default bootloader kernel arguments"
 279
 280 config CMDLINE
 281         string "Initial kernel command string"
 282         depends on CMDLINE_BOOL
 283         default "console=ttyBF0,57600"
 284         help
 285           If you don't have a boot loader capable of passing a command line string
 286           to the kernel, you may specify one here. As a minimum, you should specify
 287           the memory size and the root device (e.g., mem=8M, root=/dev/nfs).
 288
 289 comment "Clock/PLL Setup"
 290
 291 config CLKIN_HZ
 292         int "Crystal Frequency in Hz"
 293         default "11059200" if BFIN533_STAMP
 294         default "27000000" if BFIN533_EZKIT
 295         default "25000000" if (BFIN537_STAMP || BFIN527_EZKIT || H8606_HVSISTEMAS)
 296         default "30000000" if BFIN561_EZKIT
 297         default "24576000" if PNAV10
 298         help
 299           The frequency of CLKIN crystal oscillator on the board in Hz.
 300
 301 config BFIN_KERNEL_CLOCK
 302         bool "Re-program Clocks while Kernel boots?"
 303         default n
 304         help
 305           This option decides if kernel clocks are re-programed from the
 306           bootloader settings. If the clocks are not set, the SDRAM settings
 307           are also not changed, and the Bootloader does 100% of the hardware
 308           configuration.
 309
 310 config PLL_BYPASS
 311         bool "Bypass PLL"
 312         depends on BFIN_KERNEL_CLOCK
 313         default n
 314
 315 config CLKIN_HALF
 316         bool "Half Clock In"
 317         depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
 318         default n
 319         help
 320           If this is set the clock will be divided by 2, before it goes to the PLL.
 321
 322 config VCO_MULT
 323         int "VCO Multiplier"
 324         depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
 325         range 1 64
 326         default "22" if BFIN533_EZKIT
 327         default "45" if BFIN533_STAMP
 328         default "20" if (BFIN537_STAMP || BFIN527_EZKIT || BFIN548_EZKIT)
 329         default "22" if BFIN533_BLUETECHNIX_CM
 330         default "20" if BFIN537_BLUETECHNIX_CM
 331         default "20" if BFIN561_BLUETECHNIX_CM
 332         default "20" if BFIN561_EZKIT
 333         default "16" if H8606_HVSISTEMAS
 334         help
 335           This controls the frequency of the on-chip PLL. This can be between 1 and 64.
 336           PLL Frequency = (Crystal Frequency) * (this setting)
 337
 338 choice
 339         prompt "Core Clock Divider"
 340         depends on BFIN_KERNEL_CLOCK
 341         default CCLK_DIV_1
 342         help
 343           This sets the frequency of the core. It can be 1, 2, 4 or 8
 344           Core Frequency = (PLL frequency) / (this setting)
 345
 346 config CCLK_DIV_1
 347         bool "1"
 348
 349 config CCLK_DIV_2
 350         bool "2"
 351
 352 config CCLK_DIV_4
 353         bool "4"
 354
 355 config CCLK_DIV_8
 356         bool "8"
 357 endchoice
 358
 359 config SCLK_DIV
 360         int "System Clock Divider"
 361         depends on BFIN_KERNEL_CLOCK
 362         range 1 15
 363         default 5 if BFIN533_EZKIT
 364         default 5 if BFIN533_STAMP
 365         default 4 if (BFIN537_STAMP || BFIN527_EZKIT || BFIN548_EZKIT)
 366         default 5 if BFIN533_BLUETECHNIX_CM
 367         default 4 if BFIN537_BLUETECHNIX_CM
 368         default 4 if BFIN561_BLUETECHNIX_CM
 369         default 5 if BFIN561_EZKIT
 370         default 3 if H8606_HVSISTEMAS
 371         help
 372           This sets the frequency of the system clock (including SDRAM or DDR).
 373           This can be between 1 and 15
 374           System Clock = (PLL frequency) / (this setting)
 375
 376 #
 377 # Max & Min Speeds for various Chips
 378 #
 379 config MAX_VCO_HZ
 380         int
 381         default 600000000 if BF522
 382         default 400000000 if BF523
 383         default 400000000 if BF524
 384         default 600000000 if BF525
 385         default 400000000 if BF526
 386         default 600000000 if BF527
 387         default 400000000 if BF531
 388         default 400000000 if BF532
 389         default 750000000 if BF533
 390         default 500000000 if BF534
 391         default 400000000 if BF536
 392         default 600000000 if BF537
 393         default 533333333 if BF538
 394         default 533333333 if BF539
 395         default 600000000 if BF542
 396         default 533333333 if BF544
 397         default 600000000 if BF547
 398         default 600000000 if BF548
 399         default 533333333 if BF549
 400         default 600000000 if BF561
 401
 402 config MIN_VCO_HZ
 403         int
 404         default 50000000
 405
 406 config MAX_SCLK_HZ
 407         int
 408         default 133333333
 409
 410 config MIN_SCLK_HZ
 411         int
 412         default 27000000
 413
 414 comment "Kernel Timer/Scheduler"
 415
 416 source kernel/Kconfig.hz
 417
 418 comment "Memory Setup"
 419
 420 config MEM_SIZE
 421         int "SDRAM Memory Size in MBytes"
 422         default  32 if BFIN533_EZKIT
 423         default  64 if BFIN527_EZKIT
 424         default  64 if BFIN537_STAMP
 425         default  64 if BFIN548_EZKIT
 426         default  64 if BFIN561_EZKIT
 427         default 128 if BFIN533_STAMP
 428         default  64 if PNAV10
 429         default  32 if H8606_HVSISTEMAS
 430
 431 config MEM_ADD_WIDTH
 432         int "SDRAM Memory Address Width"
 433         depends on (!BF54x)
 434         default  9 if BFIN533_EZKIT
 435         default  9 if BFIN561_EZKIT
 436         default  9 if H8606_HVSISTEMAS
 437         default 10 if BFIN527_EZKIT
 438         default 10 if BFIN537_STAMP
 439         default 11 if BFIN533_STAMP
 440         default 10 if PNAV10
 441
 442
 443 choice
 444         prompt "DDR SDRAM Chip Type"
 445         depends on BFIN548_EZKIT
 446         default MEM_MT46V32M16_5B
 447
 448 config MEM_MT46V32M16_6T
 449         bool "MT46V32M16_6T"
 450
 451 config MEM_MT46V32M16_5B
 452         bool "MT46V32M16_5B"
 453 endchoice
 454
 455 config ENET_FLASH_PIN
 456         int "PF port/pin used for flash and ethernet sharing"
 457         depends on (BFIN533_STAMP)
 458         default  0
 459         help
 460           PF port/pin used for flash and ethernet sharing to allow other PF
 461           pins to be used on other platforms without having to touch common
 462           code.
 463           For example: PF0 --> 0,PF1 --> 1,PF2 --> 2, etc.
 464
 465 config BOOT_LOAD
 466         hex "Kernel load address for booting"
 467         default "0x1000"
 468         range 0x1000 0x20000000
 469         help
 470           This option allows you to set the load address of the kernel.
 471           This can be useful if you are on a board which has a small amount
 472           of memory or you wish to reserve some memory at the beginning of
 473           the address space.
 474
 475           Note that you need to keep this value above 4k (0x1000) as this
 476           memory region is used to capture NULL pointer references as well
 477           as some core kernel functions.
 478
 479 choice
 480         prompt "Blackfin Exception Scratch Register"
 481         default BFIN_SCRATCH_REG_RETN
 482         help
 483           Select the resource to reserve for the Exception handler:
 484             - RETN: Non-Maskable Interrupt (NMI)
 485             - RETE: Exception Return (JTAG/ICE)
 486             - CYCLES: Performance counter
 487
 488           If you are unsure, please select "RETN".
 489
 490 config BFIN_SCRATCH_REG_RETN
 491         bool "RETN"
 492         help
 493           Use the RETN register in the Blackfin exception handler
 494           as a stack scratch register.  This means you cannot
 495           safely use NMI on the Blackfin while running Linux, but
 496           you can debug the system with a JTAG ICE and use the
 497           CYCLES performance registers.
 498
 499           If you are unsure, please select "RETN".
 500
 501 config BFIN_SCRATCH_REG_RETE
 502         bool "RETE"
 503         help
 504           Use the RETE register in the Blackfin exception handler
 505           as a stack scratch register.  This means you cannot
 506           safely use a JTAG ICE while debugging a Blackfin board,
 507           but you can safely use the CYCLES performance registers
 508           and the NMI.
 509
 510           If you are unsure, please select "RETN".
 511
 512 config BFIN_SCRATCH_REG_CYCLES
 513         bool "CYCLES"
 514         help
 515           Use the CYCLES register in the Blackfin exception handler
 516           as a stack scratch register.  This means you cannot
 517           safely use the CYCLES performance registers on a Blackfin
 518           board at anytime, but you can debug the system with a JTAG
 519           ICE and use the NMI.
 520
 521           If you are unsure, please select "RETN".
 522
 523 endchoice
 524
 525 endmenu
 526
 527
 528 menu "Blackfin Kernel Optimizations"
 529
 530 comment "Memory Optimizations"
 531
 532 config I_ENTRY_L1
 533         bool "Locate interrupt entry code in L1 Memory"
 534         default y
 535         help
 536           If enabled, interrupt entry code (STORE/RESTORE CONTEXT) is linked
 537           into L1 instruction memory. (less latency)
 538
 539 config EXCPT_IRQ_SYSC_L1
 540         bool "Locate entire ASM lowlevel exception / interrupt - Syscall and CPLB handler code in L1 Memory"
 541         default y
 542         help
 543           If enabled, the entire ASM lowlevel exception and interrupt entry code
 544           (STORE/RESTORE CONTEXT) is linked into L1 instruction memory.
 545           (less latency)
 546
 547 config DO_IRQ_L1
 548         bool "Locate frequently called do_irq dispatcher function in L1 Memory"
 549         default y
 550         help
 551           If enabled, the frequently called do_irq dispatcher function is linked
 552           into L1 instruction memory. (less latency)
 553
 554 config CORE_TIMER_IRQ_L1
 555         bool "Locate frequently called timer_interrupt() function in L1 Memory"
 556         default y
 557         help
 558           If enabled, the frequently called timer_interrupt() function is linked
 559           into L1 instruction memory. (less latency)
 560
 561 config IDLE_L1
 562         bool "Locate frequently idle function in L1 Memory"
 563         default y
 564         help
 565           If enabled, the frequently called idle function is linked
 566           into L1 instruction memory. (less latency)
 567
 568 config SCHEDULE_L1
 569         bool "Locate kernel schedule function in L1 Memory"
 570         default y
 571         help
 572           If enabled, the frequently called kernel schedule is linked
 573           into L1 instruction memory. (less latency)
 574
 575 config ARITHMETIC_OPS_L1
 576         bool "Locate kernel owned arithmetic functions in L1 Memory"
 577         default y
 578         help
 579           If enabled, arithmetic functions are linked
 580           into L1 instruction memory. (less latency)
 581
 582 config ACCESS_OK_L1
 583         bool "Locate access_ok function in L1 Memory"
 584         default y
 585         help
 586           If enabled, the access_ok function is linked
 587           into L1 instruction memory. (less latency)
 588
 589 config MEMSET_L1
 590         bool "Locate memset function in L1 Memory"
 591         default y
 592         help
 593           If enabled, the memset function is linked
 594           into L1 instruction memory. (less latency)
 595
 596 config MEMCPY_L1
 597         bool "Locate memcpy function in L1 Memory"
 598         default y
 599         help
 600           If enabled, the memcpy function is linked
 601           into L1 instruction memory. (less latency)
 602
 603 config SYS_BFIN_SPINLOCK_L1
 604         bool "Locate sys_bfin_spinlock function in L1 Memory"
 605         default y
 606         help
 607           If enabled, sys_bfin_spinlock function is linked
 608           into L1 instruction memory. (less latency)
 609
 610 config IP_CHECKSUM_L1
 611         bool "Locate IP Checksum function in L1 Memory"
 612         default n
 613         help
 614           If enabled, the IP Checksum function is linked
 615           into L1 instruction memory. (less latency)
 616
 617 config CACHELINE_ALIGNED_L1
 618         bool "Locate cacheline_aligned data to L1 Data Memory"
 619         default y if !BF54x
 620         default n if BF54x
 621         depends on !BF531
 622         help
 623           If enabled, cacheline_anligned data is linked
 624           into L1 data memory. (less latency)
 625
 626 config SYSCALL_TAB_L1
 627         bool "Locate Syscall Table L1 Data Memory"
 628         default n
 629         depends on !BF531
 630         help
 631           If enabled, the Syscall LUT is linked
 632           into L1 data memory. (less latency)
 633
 634 config CPLB_SWITCH_TAB_L1
 635         bool "Locate CPLB Switch Tables L1 Data Memory"
 636         default n
 637         depends on !BF531
 638         help
 639           If enabled, the CPLB Switch Tables are linked
 640           into L1 data memory. (less latency)
 641
 642 endmenu
 643
 644
 645 choice
 646         prompt "Kernel executes from"
 647         help
 648           Choose the memory type that the kernel will be running in.
 649
 650 config RAMKERNEL
 651         bool "RAM"
 652         help
 653           The kernel will be resident in RAM when running.
 654
 655 config ROMKERNEL
 656         bool "ROM"
 657         help
 658           The kernel will be resident in FLASH/ROM when running.
 659
 660 endchoice
 661
 662 source "mm/Kconfig"
 663
 664 config LARGE_ALLOCS
 665         bool "Allow allocating large blocks (> 1MB) of memory"
 666         help
 667           Allow the slab memory allocator to keep chains for very large
 668           memory sizes - upto 32MB. You may need this if your system has
 669           a lot of RAM, and you need to able to allocate very large
 670           contiguous chunks. If unsure, say N.
 671
 672 config BFIN_GPTIMERS
 673         tristate "Enable Blackfin General Purpose Timers API"
 674         default n
 675         help
 676           Enable support for the General Purpose Timers API.  If you
 677           are unsure, say N.
 678
 679           To compile this driver as a module, choose M here: the module
 680           will be called gptimers.ko.
 681
 682 config BFIN_DMA_5XX
 683         bool "Enable DMA Support"
 684         depends on (BF52x || BF53x || BF561 || BF54x)
 685         default y
 686         help
 687           DMA driver for BF5xx.
 688
 689 choice
 690         prompt "Uncached SDRAM region"
 691         default DMA_UNCACHED_1M
 692         depends on BFIN_DMA_5XX
 693 config DMA_UNCACHED_2M
 694         bool "Enable 2M DMA region"
 695 config DMA_UNCACHED_1M
 696         bool "Enable 1M DMA region"
 697 config DMA_UNCACHED_NONE
 698         bool "Disable DMA region"
 699 endchoice
 700
 701
 702 comment "Cache Support"
 703 config BFIN_ICACHE
 704         bool "Enable ICACHE"
 705 config BFIN_DCACHE
 706         bool "Enable DCACHE"
 707 config BFIN_DCACHE_BANKA
 708         bool "Enable only 16k BankA DCACHE - BankB is SRAM"
 709         depends on BFIN_DCACHE && !BF531
 710         default n
 711 config BFIN_ICACHE_LOCK
 712         bool "Enable Instruction Cache Locking"
 713
 714 choice
 715         prompt "Policy"
 716         depends on BFIN_DCACHE
 717         default BFIN_WB
 718 config BFIN_WB
 719         bool "Write back"
 720         help
 721           Write Back Policy:
 722             Cached data will be written back to SDRAM only when needed.
 723             This can give a nice increase in performance, but beware of
 724             broken drivers that do not properly invalidate/flush their
 725             cache.
 726
 727           Write Through Policy:
 728             Cached data will always be written back to SDRAM when the
 729             cache is updated.  This is a completely safe setting, but
 730             performance is worse than Write Back.
 731
 732           If you are unsure of the options and you want to be safe,
 733           then go with Write Through.
 734
 735 config BFIN_WT
 736         bool "Write through"
 737         help
 738           Write Back Policy:
 739             Cached data will be written back to SDRAM only when needed.
 740             This can give a nice increase in performance, but beware of
 741             broken drivers that do not properly invalidate/flush their
 742             cache.
 743
 744           Write Through Policy:
 745             Cached data will always be written back to SDRAM when the
 746             cache is updated.  This is a completely safe setting, but
 747             performance is worse than Write Back.
 748
 749           If you are unsure of the options and you want to be safe,
 750           then go with Write Through.
 751
 752 endchoice
 753
 754 config L1_MAX_PIECE
 755         int "Set the max L1 SRAM pieces"
 756         default 16
 757         help
 758           Set the max memory pieces for the L1 SRAM allocation algorithm.
 759           Min value is 16. Max value is 1024.
 760
 761
 762 config MPU
 763         bool "Enable the memory protection unit (EXPERIMENTAL)"
 764         default n
 765         help
 766           Use the processor's MPU to protect applications from accessing
 767           memory they do not own.  This comes at a performance penalty
 768           and is recommended only for debugging.
 769
 770 comment "Asynchonous Memory Configuration"
 771
 772 menu "EBIU_AMGCTL Global Control"
 773 config C_AMCKEN
 774         bool "Enable CLKOUT"
 775         default y
 776
 777 config C_CDPRIO
 778         bool "DMA has priority over core for ext. accesses"
 779         default n
 780
 781 config C_B0PEN
 782         depends on BF561
 783         bool "Bank 0 16 bit packing enable"
 784         default y
 785
 786 config C_B1PEN
 787         depends on BF561
 788         bool "Bank 1 16 bit packing enable"
 789         default y
 790
 791 config C_B2PEN
 792         depends on BF561
 793         bool "Bank 2 16 bit packing enable"
 794         default y
 795
 796 config C_B3PEN
 797         depends on BF561
 798         bool "Bank 3 16 bit packing enable"
 799         default n
 800
 801 choice
 802         prompt"Enable Asynchonous Memory Banks"
 803         default C_AMBEN_ALL
 804
 805 config C_AMBEN
 806         bool "Disable All Banks"
 807
 808 config C_AMBEN_B0
 809         bool "Enable Bank 0"
 810
 811 config C_AMBEN_B0_B1
 812         bool "Enable Bank 0 & 1"
 813
 814 config C_AMBEN_B0_B1_B2
 815         bool "Enable Bank 0 & 1 & 2"
 816
 817 config C_AMBEN_ALL
 818         bool "Enable All Banks"
 819 endchoice
 820 endmenu
 821
 822 menu "EBIU_AMBCTL Control"
 823 config BANK_0
 824         hex "Bank 0"
 825         default 0x7BB0
 826
 827 config BANK_1
 828         hex "Bank 1"
 829         default 0x7BB0
 830
 831 config BANK_2
 832         hex "Bank 2"
 833         default 0x7BB0
 834
 835 config BANK_3
 836         hex "Bank 3"
 837         default 0x99B3
 838 endmenu
 839
 840 config EBIU_MBSCTLVAL
 841         hex "EBIU Bank Select Control Register"
 842         depends on BF54x
 843         default 0
 844
 845 config EBIU_MODEVAL
 846         hex "Flash Memory Mode Control Register"
 847         depends on BF54x
 848         default 1
 849
 850 config EBIU_FCTLVAL
 851         hex "Flash Memory Bank Control Register"
 852         depends on BF54x
 853         default 6
 854 endmenu
 855
 856 #############################################################################
 857 menu "Bus options (PCI, PCMCIA, EISA, MCA, ISA)"
 858
 859 config PCI
 860         bool "PCI support"
 861         help
 862           Support for PCI bus.
 863
 864 source "drivers/pci/Kconfig"
 865
 866 config HOTPLUG
 867         bool "Support for hot-pluggable device"
 868           help
 869           Say Y here if you want to plug devices into your computer while
 870           the system is running, and be able to use them quickly.  In many
 871           cases, the devices can likewise be unplugged at any time too.
 872
 873           One well known example of this is PCMCIA- or PC-cards, credit-card
 874           size devices such as network cards, modems or hard drives which are
 875           plugged into slots found on all modern laptop computers.  Another
 876           example, used on modern desktops as well as laptops, is USB.
 877
 878           Enable HOTPLUG and KMOD, and build a modular kernel.  Get agent
 879           software (at <http://linux-hotplug.sourceforge.net/>) and install it.
 880           Then your kernel will automatically call out to a user mode "policy
 881           agent" (/sbin/hotplug) to load modules and set up software needed
 882           to use devices as you hotplug them.
 883
 884 source "drivers/pcmcia/Kconfig"
 885
 886 source "drivers/pci/hotplug/Kconfig"
 887
 888 endmenu
 889
 890 menu "Executable file formats"
 891
 892 source "fs/Kconfig.binfmt"
 893
 894 endmenu
 895
 896 menu "Power management options"
 897 source "kernel/power/Kconfig"
 898
 899 config ARCH_SUSPEND_POSSIBLE
 900         def_bool y
 901         depends on !SMP
 902
 903 choice
 904         prompt "Default Power Saving Mode"
 905         depends on PM
 906         default PM_BFIN_SLEEP_DEEPER
 907 config  PM_BFIN_SLEEP_DEEPER
 908         bool "Sleep Deeper"
 909         help
 910           Sleep "Deeper" Mode (High Power Savings) - This mode reduces dynamic
 911           power dissipation by disabling the clock to the processor core (CCLK).
 912           Furthermore, Standby sets the internal power supply voltage (VDDINT)
 913           to 0.85 V to provide the greatest power savings, while preserving the
 914           processor state.
 915           The PLL and system clock (SCLK) continue to operate at a very low
 916           frequency of about 3.3 MHz. To preserve data integrity in the SDRAM,
 917           the SDRAM is put into Self Refresh Mode. Typically an external event
 918           such as GPIO interrupt or RTC activity wakes up the processor.
 919           Various Peripherals such as UART, SPORT, PPI may not function as
 920           normal during Sleep Deeper, due to the reduced SCLK frequency.
 921           When in the sleep mode, system DMA access to L1 memory is not supported.
 922
 923 config  PM_BFIN_SLEEP
 924         bool "Sleep"
 925         help
 926           Sleep Mode (High Power Savings) - The sleep mode reduces power
 927           dissipation by disabling the clock to the processor core (CCLK).
 928           The PLL and system clock (SCLK), however, continue to operate in
 929           this mode. Typically an external event or RTC activity will wake
 930           up the processor. When in the sleep mode,
 931           system DMA access to L1 memory is not supported.
 932 endchoice
 933
 934 config PM_WAKEUP_BY_GPIO
 935         bool "Cause Wakeup Event by GPIO"
 936
 937 config PM_WAKEUP_GPIO_NUMBER
 938         int "Wakeup GPIO number"
 939         range 0 47
 940         depends on PM_WAKEUP_BY_GPIO
 941         default 2 if BFIN537_STAMP
 942
 943 choice
 944         prompt "GPIO Polarity"
 945         depends on PM_WAKEUP_BY_GPIO
 946         default PM_WAKEUP_GPIO_POLAR_H
 947 config  PM_WAKEUP_GPIO_POLAR_H
 948         bool "Active High"
 949 config  PM_WAKEUP_GPIO_POLAR_L
 950         bool "Active Low"
 951 config  PM_WAKEUP_GPIO_POLAR_EDGE_F
 952         bool "Falling EDGE"
 953 config  PM_WAKEUP_GPIO_POLAR_EDGE_R
 954         bool "Rising EDGE"
 955 config  PM_WAKEUP_GPIO_POLAR_EDGE_B
 956         bool "Both EDGE"
 957 endchoice
 958
 959 endmenu
 960
 961 if (BF537 || BF533 || BF54x)
 962
 963 menu "CPU Frequency scaling"
 964
 965 source "drivers/cpufreq/Kconfig"
 966
 967 config CPU_FREQ
 968         bool
 969         default n
 970         help
 971           If you want to enable this option, you should select the
 972           DPMC driver from Character Devices.
 973 endmenu
 974
 975 endif
 976
 977 source "net/Kconfig"
 978
 979 source "drivers/Kconfig"
 980
 981 source "fs/Kconfig"
 982
 983 source "arch/blackfin/Kconfig.debug"
 984
 985 source "security/Kconfig"
 986
 987 source "crypto/Kconfig"
 988
 989 source "lib/Kconfig"