arch/blackfin/Kconfig

   1 config SYMBOL_PREFIX
   2         string
   3         default "_"
   4
   5 config MMU
   6         def_bool n
   7
   8 config FPU
   9         def_bool n
  10
  11 config RWSEM_GENERIC_SPINLOCK
  12         def_bool y
  13
  14 config RWSEM_XCHGADD_ALGORITHM
  15         def_bool n
  16
  17 config BLACKFIN
  18         def_bool y
  19         select HAVE_ARCH_KGDB
  20         select HAVE_ARCH_TRACEHOOK
  21         select HAVE_DYNAMIC_FTRACE
  22         select HAVE_FTRACE_MCOUNT_RECORD
  23         select HAVE_FUNCTION_GRAPH_TRACER
  24         select HAVE_FUNCTION_TRACER
  25         select HAVE_FUNCTION_TRACE_MCOUNT_TEST
  26         select HAVE_IDE
  27         select HAVE_IRQ_WORK
  28         select HAVE_KERNEL_GZIP if RAMKERNEL
  29         select HAVE_KERNEL_BZIP2 if RAMKERNEL
  30         select HAVE_KERNEL_LZMA if RAMKERNEL
  31         select HAVE_KERNEL_LZO if RAMKERNEL
  32         select HAVE_OPROFILE
  33         select HAVE_PERF_EVENTS
  34         select ARCH_HAVE_CUSTOM_GPIO_H
  35         select ARCH_WANT_OPTIONAL_GPIOLIB
  36         select ARCH_WANT_IPC_PARSE_VERSION
  37         select HAVE_GENERIC_HARDIRQS
  38         select GENERIC_ATOMIC64
  39         select GENERIC_IRQ_PROBE
  40         select IRQ_PER_CPU if SMP
  41         select USE_GENERIC_SMP_HELPERS if SMP
  42         select HAVE_NMI_WATCHDOG if NMI_WATCHDOG
  43         select GENERIC_SMP_IDLE_THREAD
  44         select ARCH_USES_GETTIMEOFFSET if !GENERIC_CLOCKEVENTS
  45         select HAVE_MOD_ARCH_SPECIFIC
  46         select MODULES_USE_ELF_RELA
  47
  48 config GENERIC_CSUM
  49         def_bool y
  50
  51 config GENERIC_BUG
  52         def_bool y
  53         depends on BUG
  54
  55 config ZONE_DMA
  56         def_bool y
  57
  58 config GENERIC_GPIO
  59         def_bool y
  60
  61 config FORCE_MAX_ZONEORDER
  62         int
  63         default "14"
  64
  65 config GENERIC_CALIBRATE_DELAY
  66         def_bool y
  67
  68 config LOCKDEP_SUPPORT
  69         def_bool y
  70
  71 config STACKTRACE_SUPPORT
  72         def_bool y
  73
  74 config TRACE_IRQFLAGS_SUPPORT
  75         def_bool y
  76
  77 source "init/Kconfig"
  78
  79 source "kernel/Kconfig.preempt"
  80
  81 source "kernel/Kconfig.freezer"
  82
  83 menu "Blackfin Processor Options"
  84
  85 comment "Processor and Board Settings"
  86
  87 choice
  88         prompt "CPU"
  89         default BF533
  90
  91 config BF512
  92         bool "BF512"
  93         help
  94           BF512 Processor Support.
  95
  96 config BF514
  97         bool "BF514"
  98         help
  99           BF514 Processor Support.
 100
 101 config BF516
 102         bool "BF516"
 103         help
 104           BF516 Processor Support.
 105
 106 config BF518
 107         bool "BF518"
 108         help
 109           BF518 Processor Support.
 110
 111 config BF522
 112         bool "BF522"
 113         help
 114           BF522 Processor Support.
 115
 116 config BF523
 117         bool "BF523"
 118         help
 119           BF523 Processor Support.
 120
 121 config BF524
 122         bool "BF524"
 123         help
 124           BF524 Processor Support.
 125
 126 config BF525
 127         bool "BF525"
 128         help
 129           BF525 Processor Support.
 130
 131 config BF526
 132         bool "BF526"
 133         help
 134           BF526 Processor Support.
 135
 136 config BF527
 137         bool "BF527"
 138         help
 139           BF527 Processor Support.
 140
 141 config BF531
 142         bool "BF531"
 143         help
 144           BF531 Processor Support.
 145
 146 config BF532
 147         bool "BF532"
 148         help
 149           BF532 Processor Support.
 150
 151 config BF533
 152         bool "BF533"
 153         help
 154           BF533 Processor Support.
 155
 156 config BF534
 157         bool "BF534"
 158         help
 159           BF534 Processor Support.
 160
 161 config BF536
 162         bool "BF536"
 163         help
 164           BF536 Processor Support.
 165
 166 config BF537
 167         bool "BF537"
 168         help
 169           BF537 Processor Support.
 170
 171 config BF538
 172         bool "BF538"
 173         help
 174           BF538 Processor Support.
 175
 176 config BF539
 177         bool "BF539"
 178         help
 179           BF539 Processor Support.
 180
 181 config BF542_std
 182         bool "BF542"
 183         help
 184           BF542 Processor Support.
 185
 186 config BF542M
 187         bool "BF542m"
 188         help
 189           BF542 Processor Support.
 190
 191 config BF544_std
 192         bool "BF544"
 193         help
 194           BF544 Processor Support.
 195
 196 config BF544M
 197         bool "BF544m"
 198         help
 199           BF544 Processor Support.
 200
 201 config BF547_std
 202         bool "BF547"
 203         help
 204           BF547 Processor Support.
 205
 206 config BF547M
 207         bool "BF547m"
 208         help
 209           BF547 Processor Support.
 210
 211 config BF548_std
 212         bool "BF548"
 213         help
 214           BF548 Processor Support.
 215
 216 config BF548M
 217         bool "BF548m"
 218         help
 219           BF548 Processor Support.
 220
 221 config BF549_std
 222         bool "BF549"
 223         help
 224           BF549 Processor Support.
 225
 226 config BF549M
 227         bool "BF549m"
 228         help
 229           BF549 Processor Support.
 230
 231 config BF561
 232         bool "BF561"
 233         help
 234           BF561 Processor Support.
 235
 236 config BF609
 237         bool "BF609"
 238         select CLKDEV_LOOKUP
 239         help
 240           BF609 Processor Support.
 241
 242 endchoice
 243
 244 config SMP
 245         depends on BF561
 246         select TICKSOURCE_CORETMR
 247         bool "Symmetric multi-processing support"
 248         ---help---
 249           This enables support for systems with more than one CPU,
 250           like the dual core BF561. If you have a system with only one
 251           CPU, say N. If you have a system with more than one CPU, say Y.
 252
 253           If you don't know what to do here, say N.
 254
 255 config NR_CPUS
 256         int
 257         depends on SMP
 258         default 2 if BF561
 259
 260 config HOTPLUG_CPU
 261         bool "Support for hot-pluggable CPUs"
 262         depends on SMP && HOTPLUG
 263         default y
 264
 265 config BF_REV_MIN
 266         int
 267         default 0 if (BF51x || BF52x || (BF54x && !BF54xM)) || BF60x
 268         default 2 if (BF537 || BF536 || BF534)
 269         default 3 if (BF561 || BF533 || BF532 || BF531 || BF54xM)
 270         default 4 if (BF538 || BF539)
 271
 272 config BF_REV_MAX
 273         int
 274         default 2 if (BF51x || BF52x || (BF54x && !BF54xM)) || BF60x
 275         default 3 if (BF537 || BF536 || BF534 || BF54xM)
 276         default 5 if (BF561 || BF538 || BF539)
 277         default 6 if (BF533 || BF532 || BF531)
 278
 279 choice
 280         prompt "Silicon Rev"
 281         default BF_REV_0_0 if (BF51x || BF52x || BF60x)
 282         default BF_REV_0_2 if (BF534 || BF536 || BF537 || (BF54x && !BF54xM))
 283         default BF_REV_0_3 if (BF531 || BF532 || BF533 || BF54xM || BF561)
 284
 285 config BF_REV_0_0
 286         bool "0.0"
 287         depends on (BF51x || BF52x || (BF54x && !BF54xM) || BF60x)
 288
 289 config BF_REV_0_1
 290         bool "0.1"
 291         depends on (BF51x || BF52x || (BF54x && !BF54xM))
 292
 293 config BF_REV_0_2
 294         bool "0.2"
 295         depends on (BF51x || BF52x || BF537 || BF536 || BF534 || (BF54x && !BF54xM))
 296
 297 config BF_REV_0_3
 298         bool "0.3"
 299         depends on (BF54xM || BF561 || BF537 || BF536 || BF534 || BF533 || BF532 || BF531)
 300
 301 config BF_REV_0_4
 302         bool "0.4"
 303         depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539)
 304
 305 config BF_REV_0_5
 306         bool "0.5"
 307         depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539)
 308
 309 config BF_REV_0_6
 310         bool "0.6"
 311         depends on (BF533 || BF532 || BF531)
 312
 313 config BF_REV_ANY
 314         bool "any"
 315
 316 config BF_REV_NONE
 317         bool "none"
 318
 319 endchoice
 320
 321 config BF53x
 322         bool
 323         depends on (BF531 || BF532 || BF533 || BF534 || BF536 || BF537)
 324         default y
 325
 326 config MEM_MT48LC64M4A2FB_7E
 327         bool
 328         depends on (BFIN533_STAMP)
 329         default y
 330
 331 config MEM_MT48LC16M16A2TG_75
 332         bool
 333         depends on (BFIN533_EZKIT || BFIN561_EZKIT \
 334                 || BFIN533_BLUETECHNIX_CM || BFIN537_BLUETECHNIX_CM_E \
 335                 || BFIN537_BLUETECHNIX_CM_U || H8606_HVSISTEMAS \
 336                 || BFIN527_BLUETECHNIX_CM)
 337         default y
 338
 339 config MEM_MT48LC32M8A2_75
 340         bool
 341         depends on (BFIN518F_EZBRD || BFIN537_STAMP || PNAV10 || BFIN538_EZKIT)
 342         default y
 343
 344 config MEM_MT48LC8M32B2B5_7
 345         bool
 346         depends on (BFIN561_BLUETECHNIX_CM)
 347         default y
 348
 349 config MEM_MT48LC32M16A2TG_75
 350         bool
 351         depends on (BFIN527_EZKIT || BFIN527_EZKIT_V2 || BFIN532_IP0X || BLACKSTAMP || BFIN527_AD7160EVAL)
 352         default y
 353
 354 config MEM_MT48H32M16LFCJ_75
 355         bool
 356         depends on (BFIN526_EZBRD)
 357         default y
 358
 359 config MEM_MT47H64M16
 360         bool
 361         depends on (BFIN609_EZKIT)
 362         default y
 363
 364 source "arch/blackfin/mach-bf518/Kconfig"
 365 source "arch/blackfin/mach-bf527/Kconfig"
 366 source "arch/blackfin/mach-bf533/Kconfig"
 367 source "arch/blackfin/mach-bf561/Kconfig"
 368 source "arch/blackfin/mach-bf537/Kconfig"
 369 source "arch/blackfin/mach-bf538/Kconfig"
 370 source "arch/blackfin/mach-bf548/Kconfig"
 371 source "arch/blackfin/mach-bf609/Kconfig"
 372
 373 menu "Board customizations"
 374
 375 config CMDLINE_BOOL
 376         bool "Default bootloader kernel arguments"
 377
 378 config CMDLINE
 379         string "Initial kernel command string"
 380         depends on CMDLINE_BOOL
 381         default "console=ttyBF0,57600"
 382         help
 383           If you don't have a boot loader capable of passing a command line string
 384           to the kernel, you may specify one here. As a minimum, you should specify
 385           the memory size and the root device (e.g., mem=8M, root=/dev/nfs).
 386
 387 config BOOT_LOAD
 388         hex "Kernel load address for booting"
 389         default "0x1000"
 390         range 0x1000 0x20000000
 391         help
 392           This option allows you to set the load address of the kernel.
 393           This can be useful if you are on a board which has a small amount
 394           of memory or you wish to reserve some memory at the beginning of
 395           the address space.
 396
 397           Note that you need to keep this value above 4k (0x1000) as this
 398           memory region is used to capture NULL pointer references as well
 399           as some core kernel functions.
 400
 401 config PHY_RAM_BASE_ADDRESS
 402         hex "Physical RAM Base"
 403         default 0x0
 404         help
 405           set BF609 FPGA physical SRAM base address
 406
 407 config ROM_BASE
 408         hex "Kernel ROM Base"
 409         depends on ROMKERNEL
 410         default "0x20040040"
 411         range 0x20000000 0x20400000 if !(BF54x || BF561 || BF60x)
 412         range 0x20000000 0x30000000 if (BF54x || BF561)
 413         range 0xB0000000 0xC0000000 if (BF60x)
 414         help
 415           Make sure your ROM base does not include any file-header
 416           information that is prepended to the kernel.
 417
 418           For example, the bootable U-Boot format (created with
 419           mkimage) has a 64 byte header (0x40).  So while the image
 420           you write to flash might start at say 0x20080000, you have
 421           to add 0x40 to get the kernel's ROM base as it will come
 422           after the header.
 423
 424 comment "Clock/PLL Setup"
 425
 426 config CLKIN_HZ
 427         int "Frequency of the crystal on the board in Hz"
 428         default "10000000" if BFIN532_IP0X
 429         default "11059200" if BFIN533_STAMP
 430         default "24576000" if PNAV10
 431         default "25000000" # most people use this
 432         default "27000000" if BFIN533_EZKIT
 433         default "30000000" if BFIN561_EZKIT
 434         default "24000000" if BFIN527_AD7160EVAL
 435         help
 436           The frequency of CLKIN crystal oscillator on the board in Hz.
 437           Warning: This value should match the crystal on the board. Otherwise,
 438           peripherals won't work properly.
 439
 440 config BFIN_KERNEL_CLOCK
 441         bool "Re-program Clocks while Kernel boots?"
 442         default n
 443         help
 444           This option decides if kernel clocks are re-programed from the
 445           bootloader settings. If the clocks are not set, the SDRAM settings
 446           are also not changed, and the Bootloader does 100% of the hardware
 447           configuration.
 448
 449 config PLL_BYPASS
 450         bool "Bypass PLL"
 451         depends on BFIN_KERNEL_CLOCK && (!BF60x)
 452         default n
 453
 454 config CLKIN_HALF
 455         bool "Half Clock In"
 456         depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
 457         default n
 458         help
 459           If this is set the clock will be divided by 2, before it goes to the PLL.
 460
 461 config VCO_MULT
 462         int "VCO Multiplier"
 463         depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
 464         range 1 64
 465         default "22" if BFIN533_EZKIT
 466         default "45" if BFIN533_STAMP
 467         default "20" if (BFIN537_STAMP || BFIN527_EZKIT || BFIN527_EZKIT_V2 || BFIN548_EZKIT || BFIN548_BLUETECHNIX_CM || BFIN538_EZKIT)
 468         default "22" if BFIN533_BLUETECHNIX_CM
 469         default "20" if (BFIN537_BLUETECHNIX_CM_E || BFIN537_BLUETECHNIX_CM_U || BFIN527_BLUETECHNIX_CM || BFIN561_BLUETECHNIX_CM)
 470         default "20" if (BFIN561_EZKIT || BF609)
 471         default "16" if (H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD || BFIN518F_EZBRD)
 472         default "25" if BFIN527_AD7160EVAL
 473         help
 474           This controls the frequency of the on-chip PLL. This can be between 1 and 64.
 475           PLL Frequency = (Crystal Frequency) * (this setting)
 476
 477 choice
 478         prompt "Core Clock Divider"
 479         depends on BFIN_KERNEL_CLOCK
 480         default CCLK_DIV_1
 481         help
 482           This sets the frequency of the core. It can be 1, 2, 4 or 8
 483           Core Frequency = (PLL frequency) / (this setting)
 484
 485 config CCLK_DIV_1
 486         bool "1"
 487
 488 config CCLK_DIV_2
 489         bool "2"
 490
 491 config CCLK_DIV_4
 492         bool "4"
 493
 494 config CCLK_DIV_8
 495         bool "8"
 496 endchoice
 497
 498 config SCLK_DIV
 499         int "System Clock Divider"
 500         depends on BFIN_KERNEL_CLOCK
 501         range 1 15
 502         default 4
 503         help
 504           This sets the frequency of the system clock (including SDRAM or DDR) on
 505           !BF60x else it set the clock for system buses and provides the
 506           source from which SCLK0 and SCLK1 are derived.
 507           This can be between 1 and 15
 508           System Clock = (PLL frequency) / (this setting)
 509
 510 config SCLK0_DIV
 511         int "System Clock0 Divider"
 512         depends on BFIN_KERNEL_CLOCK && BF60x
 513         range 1 15
 514         default 1
 515         help
 516           This sets the frequency of the system clock0 for PVP and all other
 517           peripherals not clocked by SCLK1.
 518           This can be between 1 and 15
 519           System Clock0 = (System Clock) / (this setting)
 520
 521 config SCLK1_DIV
 522         int "System Clock1 Divider"
 523         depends on BFIN_KERNEL_CLOCK && BF60x
 524         range 1 15
 525         default 1
 526         help
 527           This sets the frequency of the system clock1 (including SPORT, SPI and ACM).
 528           This can be between 1 and 15
 529           System Clock1 = (System Clock) / (this setting)
 530
 531 config DCLK_DIV
 532         int "DDR Clock Divider"
 533         depends on BFIN_KERNEL_CLOCK && BF60x
 534         range 1 15
 535         default 2
 536         help
 537           This sets the frequency of the DDR memory.
 538           This can be between 1 and 15
 539           DDR Clock = (PLL frequency) / (this setting)
 540
 541 choice
 542         prompt "DDR SDRAM Chip Type"
 543         depends on BFIN_KERNEL_CLOCK
 544         depends on BF54x
 545         default MEM_MT46V32M16_5B
 546
 547 config MEM_MT46V32M16_6T
 548         bool "MT46V32M16_6T"
 549
 550 config MEM_MT46V32M16_5B
 551         bool "MT46V32M16_5B"
 552 endchoice
 553
 554 choice
 555         prompt "DDR/SDRAM Timing"
 556         depends on BFIN_KERNEL_CLOCK && !BF60x
 557         default BFIN_KERNEL_CLOCK_MEMINIT_CALC
 558         help
 559           This option allows you to specify Blackfin SDRAM/DDR Timing parameters
 560           The calculated SDRAM timing parameters may not be 100%
 561           accurate - This option is therefore marked experimental.
 562
 563 config BFIN_KERNEL_CLOCK_MEMINIT_CALC
 564         bool "Calculate Timings (EXPERIMENTAL)"
 565         depends on EXPERIMENTAL
 566
 567 config BFIN_KERNEL_CLOCK_MEMINIT_SPEC
 568         bool "Provide accurate Timings based on target SCLK"
 569         help
 570           Please consult the Blackfin Hardware Reference Manuals as well
 571           as the memory device datasheet.
 572           http://docs.blackfin.uclinux.org/doku.php?id=bfin:sdram
 573 endchoice
 574
 575 menu "Memory Init Control"
 576         depends on BFIN_KERNEL_CLOCK_MEMINIT_SPEC
 577
 578 config MEM_DDRCTL0
 579         depends on BF54x
 580         hex "DDRCTL0"
 581         default 0x0
 582
 583 config MEM_DDRCTL1
 584         depends on BF54x
 585         hex "DDRCTL1"
 586         default 0x0
 587
 588 config MEM_DDRCTL2
 589         depends on BF54x
 590         hex "DDRCTL2"
 591         default 0x0
 592
 593 config MEM_EBIU_DDRQUE
 594         depends on BF54x
 595         hex "DDRQUE"
 596         default 0x0
 597
 598 config MEM_SDRRC
 599         depends on !BF54x
 600         hex "SDRRC"
 601         default 0x0
 602
 603 config MEM_SDGCTL
 604         depends on !BF54x
 605         hex "SDGCTL"
 606         default 0x0
 607 endmenu
 608
 609 #
 610 # Max & Min Speeds for various Chips
 611 #
 612 config MAX_VCO_HZ
 613         int
 614         default 400000000 if BF512
 615         default 400000000 if BF514
 616         default 400000000 if BF516
 617         default 400000000 if BF518
 618         default 400000000 if BF522
 619         default 600000000 if BF523
 620         default 400000000 if BF524
 621         default 600000000 if BF525
 622         default 400000000 if BF526
 623         default 600000000 if BF527
 624         default 400000000 if BF531
 625         default 400000000 if BF532
 626         default 750000000 if BF533
 627         default 500000000 if BF534
 628         default 400000000 if BF536
 629         default 600000000 if BF537
 630         default 533333333 if BF538
 631         default 533333333 if BF539
 632         default 600000000 if BF542
 633         default 533333333 if BF544
 634         default 600000000 if BF547
 635         default 600000000 if BF548
 636         default 533333333 if BF549
 637         default 600000000 if BF561
 638         default 800000000 if BF609
 639
 640 config MIN_VCO_HZ
 641         int
 642         default 50000000
 643
 644 config MAX_SCLK_HZ
 645         int
 646         default 200000000 if BF609
 647         default 133333333
 648
 649 config MIN_SCLK_HZ
 650         int
 651         default 27000000
 652
 653 comment "Kernel Timer/Scheduler"
 654
 655 source kernel/Kconfig.hz
 656
 657 config SET_GENERIC_CLOCKEVENTS
 658         bool "Generic clock events"
 659         default y
 660         select GENERIC_CLOCKEVENTS
 661
 662 menu "Clock event device"
 663         depends on GENERIC_CLOCKEVENTS
 664 config TICKSOURCE_GPTMR0
 665         bool "GPTimer0"
 666         depends on !SMP
 667         select BFIN_GPTIMERS
 668
 669 config TICKSOURCE_CORETMR
 670         bool "Core timer"
 671         default y
 672 endmenu
 673
 674 menu "Clock souce"
 675         depends on GENERIC_CLOCKEVENTS
 676 config CYCLES_CLOCKSOURCE
 677         bool "CYCLES"
 678         default y
 679         depends on !BFIN_SCRATCH_REG_CYCLES
 680         depends on !SMP
 681         help
 682           If you say Y here, you will enable support for using the 'cycles'
 683           registers as a clock source.  Doing so means you will be unable to
 684           safely write to the 'cycles' register during runtime.  You will
 685           still be able to read it (such as for performance monitoring), but
 686           writing the registers will most likely crash the kernel.
 687
 688 config GPTMR0_CLOCKSOURCE
 689         bool "GPTimer0"
 690         select BFIN_GPTIMERS
 691         depends on !TICKSOURCE_GPTMR0
 692 endmenu
 693
 694 comment "Misc"
 695
 696 choice
 697         prompt "Blackfin Exception Scratch Register"
 698         default BFIN_SCRATCH_REG_RETN
 699         help
 700           Select the resource to reserve for the Exception handler:
 701             - RETN: Non-Maskable Interrupt (NMI)
 702             - RETE: Exception Return (JTAG/ICE)
 703             - CYCLES: Performance counter
 704
 705           If you are unsure, please select "RETN".
 706
 707 config BFIN_SCRATCH_REG_RETN
 708         bool "RETN"
 709         help
 710           Use the RETN register in the Blackfin exception handler
 711           as a stack scratch register.  This means you cannot
 712           safely use NMI on the Blackfin while running Linux, but
 713           you can debug the system with a JTAG ICE and use the
 714           CYCLES performance registers.
 715
 716           If you are unsure, please select "RETN".
 717
 718 config BFIN_SCRATCH_REG_RETE
 719         bool "RETE"
 720         help
 721           Use the RETE register in the Blackfin exception handler
 722           as a stack scratch register.  This means you cannot
 723           safely use a JTAG ICE while debugging a Blackfin board,
 724           but you can safely use the CYCLES performance registers
 725           and the NMI.
 726
 727           If you are unsure, please select "RETN".
 728
 729 config BFIN_SCRATCH_REG_CYCLES
 730         bool "CYCLES"
 731         help
 732           Use the CYCLES register in the Blackfin exception handler
 733           as a stack scratch register.  This means you cannot
 734           safely use the CYCLES performance registers on a Blackfin
 735           board at anytime, but you can debug the system with a JTAG
 736           ICE and use the NMI.
 737
 738           If you are unsure, please select "RETN".
 739
 740 endchoice
 741
 742 endmenu
 743
 744
 745 menu "Blackfin Kernel Optimizations"
 746
 747 comment "Memory Optimizations"
 748
 749 config I_ENTRY_L1
 750         bool "Locate interrupt entry code in L1 Memory"
 751         default y
 752         depends on !SMP
 753         help
 754           If enabled, interrupt entry code (STORE/RESTORE CONTEXT) is linked
 755           into L1 instruction memory. (less latency)
 756
 757 config EXCPT_IRQ_SYSC_L1
 758         bool "Locate entire ASM lowlevel exception / interrupt - Syscall and CPLB handler code in L1 Memory"
 759         default y
 760         depends on !SMP
 761         help
 762           If enabled, the entire ASM lowlevel exception and interrupt entry code
 763           (STORE/RESTORE CONTEXT) is linked into L1 instruction memory.
 764           (less latency)
 765
 766 config DO_IRQ_L1
 767         bool "Locate frequently called do_irq dispatcher function in L1 Memory"
 768         default y
 769         depends on !SMP
 770         help
 771           If enabled, the frequently called do_irq dispatcher function is linked
 772           into L1 instruction memory. (less latency)
 773
 774 config CORE_TIMER_IRQ_L1
 775         bool "Locate frequently called timer_interrupt() function in L1 Memory"
 776         default y
 777         depends on !SMP
 778         help
 779           If enabled, the frequently called timer_interrupt() function is linked
 780           into L1 instruction memory. (less latency)
 781
 782 config IDLE_L1
 783         bool "Locate frequently idle function in L1 Memory"
 784         default y
 785         depends on !SMP
 786         help
 787           If enabled, the frequently called idle function is linked
 788           into L1 instruction memory. (less latency)
 789
 790 config SCHEDULE_L1
 791         bool "Locate kernel schedule function in L1 Memory"
 792         default y
 793         depends on !SMP
 794         help
 795           If enabled, the frequently called kernel schedule is linked
 796           into L1 instruction memory. (less latency)
 797
 798 config ARITHMETIC_OPS_L1
 799         bool "Locate kernel owned arithmetic functions in L1 Memory"
 800         default y
 801         depends on !SMP
 802         help
 803           If enabled, arithmetic functions are linked
 804           into L1 instruction memory. (less latency)
 805
 806 config ACCESS_OK_L1
 807         bool "Locate access_ok function in L1 Memory"
 808         default y
 809         depends on !SMP
 810         help
 811           If enabled, the access_ok function is linked
 812           into L1 instruction memory. (less latency)
 813
 814 config MEMSET_L1
 815         bool "Locate memset function in L1 Memory"
 816         default y
 817         depends on !SMP
 818         help
 819           If enabled, the memset function is linked
 820           into L1 instruction memory. (less latency)
 821
 822 config MEMCPY_L1
 823         bool "Locate memcpy function in L1 Memory"
 824         default y
 825         depends on !SMP
 826         help
 827           If enabled, the memcpy function is linked
 828           into L1 instruction memory. (less latency)
 829
 830 config STRCMP_L1
 831         bool "locate strcmp function in L1 Memory"
 832         default y
 833         depends on !SMP
 834         help
 835           If enabled, the strcmp function is linked
 836           into L1 instruction memory (less latency).
 837
 838 config STRNCMP_L1
 839         bool "locate strncmp function in L1 Memory"
 840         default y
 841         depends on !SMP
 842         help
 843           If enabled, the strncmp function is linked
 844           into L1 instruction memory (less latency).
 845
 846 config STRCPY_L1
 847         bool "locate strcpy function in L1 Memory"
 848         default y
 849         depends on !SMP
 850         help
 851           If enabled, the strcpy function is linked
 852           into L1 instruction memory (less latency).
 853
 854 config STRNCPY_L1
 855         bool "locate strncpy function in L1 Memory"
 856         default y
 857         depends on !SMP
 858         help
 859           If enabled, the strncpy function is linked
 860           into L1 instruction memory (less latency).
 861
 862 config SYS_BFIN_SPINLOCK_L1
 863         bool "Locate sys_bfin_spinlock function in L1 Memory"
 864         default y
 865         depends on !SMP
 866         help
 867           If enabled, sys_bfin_spinlock function is linked
 868           into L1 instruction memory. (less latency)
 869
 870 config IP_CHECKSUM_L1
 871         bool "Locate IP Checksum function in L1 Memory"
 872         default n
 873         depends on !SMP
 874         help
 875           If enabled, the IP Checksum function is linked
 876           into L1 instruction memory. (less latency)
 877
 878 config CACHELINE_ALIGNED_L1
 879         bool "Locate cacheline_aligned data to L1 Data Memory"
 880         default y if !BF54x
 881         default n if BF54x
 882         depends on !SMP && !BF531 && !CRC32
 883         help
 884           If enabled, cacheline_aligned data is linked
 885           into L1 data memory. (less latency)
 886
 887 config SYSCALL_TAB_L1
 888         bool "Locate Syscall Table L1 Data Memory"
 889         default n
 890         depends on !SMP && !BF531
 891         help
 892           If enabled, the Syscall LUT is linked
 893           into L1 data memory. (less latency)
 894
 895 config CPLB_SWITCH_TAB_L1
 896         bool "Locate CPLB Switch Tables L1 Data Memory"
 897         default n
 898         depends on !SMP && !BF531
 899         help
 900           If enabled, the CPLB Switch Tables are linked
 901           into L1 data memory. (less latency)
 902
 903 config ICACHE_FLUSH_L1
 904         bool "Locate icache flush funcs in L1 Inst Memory"
 905         default y
 906         help
 907           If enabled, the Blackfin icache flushing functions are linked
 908           into L1 instruction memory.
 909
 910           Note that this might be required to address anomalies, but
 911           these functions are pretty small, so it shouldn't be too bad.
 912           If you are using a processor affected by an anomaly, the build
 913           system will double check for you and prevent it.
 914
 915 config DCACHE_FLUSH_L1
 916         bool "Locate dcache flush funcs in L1 Inst Memory"
 917         default y
 918         depends on !SMP
 919         help
 920           If enabled, the Blackfin dcache flushing functions are linked
 921           into L1 instruction memory.
 922
 923 config APP_STACK_L1
 924         bool "Support locating application stack in L1 Scratch Memory"
 925         default y
 926         depends on !SMP
 927         help
 928           If enabled the application stack can be located in L1
 929           scratch memory (less latency).
 930
 931           Currently only works with FLAT binaries.
 932
 933 config EXCEPTION_L1_SCRATCH
 934         bool "Locate exception stack in L1 Scratch Memory"
 935         default n
 936         depends on !SMP && !APP_STACK_L1
 937         help
 938           Whenever an exception occurs, use the L1 Scratch memory for
 939           stack storage.  You cannot place the stacks of FLAT binaries
 940           in L1 when using this option.
 941
 942           If you don't use L1 Scratch, then you should say Y here.
 943
 944 comment "Speed Optimizations"
 945 config BFIN_INS_LOWOVERHEAD
 946         bool "ins[bwl] low overhead, higher interrupt latency"
 947         default y
 948         depends on !SMP
 949         help
 950           Reads on the Blackfin are speculative. In Blackfin terms, this means
 951           they can be interrupted at any time (even after they have been issued
 952           on to the external bus), and re-issued after the interrupt occurs.
 953           For memory - this is not a big deal, since memory does not change if
 954           it sees a read.
 955
 956           If a FIFO is sitting on the end of the read, it will see two reads,
 957           when the core only sees one since the FIFO receives both the read
 958           which is cancelled (and not delivered to the core) and the one which
 959           is re-issued (which is delivered to the core).
 960
 961           To solve this, interrupts are turned off before reads occur to
 962           I/O space. This option controls which the overhead/latency of
 963           controlling interrupts during this time
 964            "n" turns interrupts off every read
 965                 (higher overhead, but lower interrupt latency)
 966            "y" turns interrupts off every loop
 967                 (low overhead, but longer interrupt latency)
 968
 969           default behavior is to leave this set to on (type "Y"). If you are experiencing
 970           interrupt latency issues, it is safe and OK to turn this off.
 971
 972 endmenu
 973
 974 choice
 975         prompt "Kernel executes from"
 976         help
 977           Choose the memory type that the kernel will be running in.
 978
 979 config RAMKERNEL
 980         bool "RAM"
 981         help
 982           The kernel will be resident in RAM when running.
 983
 984 config ROMKERNEL
 985         bool "ROM"
 986         help
 987           The kernel will be resident in FLASH/ROM when running.
 988
 989 endchoice
 990
 991 # Common code uses "ROMKERNEL" or "XIP_KERNEL", so define both
 992 config XIP_KERNEL
 993         bool
 994         default y
 995         depends on ROMKERNEL
 996
 997 source "mm/Kconfig"
 998
 999 config BFIN_GPTIMERS
1000         tristate "Enable Blackfin General Purpose Timers API"
1001         default n
1002         help
1003           Enable support for the General Purpose Timers API.  If you
1004           are unsure, say N.
1005
1006           To compile this driver as a module, choose M here: the module
1007           will be called gptimers.
1008
1009 choice
1010         prompt "Uncached DMA region"
1011         default DMA_UNCACHED_1M
1012 config DMA_UNCACHED_32M
1013         bool "Enable 32M DMA region"
1014 config DMA_UNCACHED_16M
1015         bool "Enable 16M DMA region"
1016 config DMA_UNCACHED_8M
1017         bool "Enable 8M DMA region"
1018 config DMA_UNCACHED_4M
1019         bool "Enable 4M DMA region"
1020 config DMA_UNCACHED_2M
1021         bool "Enable 2M DMA region"
1022 config DMA_UNCACHED_1M
1023         bool "Enable 1M DMA region"
1024 config DMA_UNCACHED_512K
1025         bool "Enable 512K DMA region"
1026 config DMA_UNCACHED_256K
1027         bool "Enable 256K DMA region"
1028 config DMA_UNCACHED_128K
1029         bool "Enable 128K DMA region"
1030 config DMA_UNCACHED_NONE
1031         bool "Disable DMA region"
1032 endchoice
1033
1034
1035 comment "Cache Support"
1036
1037 config BFIN_ICACHE
1038         bool "Enable ICACHE"
1039         default y
1040 config BFIN_EXTMEM_ICACHEABLE
1041         bool "Enable ICACHE for external memory"
1042         depends on BFIN_ICACHE
1043         default y
1044 config BFIN_L2_ICACHEABLE
1045         bool "Enable ICACHE for L2 SRAM"
1046         depends on BFIN_ICACHE
1047         depends on (BF54x || BF561 || BF60x) && !SMP
1048         default n
1049
1050 config BFIN_DCACHE
1051         bool "Enable DCACHE"
1052         default y
1053 config BFIN_DCACHE_BANKA
1054         bool "Enable only 16k BankA DCACHE - BankB is SRAM"
1055         depends on BFIN_DCACHE && !BF531
1056         default n
1057 config BFIN_EXTMEM_DCACHEABLE
1058         bool "Enable DCACHE for external memory"
1059         depends on BFIN_DCACHE
1060         default y
1061 choice
1062         prompt "External memory DCACHE policy"
1063         depends on BFIN_EXTMEM_DCACHEABLE
1064         default BFIN_EXTMEM_WRITEBACK if !SMP
1065         default BFIN_EXTMEM_WRITETHROUGH if SMP
1066 config BFIN_EXTMEM_WRITEBACK
1067         bool "Write back"
1068         depends on !SMP
1069         help
1070           Write Back Policy:
1071             Cached data will be written back to SDRAM only when needed.
1072             This can give a nice increase in performance, but beware of
1073             broken drivers that do not properly invalidate/flush their
1074             cache.
1075
1076           Write Through Policy:
1077             Cached data will always be written back to SDRAM when the
1078             cache is updated.  This is a completely safe setting, but
1079             performance is worse than Write Back.
1080
1081           If you are unsure of the options and you want to be safe,
1082           then go with Write Through.
1083
1084 config BFIN_EXTMEM_WRITETHROUGH
1085         bool "Write through"
1086         help
1087           Write Back Policy:
1088             Cached data will be written back to SDRAM only when needed.
1089             This can give a nice increase in performance, but beware of
1090             broken drivers that do not properly invalidate/flush their
1091             cache.
1092
1093           Write Through Policy:
1094             Cached data will always be written back to SDRAM when the
1095             cache is updated.  This is a completely safe setting, but
1096             performance is worse than Write Back.
1097
1098           If you are unsure of the options and you want to be safe,
1099           then go with Write Through.
1100
1101 endchoice
1102
1103 config BFIN_L2_DCACHEABLE
1104         bool "Enable DCACHE for L2 SRAM"
1105         depends on BFIN_DCACHE
1106         depends on (BF54x || BF561 || BF60x) && !SMP
1107         default n
1108 choice
1109         prompt "L2 SRAM DCACHE policy"
1110         depends on BFIN_L2_DCACHEABLE
1111         default BFIN_L2_WRITEBACK
1112 config BFIN_L2_WRITEBACK
1113         bool "Write back"
1114
1115 config BFIN_L2_WRITETHROUGH
1116         bool "Write through"
1117 endchoice
1118
1119
1120 comment "Memory Protection Unit"
1121 config MPU
1122         bool "Enable the memory protection unit (EXPERIMENTAL)"
1123         default n
1124         help
1125           Use the processor's MPU to protect applications from accessing
1126           memory they do not own.  This comes at a performance penalty
1127           and is recommended only for debugging.
1128
1129 comment "Asynchronous Memory Configuration"
1130
1131 menu "EBIU_AMGCTL Global Control"
1132         depends on !BF60x
1133 config C_AMCKEN
1134         bool "Enable CLKOUT"
1135         default y
1136
1137 config C_CDPRIO
1138         bool "DMA has priority over core for ext. accesses"
1139         default n
1140
1141 config C_B0PEN
1142         depends on BF561
1143         bool "Bank 0 16 bit packing enable"
1144         default y
1145
1146 config C_B1PEN
1147         depends on BF561
1148         bool "Bank 1 16 bit packing enable"
1149         default y
1150
1151 config C_B2PEN
1152         depends on BF561
1153         bool "Bank 2 16 bit packing enable"
1154         default y
1155
1156 config C_B3PEN
1157         depends on BF561
1158         bool "Bank 3 16 bit packing enable"
1159         default n
1160
1161 choice
1162         prompt "Enable Asynchronous Memory Banks"
1163         default C_AMBEN_ALL
1164
1165 config C_AMBEN
1166         bool "Disable All Banks"
1167
1168 config C_AMBEN_B0
1169         bool "Enable Bank 0"
1170
1171 config C_AMBEN_B0_B1
1172         bool "Enable Bank 0 & 1"
1173
1174 config C_AMBEN_B0_B1_B2
1175         bool "Enable Bank 0 & 1 & 2"
1176
1177 config C_AMBEN_ALL
1178         bool "Enable All Banks"
1179 endchoice
1180 endmenu
1181
1182 menu "EBIU_AMBCTL Control"
1183         depends on !BF60x
1184 config BANK_0
1185         hex "Bank 0 (AMBCTL0.L)"
1186         default 0x7BB0
1187         help
1188           These are the low 16 bits of the EBIU_AMBCTL0 MMR which are
1189           used to control the Asynchronous Memory Bank 0 settings.
1190
1191 config BANK_1
1192         hex "Bank 1 (AMBCTL0.H)"
1193         default 0x7BB0
1194         default 0x5558 if BF54x
1195         help
1196           These are the high 16 bits of the EBIU_AMBCTL0 MMR which are
1197           used to control the Asynchronous Memory Bank 1 settings.
1198
1199 config BANK_2
1200         hex "Bank 2 (AMBCTL1.L)"
1201         default 0x7BB0
1202         help
1203           These are the low 16 bits of the EBIU_AMBCTL1 MMR which are
1204           used to control the Asynchronous Memory Bank 2 settings.
1205
1206 config BANK_3
1207         hex "Bank 3 (AMBCTL1.H)"
1208         default 0x99B3
1209         help
1210           These are the high 16 bits of the EBIU_AMBCTL1 MMR which are
1211           used to control the Asynchronous Memory Bank 3 settings.
1212
1213 endmenu
1214
1215 config EBIU_MBSCTLVAL
1216         hex "EBIU Bank Select Control Register"
1217         depends on BF54x
1218         default 0
1219
1220 config EBIU_MODEVAL
1221         hex "Flash Memory Mode Control Register"
1222         depends on BF54x
1223         default 1
1224
1225 config EBIU_FCTLVAL
1226         hex "Flash Memory Bank Control Register"
1227         depends on BF54x
1228         default 6
1229 endmenu
1230
1231 #############################################################################
1232 menu "Bus options (PCI, PCMCIA, EISA, MCA, ISA)"
1233
1234 config PCI
1235         bool "PCI support"
1236         depends on BROKEN
1237         help
1238           Support for PCI bus.
1239
1240 source "drivers/pci/Kconfig"
1241
1242 source "drivers/pcmcia/Kconfig"
1243
1244 source "drivers/pci/hotplug/Kconfig"
1245
1246 endmenu
1247
1248 menu "Executable file formats"
1249
1250 source "fs/Kconfig.binfmt"
1251
1252 endmenu
1253
1254 menu "Power management options"
1255
1256 source "kernel/power/Kconfig"
1257
1258 config ARCH_SUSPEND_POSSIBLE
1259         def_bool y
1260
1261 choice
1262         prompt "Standby Power Saving Mode"
1263         depends on PM && !BF60x
1264         default PM_BFIN_SLEEP_DEEPER
1265 config  PM_BFIN_SLEEP_DEEPER
1266         bool "Sleep Deeper"
1267         help
1268           Sleep "Deeper" Mode (High Power Savings) - This mode reduces dynamic
1269           power dissipation by disabling the clock to the processor core (CCLK).
1270           Furthermore, Standby sets the internal power supply voltage (VDDINT)
1271           to 0.85 V to provide the greatest power savings, while preserving the
1272           processor state.
1273           The PLL and system clock (SCLK) continue to operate at a very low
1274           frequency of about 3.3 MHz. To preserve data integrity in the SDRAM,
1275           the SDRAM is put into Self Refresh Mode. Typically an external event
1276           such as GPIO interrupt or RTC activity wakes up the processor.
1277           Various Peripherals such as UART, SPORT, PPI may not function as
1278           normal during Sleep Deeper, due to the reduced SCLK frequency.
1279           When in the sleep mode, system DMA access to L1 memory is not supported.
1280
1281           If unsure, select "Sleep Deeper".
1282
1283 config  PM_BFIN_SLEEP
1284         bool "Sleep"
1285         help
1286           Sleep Mode (High Power Savings) - The sleep mode reduces power
1287           dissipation by disabling the clock to the processor core (CCLK).
1288           The PLL and system clock (SCLK), however, continue to operate in
1289           this mode. Typically an external event or RTC activity will wake
1290           up the processor. When in the sleep mode, system DMA access to L1
1291           memory is not supported.
1292
1293           If unsure, select "Sleep Deeper".
1294 endchoice
1295
1296 comment "Possible Suspend Mem / Hibernate Wake-Up Sources"
1297         depends on PM
1298
1299 config PM_BFIN_WAKE_PH6
1300         bool "Allow Wake-Up from on-chip PHY or PH6 GP"
1301         depends on PM && (BF51x || BF52x || BF534 || BF536 || BF537)
1302         default n
1303         help
1304           Enable PHY and PH6 GP Wake-Up (Voltage Regulator Power-Up)
1305
1306 config PM_BFIN_WAKE_GP
1307         bool "Allow Wake-Up from GPIOs"
1308         depends on PM && BF54x
1309         default n
1310         help
1311           Enable General-Purpose Wake-Up (Voltage Regulator Power-Up)
1312           (all processors, except ADSP-BF549). This option sets
1313           the general-purpose wake-up enable (GPWE) control bit to enable
1314           wake-up upon detection of an active low signal on the /GPW (PH7) pin.
1315           On ADSP-BF549 this option enables the same functionality on the
1316           /MRXON pin also PH7.
1317
1318 config PM_BFIN_WAKE_PA15
1319         bool "Allow Wake-Up from PA15"
1320         depends on PM && BF60x
1321         default n
1322         help
1323           Enable PA15 Wake-Up
1324
1325 config PM_BFIN_WAKE_PA15_POL
1326         int "Wake-up priority"
1327         depends on PM_BFIN_WAKE_PA15
1328         default 0
1329         help
1330           Wake-Up priority 0(low) 1(high)
1331
1332 config PM_BFIN_WAKE_PB15
1333         bool "Allow Wake-Up from PB15"
1334         depends on PM && BF60x
1335         default n
1336         help
1337           Enable PB15 Wake-Up
1338
1339 config PM_BFIN_WAKE_PB15_POL
1340         int "Wake-up priority"
1341         depends on PM_BFIN_WAKE_PB15
1342         default 0
1343         help
1344           Wake-Up priority 0(low) 1(high)
1345
1346 config PM_BFIN_WAKE_PC15
1347         bool "Allow Wake-Up from PC15"
1348         depends on PM && BF60x
1349         default n
1350         help
1351           Enable PC15 Wake-Up
1352
1353 config PM_BFIN_WAKE_PC15_POL
1354         int "Wake-up priority"
1355         depends on PM_BFIN_WAKE_PC15
1356         default 0
1357         help
1358           Wake-Up priority 0(low) 1(high)
1359
1360 config PM_BFIN_WAKE_PD06
1361         bool "Allow Wake-Up from PD06(ETH0_PHYINT)"
1362         depends on PM && BF60x
1363         default n
1364         help
1365           Enable PD06(ETH0_PHYINT) Wake-up
1366
1367 config PM_BFIN_WAKE_PD06_POL
1368         int "Wake-up priority"
1369         depends on PM_BFIN_WAKE_PD06
1370         default 0
1371         help
1372           Wake-Up priority 0(low) 1(high)
1373
1374 config PM_BFIN_WAKE_PE12
1375         bool "Allow Wake-Up from PE12(ETH1_PHYINT, PUSH BUTTON)"
1376         depends on PM && BF60x
1377         default n
1378         help
1379           Enable PE12(ETH1_PHYINT, PUSH BUTTON) Wake-up
1380
1381 config PM_BFIN_WAKE_PE12_POL
1382         int "Wake-up priority"
1383         depends on PM_BFIN_WAKE_PE12
1384         default 0
1385         help
1386           Wake-Up priority 0(low) 1(high)
1387
1388 config PM_BFIN_WAKE_PG04
1389         bool "Allow Wake-Up from PG04(CAN0_RX)"
1390         depends on PM && BF60x
1391         default n
1392         help
1393           Enable PG04(CAN0_RX) Wake-up
1394
1395 config PM_BFIN_WAKE_PG04_POL
1396         int "Wake-up priority"
1397         depends on PM_BFIN_WAKE_PG04
1398         default 0
1399         help
1400           Wake-Up priority 0(low) 1(high)
1401
1402 config PM_BFIN_WAKE_PG13
1403         bool "Allow Wake-Up from PG13"
1404         depends on PM && BF60x
1405         default n
1406         help
1407           Enable PG13 Wake-Up
1408
1409 config PM_BFIN_WAKE_PG13_POL
1410         int "Wake-up priority"
1411         depends on PM_BFIN_WAKE_PG13
1412         default 0
1413         help
1414           Wake-Up priority 0(low) 1(high)
1415
1416 config PM_BFIN_WAKE_USB
1417         bool "Allow Wake-Up from (USB)"
1418         depends on PM && BF60x
1419         default n
1420         help
1421           Enable (USB) Wake-up
1422
1423 config PM_BFIN_WAKE_USB_POL
1424         int "Wake-up priority"
1425         depends on PM_BFIN_WAKE_USB
1426         default 0
1427         help
1428           Wake-Up priority 0(low) 1(high)
1429
1430 endmenu
1431
1432 menu "CPU Frequency scaling"
1433
1434 source "drivers/cpufreq/Kconfig"
1435
1436 config BFIN_CPU_FREQ
1437         bool
1438         depends on CPU_FREQ
1439         select CPU_FREQ_TABLE
1440         default y
1441
1442 config CPU_VOLTAGE
1443         bool "CPU Voltage scaling"
1444         depends on EXPERIMENTAL
1445         depends on CPU_FREQ
1446         default n
1447         help
1448           Say Y here if you want CPU voltage scaling according to the CPU frequency.
1449           This option violates the PLL BYPASS recommendation in the Blackfin Processor
1450           manuals. There is a theoretical risk that during VDDINT transitions
1451           the PLL may unlock.
1452
1453 endmenu
1454
1455 source "net/Kconfig"
1456
1457 source "drivers/Kconfig"
1458
1459 source "drivers/firmware/Kconfig"
1460
1461 source "fs/Kconfig"
1462
1463 source "arch/blackfin/Kconfig.debug"
1464
1465 source "security/Kconfig"
1466
1467 source "crypto/Kconfig"
1468
1469 source "lib/Kconfig"