arch/blackfin/Kconfig

   1 #
   2 # For a description of the syntax of this configuration file,
   3 # see Documentation/kbuild/kconfig-language.txt.
   4 #
   5
   6 mainmenu "Blackfin Kernel Configuration"
   7
   8 config MMU
   9         def_bool n
  10
  11 config FPU
  12         def_bool n
  13
  14 config RWSEM_GENERIC_SPINLOCK
  15         def_bool y
  16
  17 config RWSEM_XCHGADD_ALGORITHM
  18         def_bool n
  19
  20 config BLACKFIN
  21         def_bool y
  22         select HAVE_FUNCTION_GRAPH_TRACER
  23         select HAVE_FUNCTION_TRACER
  24         select HAVE_IDE
  25         select HAVE_KERNEL_GZIP
  26         select HAVE_KERNEL_BZIP2
  27         select HAVE_KERNEL_LZMA
  28         select HAVE_OPROFILE
  29         select ARCH_WANT_OPTIONAL_GPIOLIB
  30
  31 config GENERIC_BUG
  32         def_bool y
  33         depends on BUG
  34
  35 config ZONE_DMA
  36         def_bool y
  37
  38 config GENERIC_FIND_NEXT_BIT
  39         def_bool y
  40
  41 config GENERIC_HWEIGHT
  42         def_bool y
  43
  44 config GENERIC_HARDIRQS
  45         def_bool y
  46
  47 config GENERIC_IRQ_PROBE
  48         def_bool y
  49
  50 config GENERIC_GPIO
  51         def_bool y
  52
  53 config FORCE_MAX_ZONEORDER
  54         int
  55         default "14"
  56
  57 config GENERIC_CALIBRATE_DELAY
  58         def_bool y
  59
  60 config LOCKDEP_SUPPORT
  61         def_bool y
  62
  63 config STACKTRACE_SUPPORT
  64         def_bool y
  65
  66 config TRACE_IRQFLAGS_SUPPORT
  67         def_bool y
  68
  69 source "init/Kconfig"
  70
  71 source "kernel/Kconfig.preempt"
  72
  73 source "kernel/Kconfig.freezer"
  74
  75 menu "Blackfin Processor Options"
  76
  77 comment "Processor and Board Settings"
  78
  79 choice
  80         prompt "CPU"
  81         default BF533
  82
  83 config BF512
  84         bool "BF512"
  85         help
  86           BF512 Processor Support.
  87
  88 config BF514
  89         bool "BF514"
  90         help
  91           BF514 Processor Support.
  92
  93 config BF516
  94         bool "BF516"
  95         help
  96           BF516 Processor Support.
  97
  98 config BF518
  99         bool "BF518"
 100         help
 101           BF518 Processor Support.
 102
 103 config BF522
 104         bool "BF522"
 105         help
 106           BF522 Processor Support.
 107
 108 config BF523
 109         bool "BF523"
 110         help
 111           BF523 Processor Support.
 112
 113 config BF524
 114         bool "BF524"
 115         help
 116           BF524 Processor Support.
 117
 118 config BF525
 119         bool "BF525"
 120         help
 121           BF525 Processor Support.
 122
 123 config BF526
 124         bool "BF526"
 125         help
 126           BF526 Processor Support.
 127
 128 config BF527
 129         bool "BF527"
 130         help
 131           BF527 Processor Support.
 132
 133 config BF531
 134         bool "BF531"
 135         help
 136           BF531 Processor Support.
 137
 138 config BF532
 139         bool "BF532"
 140         help
 141           BF532 Processor Support.
 142
 143 config BF533
 144         bool "BF533"
 145         help
 146           BF533 Processor Support.
 147
 148 config BF534
 149         bool "BF534"
 150         help
 151           BF534 Processor Support.
 152
 153 config BF536
 154         bool "BF536"
 155         help
 156           BF536 Processor Support.
 157
 158 config BF537
 159         bool "BF537"
 160         help
 161           BF537 Processor Support.
 162
 163 config BF538
 164         bool "BF538"
 165         help
 166           BF538 Processor Support.
 167
 168 config BF539
 169         bool "BF539"
 170         help
 171           BF539 Processor Support.
 172
 173 config BF542
 174         bool "BF542"
 175         help
 176           BF542 Processor Support.
 177
 178 config BF542M
 179         bool "BF542m"
 180         help
 181           BF542 Processor Support.
 182
 183 config BF544
 184         bool "BF544"
 185         help
 186           BF544 Processor Support.
 187
 188 config BF544M
 189         bool "BF544m"
 190         help
 191           BF544 Processor Support.
 192
 193 config BF547
 194         bool "BF547"
 195         help
 196           BF547 Processor Support.
 197
 198 config BF547M
 199         bool "BF547m"
 200         help
 201           BF547 Processor Support.
 202
 203 config BF548
 204         bool "BF548"
 205         help
 206           BF548 Processor Support.
 207
 208 config BF548M
 209         bool "BF548m"
 210         help
 211           BF548 Processor Support.
 212
 213 config BF549
 214         bool "BF549"
 215         help
 216           BF549 Processor Support.
 217
 218 config BF549M
 219         bool "BF549m"
 220         help
 221           BF549 Processor Support.
 222
 223 config BF561
 224         bool "BF561"
 225         help
 226           BF561 Processor Support.
 227
 228 endchoice
 229
 230 config SMP
 231         depends on BF561
 232         select GENERIC_TIME
 233         bool "Symmetric multi-processing support"
 234         ---help---
 235           This enables support for systems with more than one CPU,
 236           like the dual core BF561. If you have a system with only one
 237           CPU, say N. If you have a system with more than one CPU, say Y.
 238
 239           If you don't know what to do here, say N.
 240
 241 config NR_CPUS
 242         int
 243         depends on SMP
 244         default 2 if BF561
 245
 246 config IRQ_PER_CPU
 247         bool
 248         depends on SMP
 249         default y
 250
 251 config BF_REV_MIN
 252         int
 253         default 0 if (BF51x || BF52x || (BF54x && !BF54xM))
 254         default 2 if (BF537 || BF536 || BF534)
 255         default 3 if (BF561 || BF533 || BF532 || BF531 || BF54xM)
 256         default 4 if (BF538 || BF539)
 257
 258 config BF_REV_MAX
 259         int
 260         default 2 if (BF51x || BF52x || (BF54x && !BF54xM))
 261         default 3 if (BF537 || BF536 || BF534 || BF54xM)
 262         default 5 if (BF561 || BF538 || BF539)
 263         default 6 if (BF533 || BF532 || BF531)
 264
 265 choice
 266         prompt "Silicon Rev"
 267         default BF_REV_0_0 if (BF51x || BF52x)
 268         default BF_REV_0_2 if (BF534 || BF536 || BF537 || (BF54x && !BF54xM))
 269         default BF_REV_0_3 if (BF531 || BF532 || BF533 || BF54xM || BF561)
 270
 271 config BF_REV_0_0
 272         bool "0.0"
 273         depends on (BF51x || BF52x || (BF54x && !BF54xM))
 274
 275 config BF_REV_0_1
 276         bool "0.1"
 277         depends on (BF52x || (BF54x && !BF54xM))
 278
 279 config BF_REV_0_2
 280         bool "0.2"
 281         depends on (BF52x || BF537 || BF536 || BF534 || (BF54x && !BF54xM))
 282
 283 config BF_REV_0_3
 284         bool "0.3"
 285         depends on (BF54xM || BF561 || BF537 || BF536 || BF534 || BF533 || BF532 || BF531)
 286
 287 config BF_REV_0_4
 288         bool "0.4"
 289         depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539)
 290
 291 config BF_REV_0_5
 292         bool "0.5"
 293         depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539)
 294
 295 config BF_REV_0_6
 296         bool "0.6"
 297         depends on (BF533 || BF532 || BF531)
 298
 299 config BF_REV_ANY
 300         bool "any"
 301
 302 config BF_REV_NONE
 303         bool "none"
 304
 305 endchoice
 306
 307 config BF51x
 308         bool
 309         depends on (BF512 || BF514 || BF516 || BF518)
 310         default y
 311
 312 config BF52x
 313         bool
 314         depends on (BF522 || BF523 || BF524 || BF525 || BF526 || BF527)
 315         default y
 316
 317 config BF53x
 318         bool
 319         depends on (BF531 || BF532 || BF533 || BF534 || BF536 || BF537)
 320         default y
 321
 322 config BF54xM
 323         bool
 324         depends on (BF542M || BF544M || BF547M || BF548M || BF549M)
 325         default y
 326
 327 config BF54x
 328         bool
 329         depends on (BF542 || BF544 || BF547 || BF548 || BF549 || BF54xM)
 330         default y
 331
 332 config MEM_GENERIC_BOARD
 333         bool
 334         depends on GENERIC_BOARD
 335         default y
 336
 337 config MEM_MT48LC64M4A2FB_7E
 338         bool
 339         depends on (BFIN533_STAMP)
 340         default y
 341
 342 config MEM_MT48LC16M16A2TG_75
 343         bool
 344         depends on (BFIN533_EZKIT || BFIN561_EZKIT \
 345                 || BFIN533_BLUETECHNIX_CM || BFIN537_BLUETECHNIX_CM \
 346                 || H8606_HVSISTEMAS || BFIN527_BLUETECHNIX_CM)
 347         default y
 348
 349 config MEM_MT48LC32M8A2_75
 350         bool
 351         depends on (BFIN537_STAMP || PNAV10 || BFIN538_EZKIT)
 352         default y
 353
 354 config MEM_MT48LC8M32B2B5_7
 355         bool
 356         depends on (BFIN561_BLUETECHNIX_CM)
 357         default y
 358
 359 config MEM_MT48LC32M16A2TG_75
 360         bool
 361         depends on (BFIN527_EZKIT || BFIN532_IP0X || BLACKSTAMP || BFIN526_EZBRD)
 362         default y
 363
 364 config MEM_MT48LC32M8A2_75
 365         bool
 366         depends on (BFIN518F_EZBRD)
 367         default y
 368
 369 source "arch/blackfin/mach-bf518/Kconfig"
 370 source "arch/blackfin/mach-bf527/Kconfig"
 371 source "arch/blackfin/mach-bf533/Kconfig"
 372 source "arch/blackfin/mach-bf561/Kconfig"
 373 source "arch/blackfin/mach-bf537/Kconfig"
 374 source "arch/blackfin/mach-bf538/Kconfig"
 375 source "arch/blackfin/mach-bf548/Kconfig"
 376
 377 menu "Board customizations"
 378
 379 config CMDLINE_BOOL
 380         bool "Default bootloader kernel arguments"
 381
 382 config CMDLINE
 383         string "Initial kernel command string"
 384         depends on CMDLINE_BOOL
 385         default "console=ttyBF0,57600"
 386         help
 387           If you don't have a boot loader capable of passing a command line string
 388           to the kernel, you may specify one here. As a minimum, you should specify
 389           the memory size and the root device (e.g., mem=8M, root=/dev/nfs).
 390
 391 config BOOT_LOAD
 392         hex "Kernel load address for booting"
 393         default "0x1000"
 394         range 0x1000 0x20000000
 395         help
 396           This option allows you to set the load address of the kernel.
 397           This can be useful if you are on a board which has a small amount
 398           of memory or you wish to reserve some memory at the beginning of
 399           the address space.
 400
 401           Note that you need to keep this value above 4k (0x1000) as this
 402           memory region is used to capture NULL pointer references as well
 403           as some core kernel functions.
 404
 405 config ROM_BASE
 406         hex "Kernel ROM Base"
 407         depends on ROMKERNEL
 408         default "0x20040000"
 409         range 0x20000000 0x20400000 if !(BF54x || BF561)
 410         range 0x20000000 0x30000000 if (BF54x || BF561)
 411         help
 412
 413 comment "Clock/PLL Setup"
 414
 415 config CLKIN_HZ
 416         int "Frequency of the crystal on the board in Hz"
 417         default "10000000" if BFIN532_IP0X
 418         default "11059200" if BFIN533_STAMP
 419         default "24576000" if PNAV10
 420         default "25000000" # most people use this
 421         default "27000000" if BFIN533_EZKIT
 422         default "30000000" if BFIN561_EZKIT
 423         help
 424           The frequency of CLKIN crystal oscillator on the board in Hz.
 425           Warning: This value should match the crystal on the board. Otherwise,
 426           peripherals won't work properly.
 427
 428 config BFIN_KERNEL_CLOCK
 429         bool "Re-program Clocks while Kernel boots?"
 430         default n
 431         help
 432           This option decides if kernel clocks are re-programed from the
 433           bootloader settings. If the clocks are not set, the SDRAM settings
 434           are also not changed, and the Bootloader does 100% of the hardware
 435           configuration.
 436
 437 config PLL_BYPASS
 438         bool "Bypass PLL"
 439         depends on BFIN_KERNEL_CLOCK
 440         default n
 441
 442 config CLKIN_HALF
 443         bool "Half Clock In"
 444         depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
 445         default n
 446         help
 447           If this is set the clock will be divided by 2, before it goes to the PLL.
 448
 449 config VCO_MULT
 450         int "VCO Multiplier"
 451         depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
 452         range 1 64
 453         default "22" if BFIN533_EZKIT
 454         default "45" if BFIN533_STAMP
 455         default "20" if (BFIN537_STAMP || BFIN527_EZKIT || BFIN548_EZKIT || BFIN548_BLUETECHNIX_CM || BFIN538_EZKIT)
 456         default "22" if BFIN533_BLUETECHNIX_CM
 457         default "20" if (BFIN537_BLUETECHNIX_CM || BFIN527_BLUETECHNIX_CM || BFIN561_BLUETECHNIX_CM)
 458         default "20" if BFIN561_EZKIT
 459         default "16" if (H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD || BFIN518F_EZBRD)
 460         help
 461           This controls the frequency of the on-chip PLL. This can be between 1 and 64.
 462           PLL Frequency = (Crystal Frequency) * (this setting)
 463
 464 choice
 465         prompt "Core Clock Divider"
 466         depends on BFIN_KERNEL_CLOCK
 467         default CCLK_DIV_1
 468         help
 469           This sets the frequency of the core. It can be 1, 2, 4 or 8
 470           Core Frequency = (PLL frequency) / (this setting)
 471
 472 config CCLK_DIV_1
 473         bool "1"
 474
 475 config CCLK_DIV_2
 476         bool "2"
 477
 478 config CCLK_DIV_4
 479         bool "4"
 480
 481 config CCLK_DIV_8
 482         bool "8"
 483 endchoice
 484
 485 config SCLK_DIV
 486         int "System Clock Divider"
 487         depends on BFIN_KERNEL_CLOCK
 488         range 1 15
 489         default 5
 490         help
 491           This sets the frequency of the system clock (including SDRAM or DDR).
 492           This can be between 1 and 15
 493           System Clock = (PLL frequency) / (this setting)
 494
 495 choice
 496         prompt "DDR SDRAM Chip Type"
 497         depends on BFIN_KERNEL_CLOCK
 498         depends on BF54x
 499         default MEM_MT46V32M16_5B
 500
 501 config MEM_MT46V32M16_6T
 502         bool "MT46V32M16_6T"
 503
 504 config MEM_MT46V32M16_5B
 505         bool "MT46V32M16_5B"
 506 endchoice
 507
 508 choice
 509         prompt "DDR/SDRAM Timing"
 510         depends on BFIN_KERNEL_CLOCK
 511         default BFIN_KERNEL_CLOCK_MEMINIT_CALC
 512         help
 513           This option allows you to specify Blackfin SDRAM/DDR Timing parameters
 514           The calculated SDRAM timing parameters may not be 100%
 515           accurate - This option is therefore marked experimental.
 516
 517 config BFIN_KERNEL_CLOCK_MEMINIT_CALC
 518         bool "Calculate Timings (EXPERIMENTAL)"
 519         depends on EXPERIMENTAL
 520
 521 config BFIN_KERNEL_CLOCK_MEMINIT_SPEC
 522         bool "Provide accurate Timings based on target SCLK"
 523         help
 524           Please consult the Blackfin Hardware Reference Manuals as well
 525           as the memory device datasheet.
 526           http://docs.blackfin.uclinux.org/doku.php?id=bfin:sdram
 527 endchoice
 528
 529 menu "Memory Init Control"
 530         depends on BFIN_KERNEL_CLOCK_MEMINIT_SPEC
 531
 532 config MEM_DDRCTL0
 533         depends on BF54x
 534         hex "DDRCTL0"
 535         default 0x0
 536
 537 config MEM_DDRCTL1
 538         depends on BF54x
 539         hex "DDRCTL1"
 540         default 0x0
 541
 542 config MEM_DDRCTL2
 543         depends on BF54x
 544         hex "DDRCTL2"
 545         default 0x0
 546
 547 config MEM_EBIU_DDRQUE
 548         depends on BF54x
 549         hex "DDRQUE"
 550         default 0x0
 551
 552 config MEM_SDRRC
 553         depends on !BF54x
 554         hex "SDRRC"
 555         default 0x0
 556
 557 config MEM_SDGCTL
 558         depends on !BF54x
 559         hex "SDGCTL"
 560         default 0x0
 561 endmenu
 562
 563 #
 564 # Max & Min Speeds for various Chips
 565 #
 566 config MAX_VCO_HZ
 567         int
 568         default 400000000 if BF512
 569         default 400000000 if BF514
 570         default 400000000 if BF516
 571         default 400000000 if BF518
 572         default 600000000 if BF522
 573         default 400000000 if BF523
 574         default 400000000 if BF524
 575         default 600000000 if BF525
 576         default 400000000 if BF526
 577         default 600000000 if BF527
 578         default 400000000 if BF531
 579         default 400000000 if BF532
 580         default 750000000 if BF533
 581         default 500000000 if BF534
 582         default 400000000 if BF536
 583         default 600000000 if BF537
 584         default 533333333 if BF538
 585         default 533333333 if BF539
 586         default 600000000 if BF542
 587         default 533333333 if BF544
 588         default 600000000 if BF547
 589         default 600000000 if BF548
 590         default 533333333 if BF549
 591         default 600000000 if BF561
 592
 593 config MIN_VCO_HZ
 594         int
 595         default 50000000
 596
 597 config MAX_SCLK_HZ
 598         int
 599         default 133333333
 600
 601 config MIN_SCLK_HZ
 602         int
 603         default 27000000
 604
 605 comment "Kernel Timer/Scheduler"
 606
 607 source kernel/Kconfig.hz
 608
 609 config GENERIC_TIME
 610         bool "Generic time"
 611         default y
 612
 613 config GENERIC_CLOCKEVENTS
 614         bool "Generic clock events"
 615         depends on GENERIC_TIME
 616         default y
 617
 618 choice
 619         prompt "Kernel Tick Source"
 620         depends on GENERIC_CLOCKEVENTS
 621         default TICKSOURCE_CORETMR
 622
 623 config TICKSOURCE_GPTMR0
 624         bool "Gptimer0 (SCLK domain)"
 625         select BFIN_GPTIMERS
 626         depends on !IPIPE
 627
 628 config TICKSOURCE_CORETMR
 629         bool "Core timer (CCLK domain)"
 630
 631 endchoice
 632
 633 config CYCLES_CLOCKSOURCE
 634         bool "Use 'CYCLES' as a clocksource"
 635         depends on GENERIC_CLOCKEVENTS
 636         depends on !BFIN_SCRATCH_REG_CYCLES
 637         depends on !SMP
 638         help
 639           If you say Y here, you will enable support for using the 'cycles'
 640           registers as a clock source.  Doing so means you will be unable to
 641           safely write to the 'cycles' register during runtime.  You will
 642           still be able to read it (such as for performance monitoring), but
 643           writing the registers will most likely crash the kernel.
 644
 645 config GPTMR0_CLOCKSOURCE
 646         bool "Use GPTimer0 as a clocksource (higher rating)"
 647         depends on GENERIC_CLOCKEVENTS
 648         depends on !TICKSOURCE_GPTMR0
 649
 650 source kernel/time/Kconfig
 651
 652 comment "Misc"
 653
 654 choice
 655         prompt "Blackfin Exception Scratch Register"
 656         default BFIN_SCRATCH_REG_RETN
 657         help
 658           Select the resource to reserve for the Exception handler:
 659             - RETN: Non-Maskable Interrupt (NMI)
 660             - RETE: Exception Return (JTAG/ICE)
 661             - CYCLES: Performance counter
 662
 663           If you are unsure, please select "RETN".
 664
 665 config BFIN_SCRATCH_REG_RETN
 666         bool "RETN"
 667         help
 668           Use the RETN register in the Blackfin exception handler
 669           as a stack scratch register.  This means you cannot
 670           safely use NMI on the Blackfin while running Linux, but
 671           you can debug the system with a JTAG ICE and use the
 672           CYCLES performance registers.
 673
 674           If you are unsure, please select "RETN".
 675
 676 config BFIN_SCRATCH_REG_RETE
 677         bool "RETE"
 678         help
 679           Use the RETE register in the Blackfin exception handler
 680           as a stack scratch register.  This means you cannot
 681           safely use a JTAG ICE while debugging a Blackfin board,
 682           but you can safely use the CYCLES performance registers
 683           and the NMI.
 684
 685           If you are unsure, please select "RETN".
 686
 687 config BFIN_SCRATCH_REG_CYCLES
 688         bool "CYCLES"
 689         help
 690           Use the CYCLES register in the Blackfin exception handler
 691           as a stack scratch register.  This means you cannot
 692           safely use the CYCLES performance registers on a Blackfin
 693           board at anytime, but you can debug the system with a JTAG
 694           ICE and use the NMI.
 695
 696           If you are unsure, please select "RETN".
 697
 698 endchoice
 699
 700 endmenu
 701
 702
 703 menu "Blackfin Kernel Optimizations"
 704         depends on !SMP
 705
 706 comment "Memory Optimizations"
 707
 708 config I_ENTRY_L1
 709         bool "Locate interrupt entry code in L1 Memory"
 710         default y
 711         help
 712           If enabled, interrupt entry code (STORE/RESTORE CONTEXT) is linked
 713           into L1 instruction memory. (less latency)
 714
 715 config EXCPT_IRQ_SYSC_L1
 716         bool "Locate entire ASM lowlevel exception / interrupt - Syscall and CPLB handler code in L1 Memory"
 717         default y
 718         help
 719           If enabled, the entire ASM lowlevel exception and interrupt entry code
 720           (STORE/RESTORE CONTEXT) is linked into L1 instruction memory.
 721           (less latency)
 722
 723 config DO_IRQ_L1
 724         bool "Locate frequently called do_irq dispatcher function in L1 Memory"
 725         default y
 726         help
 727           If enabled, the frequently called do_irq dispatcher function is linked
 728           into L1 instruction memory. (less latency)
 729
 730 config CORE_TIMER_IRQ_L1
 731         bool "Locate frequently called timer_interrupt() function in L1 Memory"
 732         default y
 733         help
 734           If enabled, the frequently called timer_interrupt() function is linked
 735           into L1 instruction memory. (less latency)
 736
 737 config IDLE_L1
 738         bool "Locate frequently idle function in L1 Memory"
 739         default y
 740         help
 741           If enabled, the frequently called idle function is linked
 742           into L1 instruction memory. (less latency)
 743
 744 config SCHEDULE_L1
 745         bool "Locate kernel schedule function in L1 Memory"
 746         default y
 747         help
 748           If enabled, the frequently called kernel schedule is linked
 749           into L1 instruction memory. (less latency)
 750
 751 config ARITHMETIC_OPS_L1
 752         bool "Locate kernel owned arithmetic functions in L1 Memory"
 753         default y
 754         help
 755           If enabled, arithmetic functions are linked
 756           into L1 instruction memory. (less latency)
 757
 758 config ACCESS_OK_L1
 759         bool "Locate access_ok function in L1 Memory"
 760         default y
 761         help
 762           If enabled, the access_ok function is linked
 763           into L1 instruction memory. (less latency)
 764
 765 config MEMSET_L1
 766         bool "Locate memset function in L1 Memory"
 767         default y
 768         help
 769           If enabled, the memset function is linked
 770           into L1 instruction memory. (less latency)
 771
 772 config MEMCPY_L1
 773         bool "Locate memcpy function in L1 Memory"
 774         default y
 775         help
 776           If enabled, the memcpy function is linked
 777           into L1 instruction memory. (less latency)
 778
 779 config SYS_BFIN_SPINLOCK_L1
 780         bool "Locate sys_bfin_spinlock function in L1 Memory"
 781         default y
 782         help
 783           If enabled, sys_bfin_spinlock function is linked
 784           into L1 instruction memory. (less latency)
 785
 786 config IP_CHECKSUM_L1
 787         bool "Locate IP Checksum function in L1 Memory"
 788         default n
 789         help
 790           If enabled, the IP Checksum function is linked
 791           into L1 instruction memory. (less latency)
 792
 793 config CACHELINE_ALIGNED_L1
 794         bool "Locate cacheline_aligned data to L1 Data Memory"
 795         default y if !BF54x
 796         default n if BF54x
 797         depends on !BF531
 798         help
 799           If enabled, cacheline_aligned data is linked
 800           into L1 data memory. (less latency)
 801
 802 config SYSCALL_TAB_L1
 803         bool "Locate Syscall Table L1 Data Memory"
 804         default n
 805         depends on !BF531
 806         help
 807           If enabled, the Syscall LUT is linked
 808           into L1 data memory. (less latency)
 809
 810 config CPLB_SWITCH_TAB_L1
 811         bool "Locate CPLB Switch Tables L1 Data Memory"
 812         default n
 813         depends on !BF531
 814         help
 815           If enabled, the CPLB Switch Tables are linked
 816           into L1 data memory. (less latency)
 817
 818 config APP_STACK_L1
 819         bool "Support locating application stack in L1 Scratch Memory"
 820         default y
 821         help
 822           If enabled the application stack can be located in L1
 823           scratch memory (less latency).
 824
 825           Currently only works with FLAT binaries.
 826
 827 config EXCEPTION_L1_SCRATCH
 828         bool "Locate exception stack in L1 Scratch Memory"
 829         default n
 830         depends on !APP_STACK_L1
 831         help
 832           Whenever an exception occurs, use the L1 Scratch memory for
 833           stack storage.  You cannot place the stacks of FLAT binaries
 834           in L1 when using this option.
 835
 836           If you don't use L1 Scratch, then you should say Y here.
 837
 838 comment "Speed Optimizations"
 839 config BFIN_INS_LOWOVERHEAD
 840         bool "ins[bwl] low overhead, higher interrupt latency"
 841         default y
 842         help
 843           Reads on the Blackfin are speculative. In Blackfin terms, this means
 844           they can be interrupted at any time (even after they have been issued
 845           on to the external bus), and re-issued after the interrupt occurs.
 846           For memory - this is not a big deal, since memory does not change if
 847           it sees a read.
 848
 849           If a FIFO is sitting on the end of the read, it will see two reads,
 850           when the core only sees one since the FIFO receives both the read
 851           which is cancelled (and not delivered to the core) and the one which
 852           is re-issued (which is delivered to the core).
 853
 854           To solve this, interrupts are turned off before reads occur to
 855           I/O space. This option controls which the overhead/latency of
 856           controlling interrupts during this time
 857            "n" turns interrupts off every read
 858                 (higher overhead, but lower interrupt latency)
 859            "y" turns interrupts off every loop
 860                 (low overhead, but longer interrupt latency)
 861
 862           default behavior is to leave this set to on (type "Y"). If you are experiencing
 863           interrupt latency issues, it is safe and OK to turn this off.
 864
 865 endmenu
 866
 867 choice
 868         prompt "Kernel executes from"
 869         help
 870           Choose the memory type that the kernel will be running in.
 871
 872 config RAMKERNEL
 873         bool "RAM"
 874         help
 875           The kernel will be resident in RAM when running.
 876
 877 config ROMKERNEL
 878         bool "ROM"
 879         help
 880           The kernel will be resident in FLASH/ROM when running.
 881
 882 endchoice
 883
 884 source "mm/Kconfig"
 885
 886 config BFIN_GPTIMERS
 887         tristate "Enable Blackfin General Purpose Timers API"
 888         default n
 889         help
 890           Enable support for the General Purpose Timers API.  If you
 891           are unsure, say N.
 892
 893           To compile this driver as a module, choose M here: the module
 894           will be called gptimers.
 895
 896 choice
 897         prompt "Uncached DMA region"
 898         default DMA_UNCACHED_1M
 899 config DMA_UNCACHED_4M
 900         bool "Enable 4M DMA region"
 901 config DMA_UNCACHED_2M
 902         bool "Enable 2M DMA region"
 903 config DMA_UNCACHED_1M
 904         bool "Enable 1M DMA region"
 905 config DMA_UNCACHED_NONE
 906         bool "Disable DMA region"
 907 endchoice
 908
 909
 910 comment "Cache Support"
 911 config BFIN_ICACHE
 912         bool "Enable ICACHE"
 913 config BFIN_DCACHE
 914         bool "Enable DCACHE"
 915 config BFIN_DCACHE_BANKA
 916         bool "Enable only 16k BankA DCACHE - BankB is SRAM"
 917         depends on BFIN_DCACHE && !BF531
 918         default n
 919 config BFIN_ICACHE_LOCK
 920         bool "Enable Instruction Cache Locking"
 921
 922 choice
 923         prompt "External memory cache policy"
 924         depends on BFIN_DCACHE
 925         default BFIN_WB if !SMP
 926         default BFIN_WT if SMP
 927 config BFIN_WB
 928         bool "Write back"
 929         depends on !SMP
 930         help
 931           Write Back Policy:
 932             Cached data will be written back to SDRAM only when needed.
 933             This can give a nice increase in performance, but beware of
 934             broken drivers that do not properly invalidate/flush their
 935             cache.
 936
 937           Write Through Policy:
 938             Cached data will always be written back to SDRAM when the
 939             cache is updated.  This is a completely safe setting, but
 940             performance is worse than Write Back.
 941
 942           If you are unsure of the options and you want to be safe,
 943           then go with Write Through.
 944
 945 config BFIN_WT
 946         bool "Write through"
 947         help
 948           Write Back Policy:
 949             Cached data will be written back to SDRAM only when needed.
 950             This can give a nice increase in performance, but beware of
 951             broken drivers that do not properly invalidate/flush their
 952             cache.
 953
 954           Write Through Policy:
 955             Cached data will always be written back to SDRAM when the
 956             cache is updated.  This is a completely safe setting, but
 957             performance is worse than Write Back.
 958
 959           If you are unsure of the options and you want to be safe,
 960           then go with Write Through.
 961
 962 endchoice
 963
 964 choice
 965         prompt "L2 SRAM cache policy"
 966         depends on (BF54x || BF561)
 967         default BFIN_L2_WT
 968 config BFIN_L2_WB
 969         bool "Write back"
 970         depends on !SMP
 971
 972 config BFIN_L2_WT
 973         bool "Write through"
 974         depends on !SMP
 975
 976 config BFIN_L2_NOT_CACHED
 977         bool "Not cached"
 978
 979 endchoice
 980
 981 config MPU
 982         bool "Enable the memory protection unit (EXPERIMENTAL)"
 983         default n
 984         help
 985           Use the processor's MPU to protect applications from accessing
 986           memory they do not own.  This comes at a performance penalty
 987           and is recommended only for debugging.
 988
 989 comment "Asynchronous Memory Configuration"
 990
 991 menu "EBIU_AMGCTL Global Control"
 992 config C_AMCKEN
 993         bool "Enable CLKOUT"
 994         default y
 995
 996 config C_CDPRIO
 997         bool "DMA has priority over core for ext. accesses"
 998         default n
 999
1000 config C_B0PEN
1001         depends on BF561
1002         bool "Bank 0 16 bit packing enable"
1003         default y
1004
1005 config C_B1PEN
1006         depends on BF561
1007         bool "Bank 1 16 bit packing enable"
1008         default y
1009
1010 config C_B2PEN
1011         depends on BF561
1012         bool "Bank 2 16 bit packing enable"
1013         default y
1014
1015 config C_B3PEN
1016         depends on BF561
1017         bool "Bank 3 16 bit packing enable"
1018         default n
1019
1020 choice
1021         prompt "Enable Asynchronous Memory Banks"
1022         default C_AMBEN_ALL
1023
1024 config C_AMBEN
1025         bool "Disable All Banks"
1026
1027 config C_AMBEN_B0
1028         bool "Enable Bank 0"
1029
1030 config C_AMBEN_B0_B1
1031         bool "Enable Bank 0 & 1"
1032
1033 config C_AMBEN_B0_B1_B2
1034         bool "Enable Bank 0 & 1 & 2"
1035
1036 config C_AMBEN_ALL
1037         bool "Enable All Banks"
1038 endchoice
1039 endmenu
1040
1041 menu "EBIU_AMBCTL Control"
1042 config BANK_0
1043         hex "Bank 0 (AMBCTL0.L)"
1044         default 0x7BB0
1045         help
1046           These are the low 16 bits of the EBIU_AMBCTL0 MMR which are
1047           used to control the Asynchronous Memory Bank 0 settings.
1048
1049 config BANK_1
1050         hex "Bank 1 (AMBCTL0.H)"
1051         default 0x7BB0
1052         default 0x5558 if BF54x
1053         help
1054           These are the high 16 bits of the EBIU_AMBCTL0 MMR which are
1055           used to control the Asynchronous Memory Bank 1 settings.
1056
1057 config BANK_2
1058         hex "Bank 2 (AMBCTL1.L)"
1059         default 0x7BB0
1060         help
1061           These are the low 16 bits of the EBIU_AMBCTL1 MMR which are
1062           used to control the Asynchronous Memory Bank 2 settings.
1063
1064 config BANK_3
1065         hex "Bank 3 (AMBCTL1.H)"
1066         default 0x99B3
1067         help
1068           These are the high 16 bits of the EBIU_AMBCTL1 MMR which are
1069           used to control the Asynchronous Memory Bank 3 settings.
1070
1071 endmenu
1072
1073 config EBIU_MBSCTLVAL
1074         hex "EBIU Bank Select Control Register"
1075         depends on BF54x
1076         default 0
1077
1078 config EBIU_MODEVAL
1079         hex "Flash Memory Mode Control Register"
1080         depends on BF54x
1081         default 1
1082
1083 config EBIU_FCTLVAL
1084         hex "Flash Memory Bank Control Register"
1085         depends on BF54x
1086         default 6
1087 endmenu
1088
1089 #############################################################################
1090 menu "Bus options (PCI, PCMCIA, EISA, MCA, ISA)"
1091
1092 config PCI
1093         bool "PCI support"
1094         depends on BROKEN
1095         help
1096           Support for PCI bus.
1097
1098 source "drivers/pci/Kconfig"
1099
1100 config HOTPLUG
1101         bool "Support for hot-pluggable device"
1102           help
1103           Say Y here if you want to plug devices into your computer while
1104           the system is running, and be able to use them quickly.  In many
1105           cases, the devices can likewise be unplugged at any time too.
1106
1107           One well known example of this is PCMCIA- or PC-cards, credit-card
1108           size devices such as network cards, modems or hard drives which are
1109           plugged into slots found on all modern laptop computers.  Another
1110           example, used on modern desktops as well as laptops, is USB.
1111
1112           Enable HOTPLUG and build a modular kernel.  Get agent software
1113           (from <http://linux-hotplug.sourceforge.net/>) and install it.
1114           Then your kernel will automatically call out to a user mode "policy
1115           agent" (/sbin/hotplug) to load modules and set up software needed
1116           to use devices as you hotplug them.
1117
1118 source "drivers/pcmcia/Kconfig"
1119
1120 source "drivers/pci/hotplug/Kconfig"
1121
1122 endmenu
1123
1124 menu "Executable file formats"
1125
1126 source "fs/Kconfig.binfmt"
1127
1128 endmenu
1129
1130 menu "Power management options"
1131 source "kernel/power/Kconfig"
1132
1133 config ARCH_SUSPEND_POSSIBLE
1134         def_bool y
1135         depends on !SMP
1136
1137 choice
1138         prompt "Standby Power Saving Mode"
1139         depends on PM
1140         default PM_BFIN_SLEEP_DEEPER
1141 config  PM_BFIN_SLEEP_DEEPER
1142         bool "Sleep Deeper"
1143         help
1144           Sleep "Deeper" Mode (High Power Savings) - This mode reduces dynamic
1145           power dissipation by disabling the clock to the processor core (CCLK).
1146           Furthermore, Standby sets the internal power supply voltage (VDDINT)
1147           to 0.85 V to provide the greatest power savings, while preserving the
1148           processor state.
1149           The PLL and system clock (SCLK) continue to operate at a very low
1150           frequency of about 3.3 MHz. To preserve data integrity in the SDRAM,
1151           the SDRAM is put into Self Refresh Mode. Typically an external event
1152           such as GPIO interrupt or RTC activity wakes up the processor.
1153           Various Peripherals such as UART, SPORT, PPI may not function as
1154           normal during Sleep Deeper, due to the reduced SCLK frequency.
1155           When in the sleep mode, system DMA access to L1 memory is not supported.
1156
1157           If unsure, select "Sleep Deeper".
1158
1159 config  PM_BFIN_SLEEP
1160         bool "Sleep"
1161         help
1162           Sleep Mode (High Power Savings) - The sleep mode reduces power
1163           dissipation by disabling the clock to the processor core (CCLK).
1164           The PLL and system clock (SCLK), however, continue to operate in
1165           this mode. Typically an external event or RTC activity will wake
1166           up the processor. When in the sleep mode, system DMA access to L1
1167           memory is not supported.
1168
1169           If unsure, select "Sleep Deeper".
1170 endchoice
1171
1172 config PM_WAKEUP_BY_GPIO
1173         bool "Allow Wakeup from Standby by GPIO"
1174         depends on PM && !BF54x
1175
1176 config PM_WAKEUP_GPIO_NUMBER
1177         int "GPIO number"
1178         range 0 47
1179         depends on PM_WAKEUP_BY_GPIO
1180         default 2
1181
1182 choice
1183         prompt "GPIO Polarity"
1184         depends on PM_WAKEUP_BY_GPIO
1185         default PM_WAKEUP_GPIO_POLAR_H
1186 config  PM_WAKEUP_GPIO_POLAR_H
1187         bool "Active High"
1188 config  PM_WAKEUP_GPIO_POLAR_L
1189         bool "Active Low"
1190 config  PM_WAKEUP_GPIO_POLAR_EDGE_F
1191         bool "Falling EDGE"
1192 config  PM_WAKEUP_GPIO_POLAR_EDGE_R
1193         bool "Rising EDGE"
1194 config  PM_WAKEUP_GPIO_POLAR_EDGE_B
1195         bool "Both EDGE"
1196 endchoice
1197
1198 comment "Possible Suspend Mem / Hibernate Wake-Up Sources"
1199         depends on PM
1200
1201 config PM_BFIN_WAKE_PH6
1202         bool "Allow Wake-Up from on-chip PHY or PH6 GP"
1203         depends on PM && (BF51x || BF52x || BF534 || BF536 || BF537)
1204         default n
1205         help
1206           Enable PHY and PH6 GP Wake-Up (Voltage Regulator Power-Up)
1207
1208 config PM_BFIN_WAKE_GP
1209         bool "Allow Wake-Up from GPIOs"
1210         depends on PM && BF54x
1211         default n
1212         help
1213           Enable General-Purpose Wake-Up (Voltage Regulator Power-Up)
1214           (all processors, except ADSP-BF549). This option sets
1215           the general-purpose wake-up enable (GPWE) control bit to enable
1216           wake-up upon detection of an active low signal on the /GPW (PH7) pin.
1217           On ADSP-BF549 this option enables the the same functionality on the
1218           /MRXON pin also PH7.
1219
1220 endmenu
1221
1222 menu "CPU Frequency scaling"
1223
1224 source "drivers/cpufreq/Kconfig"
1225
1226 config BFIN_CPU_FREQ
1227         bool
1228         depends on CPU_FREQ
1229         select CPU_FREQ_TABLE
1230         default y
1231
1232 config CPU_VOLTAGE
1233         bool "CPU Voltage scaling"
1234         depends on EXPERIMENTAL
1235         depends on CPU_FREQ
1236         default n
1237         help
1238           Say Y here if you want CPU voltage scaling according to the CPU frequency.
1239           This option violates the PLL BYPASS recommendation in the Blackfin Processor
1240           manuals. There is a theoretical risk that during VDDINT transitions
1241           the PLL may unlock.
1242
1243 endmenu
1244
1245 source "net/Kconfig"
1246
1247 source "drivers/Kconfig"
1248
1249 source "fs/Kconfig"
1250
1251 source "arch/blackfin/Kconfig.debug"
1252
1253 source "security/Kconfig"
1254
1255 source "crypto/Kconfig"
1256
1257 source "lib/Kconfig"