arch/blackfin/Kconfig

   1 #
   2 # For a description of the syntax of this configuration file,
   3 # see Documentation/kbuild/kconfig-language.txt.
   4 #
   5
   6 mainmenu "Blackfin Kernel Configuration"
   7
   8 config MMU
   9         def_bool n
  10
  11 config FPU
  12         def_bool n
  13
  14 config RWSEM_GENERIC_SPINLOCK
  15         def_bool y
  16
  17 config RWSEM_XCHGADD_ALGORITHM
  18         def_bool n
  19
  20 config BLACKFIN
  21         def_bool y
  22         select HAVE_FUNCTION_GRAPH_TRACER
  23         select HAVE_FUNCTION_TRACER
  24         select HAVE_IDE
  25         select HAVE_KERNEL_GZIP
  26         select HAVE_KERNEL_BZIP2
  27         select HAVE_KERNEL_LZMA
  28         select HAVE_OPROFILE
  29         select ARCH_WANT_OPTIONAL_GPIOLIB
  30
  31 config GENERIC_BUG
  32         def_bool y
  33         depends on BUG
  34
  35 config ZONE_DMA
  36         def_bool y
  37
  38 config GENERIC_FIND_NEXT_BIT
  39         def_bool y
  40
  41 config GENERIC_HWEIGHT
  42         def_bool y
  43
  44 config GENERIC_HARDIRQS
  45         def_bool y
  46
  47 config GENERIC_IRQ_PROBE
  48         def_bool y
  49
  50 config GENERIC_GPIO
  51         def_bool y
  52
  53 config FORCE_MAX_ZONEORDER
  54         int
  55         default "14"
  56
  57 config GENERIC_CALIBRATE_DELAY
  58         def_bool y
  59
  60 config LOCKDEP_SUPPORT
  61         def_bool y
  62
  63 config STACKTRACE_SUPPORT
  64         def_bool y
  65
  66 config TRACE_IRQFLAGS_SUPPORT
  67         def_bool y
  68
  69 source "init/Kconfig"
  70
  71 source "kernel/Kconfig.preempt"
  72
  73 source "kernel/Kconfig.freezer"
  74
  75 menu "Blackfin Processor Options"
  76
  77 comment "Processor and Board Settings"
  78
  79 choice
  80         prompt "CPU"
  81         default BF533
  82
  83 config BF512
  84         bool "BF512"
  85         help
  86           BF512 Processor Support.
  87
  88 config BF514
  89         bool "BF514"
  90         help
  91           BF514 Processor Support.
  92
  93 config BF516
  94         bool "BF516"
  95         help
  96           BF516 Processor Support.
  97
  98 config BF518
  99         bool "BF518"
 100         help
 101           BF518 Processor Support.
 102
 103 config BF522
 104         bool "BF522"
 105         help
 106           BF522 Processor Support.
 107
 108 config BF523
 109         bool "BF523"
 110         help
 111           BF523 Processor Support.
 112
 113 config BF524
 114         bool "BF524"
 115         help
 116           BF524 Processor Support.
 117
 118 config BF525
 119         bool "BF525"
 120         help
 121           BF525 Processor Support.
 122
 123 config BF526
 124         bool "BF526"
 125         help
 126           BF526 Processor Support.
 127
 128 config BF527
 129         bool "BF527"
 130         help
 131           BF527 Processor Support.
 132
 133 config BF531
 134         bool "BF531"
 135         help
 136           BF531 Processor Support.
 137
 138 config BF532
 139         bool "BF532"
 140         help
 141           BF532 Processor Support.
 142
 143 config BF533
 144         bool "BF533"
 145         help
 146           BF533 Processor Support.
 147
 148 config BF534
 149         bool "BF534"
 150         help
 151           BF534 Processor Support.
 152
 153 config BF536
 154         bool "BF536"
 155         help
 156           BF536 Processor Support.
 157
 158 config BF537
 159         bool "BF537"
 160         help
 161           BF537 Processor Support.
 162
 163 config BF538
 164         bool "BF538"
 165         help
 166           BF538 Processor Support.
 167
 168 config BF539
 169         bool "BF539"
 170         help
 171           BF539 Processor Support.
 172
 173 config BF542
 174         bool "BF542"
 175         help
 176           BF542 Processor Support.
 177
 178 config BF542M
 179         bool "BF542m"
 180         help
 181           BF542 Processor Support.
 182
 183 config BF544
 184         bool "BF544"
 185         help
 186           BF544 Processor Support.
 187
 188 config BF544M
 189         bool "BF544m"
 190         help
 191           BF544 Processor Support.
 192
 193 config BF547
 194         bool "BF547"
 195         help
 196           BF547 Processor Support.
 197
 198 config BF547M
 199         bool "BF547m"
 200         help
 201           BF547 Processor Support.
 202
 203 config BF548
 204         bool "BF548"
 205         help
 206           BF548 Processor Support.
 207
 208 config BF548M
 209         bool "BF548m"
 210         help
 211           BF548 Processor Support.
 212
 213 config BF549
 214         bool "BF549"
 215         help
 216           BF549 Processor Support.
 217
 218 config BF549M
 219         bool "BF549m"
 220         help
 221           BF549 Processor Support.
 222
 223 config BF561
 224         bool "BF561"
 225         help
 226           BF561 Processor Support.
 227
 228 endchoice
 229
 230 config SMP
 231         depends on BF561
 232         select GENERIC_TIME
 233         bool "Symmetric multi-processing support"
 234         ---help---
 235           This enables support for systems with more than one CPU,
 236           like the dual core BF561. If you have a system with only one
 237           CPU, say N. If you have a system with more than one CPU, say Y.
 238
 239           If you don't know what to do here, say N.
 240
 241 config NR_CPUS
 242         int
 243         depends on SMP
 244         default 2 if BF561
 245
 246 config IRQ_PER_CPU
 247         bool
 248         depends on SMP
 249         default y
 250
 251 config BF_REV_MIN
 252         int
 253         default 0 if (BF51x || BF52x || (BF54x && !BF54xM))
 254         default 2 if (BF537 || BF536 || BF534)
 255         default 3 if (BF561 || BF533 || BF532 || BF531 || BF54xM)
 256         default 4 if (BF538 || BF539)
 257
 258 config BF_REV_MAX
 259         int
 260         default 2 if (BF51x || BF52x || (BF54x && !BF54xM))
 261         default 3 if (BF537 || BF536 || BF534 || BF54xM)
 262         default 5 if (BF561 || BF538 || BF539)
 263         default 6 if (BF533 || BF532 || BF531)
 264
 265 choice
 266         prompt "Silicon Rev"
 267         default BF_REV_0_0 if (BF51x || BF52x)
 268         default BF_REV_0_2 if (BF534 || BF536 || BF537 || (BF54x && !BF54xM))
 269         default BF_REV_0_3 if (BF531 || BF532 || BF533 || BF54xM || BF561)
 270
 271 config BF_REV_0_0
 272         bool "0.0"
 273         depends on (BF51x || BF52x || (BF54x && !BF54xM))
 274
 275 config BF_REV_0_1
 276         bool "0.1"
 277         depends on (BF51x || BF52x || (BF54x && !BF54xM))
 278
 279 config BF_REV_0_2
 280         bool "0.2"
 281         depends on (BF52x || BF537 || BF536 || BF534 || (BF54x && !BF54xM))
 282
 283 config BF_REV_0_3
 284         bool "0.3"
 285         depends on (BF54xM || BF561 || BF537 || BF536 || BF534 || BF533 || BF532 || BF531)
 286
 287 config BF_REV_0_4
 288         bool "0.4"
 289         depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539)
 290
 291 config BF_REV_0_5
 292         bool "0.5"
 293         depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539)
 294
 295 config BF_REV_0_6
 296         bool "0.6"
 297         depends on (BF533 || BF532 || BF531)
 298
 299 config BF_REV_ANY
 300         bool "any"
 301
 302 config BF_REV_NONE
 303         bool "none"
 304
 305 endchoice
 306
 307 config BF51x
 308         bool
 309         depends on (BF512 || BF514 || BF516 || BF518)
 310         default y
 311
 312 config BF52x
 313         bool
 314         depends on (BF522 || BF523 || BF524 || BF525 || BF526 || BF527)
 315         default y
 316
 317 config BF53x
 318         bool
 319         depends on (BF531 || BF532 || BF533 || BF534 || BF536 || BF537)
 320         default y
 321
 322 config BF54xM
 323         bool
 324         depends on (BF542M || BF544M || BF547M || BF548M || BF549M)
 325         default y
 326
 327 config BF54x
 328         bool
 329         depends on (BF542 || BF544 || BF547 || BF548 || BF549 || BF54xM)
 330         default y
 331
 332 config MEM_GENERIC_BOARD
 333         bool
 334         depends on GENERIC_BOARD
 335         default y
 336
 337 config MEM_MT48LC64M4A2FB_7E
 338         bool
 339         depends on (BFIN533_STAMP)
 340         default y
 341
 342 config MEM_MT48LC16M16A2TG_75
 343         bool
 344         depends on (BFIN533_EZKIT || BFIN561_EZKIT \
 345                 || BFIN533_BLUETECHNIX_CM || BFIN537_BLUETECHNIX_CM_E \
 346                 || BFIN537_BLUETECHNIX_CM_U || H8606_HVSISTEMAS \
 347                 || BFIN527_BLUETECHNIX_CM)
 348         default y
 349
 350 config MEM_MT48LC32M8A2_75
 351         bool
 352         depends on (BFIN537_STAMP || PNAV10 || BFIN538_EZKIT)
 353         default y
 354
 355 config MEM_MT48LC8M32B2B5_7
 356         bool
 357         depends on (BFIN561_BLUETECHNIX_CM)
 358         default y
 359
 360 config MEM_MT48LC32M16A2TG_75
 361         bool
 362         depends on (BFIN527_EZKIT || BFIN532_IP0X || BLACKSTAMP)
 363         default y
 364
 365 config MEM_MT48LC32M8A2_75
 366         bool
 367         depends on (BFIN518F_EZBRD)
 368         default y
 369
 370 config MEM_MT48H32M16LFCJ_75
 371         bool
 372         depends on (BFIN526_EZBRD)
 373         default y
 374
 375 source "arch/blackfin/mach-bf518/Kconfig"
 376 source "arch/blackfin/mach-bf527/Kconfig"
 377 source "arch/blackfin/mach-bf533/Kconfig"
 378 source "arch/blackfin/mach-bf561/Kconfig"
 379 source "arch/blackfin/mach-bf537/Kconfig"
 380 source "arch/blackfin/mach-bf538/Kconfig"
 381 source "arch/blackfin/mach-bf548/Kconfig"
 382
 383 menu "Board customizations"
 384
 385 config CMDLINE_BOOL
 386         bool "Default bootloader kernel arguments"
 387
 388 config CMDLINE
 389         string "Initial kernel command string"
 390         depends on CMDLINE_BOOL
 391         default "console=ttyBF0,57600"
 392         help
 393           If you don't have a boot loader capable of passing a command line string
 394           to the kernel, you may specify one here. As a minimum, you should specify
 395           the memory size and the root device (e.g., mem=8M, root=/dev/nfs).
 396
 397 config BOOT_LOAD
 398         hex "Kernel load address for booting"
 399         default "0x1000"
 400         range 0x1000 0x20000000
 401         help
 402           This option allows you to set the load address of the kernel.
 403           This can be useful if you are on a board which has a small amount
 404           of memory or you wish to reserve some memory at the beginning of
 405           the address space.
 406
 407           Note that you need to keep this value above 4k (0x1000) as this
 408           memory region is used to capture NULL pointer references as well
 409           as some core kernel functions.
 410
 411 config ROM_BASE
 412         hex "Kernel ROM Base"
 413         depends on ROMKERNEL
 414         default "0x20040000"
 415         range 0x20000000 0x20400000 if !(BF54x || BF561)
 416         range 0x20000000 0x30000000 if (BF54x || BF561)
 417         help
 418
 419 comment "Clock/PLL Setup"
 420
 421 config CLKIN_HZ
 422         int "Frequency of the crystal on the board in Hz"
 423         default "10000000" if BFIN532_IP0X
 424         default "11059200" if BFIN533_STAMP
 425         default "24576000" if PNAV10
 426         default "25000000" # most people use this
 427         default "27000000" if BFIN533_EZKIT
 428         default "30000000" if BFIN561_EZKIT
 429         help
 430           The frequency of CLKIN crystal oscillator on the board in Hz.
 431           Warning: This value should match the crystal on the board. Otherwise,
 432           peripherals won't work properly.
 433
 434 config BFIN_KERNEL_CLOCK
 435         bool "Re-program Clocks while Kernel boots?"
 436         default n
 437         help
 438           This option decides if kernel clocks are re-programed from the
 439           bootloader settings. If the clocks are not set, the SDRAM settings
 440           are also not changed, and the Bootloader does 100% of the hardware
 441           configuration.
 442
 443 config PLL_BYPASS
 444         bool "Bypass PLL"
 445         depends on BFIN_KERNEL_CLOCK
 446         default n
 447
 448 config CLKIN_HALF
 449         bool "Half Clock In"
 450         depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
 451         default n
 452         help
 453           If this is set the clock will be divided by 2, before it goes to the PLL.
 454
 455 config VCO_MULT
 456         int "VCO Multiplier"
 457         depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
 458         range 1 64
 459         default "22" if BFIN533_EZKIT
 460         default "45" if BFIN533_STAMP
 461         default "20" if (BFIN537_STAMP || BFIN527_EZKIT || BFIN548_EZKIT || BFIN548_BLUETECHNIX_CM || BFIN538_EZKIT)
 462         default "22" if BFIN533_BLUETECHNIX_CM
 463         default "20" if (BFIN537_BLUETECHNIX_CM_E || BFIN537_BLUETECHNIX_CM_U || BFIN527_BLUETECHNIX_CM || BFIN561_BLUETECHNIX_CM)
 464         default "20" if BFIN561_EZKIT
 465         default "16" if (H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD || BFIN518F_EZBRD)
 466         help
 467           This controls the frequency of the on-chip PLL. This can be between 1 and 64.
 468           PLL Frequency = (Crystal Frequency) * (this setting)
 469
 470 choice
 471         prompt "Core Clock Divider"
 472         depends on BFIN_KERNEL_CLOCK
 473         default CCLK_DIV_1
 474         help
 475           This sets the frequency of the core. It can be 1, 2, 4 or 8
 476           Core Frequency = (PLL frequency) / (this setting)
 477
 478 config CCLK_DIV_1
 479         bool "1"
 480
 481 config CCLK_DIV_2
 482         bool "2"
 483
 484 config CCLK_DIV_4
 485         bool "4"
 486
 487 config CCLK_DIV_8
 488         bool "8"
 489 endchoice
 490
 491 config SCLK_DIV
 492         int "System Clock Divider"
 493         depends on BFIN_KERNEL_CLOCK
 494         range 1 15
 495         default 5
 496         help
 497           This sets the frequency of the system clock (including SDRAM or DDR).
 498           This can be between 1 and 15
 499           System Clock = (PLL frequency) / (this setting)
 500
 501 choice
 502         prompt "DDR SDRAM Chip Type"
 503         depends on BFIN_KERNEL_CLOCK
 504         depends on BF54x
 505         default MEM_MT46V32M16_5B
 506
 507 config MEM_MT46V32M16_6T
 508         bool "MT46V32M16_6T"
 509
 510 config MEM_MT46V32M16_5B
 511         bool "MT46V32M16_5B"
 512 endchoice
 513
 514 choice
 515         prompt "DDR/SDRAM Timing"
 516         depends on BFIN_KERNEL_CLOCK
 517         default BFIN_KERNEL_CLOCK_MEMINIT_CALC
 518         help
 519           This option allows you to specify Blackfin SDRAM/DDR Timing parameters
 520           The calculated SDRAM timing parameters may not be 100%
 521           accurate - This option is therefore marked experimental.
 522
 523 config BFIN_KERNEL_CLOCK_MEMINIT_CALC
 524         bool "Calculate Timings (EXPERIMENTAL)"
 525         depends on EXPERIMENTAL
 526
 527 config BFIN_KERNEL_CLOCK_MEMINIT_SPEC
 528         bool "Provide accurate Timings based on target SCLK"
 529         help
 530           Please consult the Blackfin Hardware Reference Manuals as well
 531           as the memory device datasheet.
 532           http://docs.blackfin.uclinux.org/doku.php?id=bfin:sdram
 533 endchoice
 534
 535 menu "Memory Init Control"
 536         depends on BFIN_KERNEL_CLOCK_MEMINIT_SPEC
 537
 538 config MEM_DDRCTL0
 539         depends on BF54x
 540         hex "DDRCTL0"
 541         default 0x0
 542
 543 config MEM_DDRCTL1
 544         depends on BF54x
 545         hex "DDRCTL1"
 546         default 0x0
 547
 548 config MEM_DDRCTL2
 549         depends on BF54x
 550         hex "DDRCTL2"
 551         default 0x0
 552
 553 config MEM_EBIU_DDRQUE
 554         depends on BF54x
 555         hex "DDRQUE"
 556         default 0x0
 557
 558 config MEM_SDRRC
 559         depends on !BF54x
 560         hex "SDRRC"
 561         default 0x0
 562
 563 config MEM_SDGCTL
 564         depends on !BF54x
 565         hex "SDGCTL"
 566         default 0x0
 567 endmenu
 568
 569 #
 570 # Max & Min Speeds for various Chips
 571 #
 572 config MAX_VCO_HZ
 573         int
 574         default 400000000 if BF512
 575         default 400000000 if BF514
 576         default 400000000 if BF516
 577         default 400000000 if BF518
 578         default 400000000 if BF522
 579         default 600000000 if BF523
 580         default 400000000 if BF524
 581         default 600000000 if BF525
 582         default 400000000 if BF526
 583         default 600000000 if BF527
 584         default 400000000 if BF531
 585         default 400000000 if BF532
 586         default 750000000 if BF533
 587         default 500000000 if BF534
 588         default 400000000 if BF536
 589         default 600000000 if BF537
 590         default 533333333 if BF538
 591         default 533333333 if BF539
 592         default 600000000 if BF542
 593         default 533333333 if BF544
 594         default 600000000 if BF547
 595         default 600000000 if BF548
 596         default 533333333 if BF549
 597         default 600000000 if BF561
 598
 599 config MIN_VCO_HZ
 600         int
 601         default 50000000
 602
 603 config MAX_SCLK_HZ
 604         int
 605         default 133333333
 606
 607 config MIN_SCLK_HZ
 608         int
 609         default 27000000
 610
 611 comment "Kernel Timer/Scheduler"
 612
 613 source kernel/Kconfig.hz
 614
 615 config GENERIC_TIME
 616         bool "Generic time"
 617         default y
 618
 619 config GENERIC_CLOCKEVENTS
 620         bool "Generic clock events"
 621         depends on GENERIC_TIME
 622         default y
 623
 624 choice
 625         prompt "Kernel Tick Source"
 626         depends on GENERIC_CLOCKEVENTS
 627         default TICKSOURCE_CORETMR
 628
 629 config TICKSOURCE_GPTMR0
 630         bool "Gptimer0 (SCLK domain)"
 631         select BFIN_GPTIMERS
 632
 633 config TICKSOURCE_CORETMR
 634         bool "Core timer (CCLK domain)"
 635
 636 endchoice
 637
 638 config CYCLES_CLOCKSOURCE
 639         bool "Use 'CYCLES' as a clocksource"
 640         depends on GENERIC_CLOCKEVENTS
 641         depends on !BFIN_SCRATCH_REG_CYCLES
 642         depends on !SMP
 643         help
 644           If you say Y here, you will enable support for using the 'cycles'
 645           registers as a clock source.  Doing so means you will be unable to
 646           safely write to the 'cycles' register during runtime.  You will
 647           still be able to read it (such as for performance monitoring), but
 648           writing the registers will most likely crash the kernel.
 649
 650 config GPTMR0_CLOCKSOURCE
 651         bool "Use GPTimer0 as a clocksource"
 652         select BFIN_GPTIMERS
 653         depends on GENERIC_CLOCKEVENTS
 654         depends on !TICKSOURCE_GPTMR0
 655
 656 source kernel/time/Kconfig
 657
 658 comment "Misc"
 659
 660 choice
 661         prompt "Blackfin Exception Scratch Register"
 662         default BFIN_SCRATCH_REG_RETN
 663         help
 664           Select the resource to reserve for the Exception handler:
 665             - RETN: Non-Maskable Interrupt (NMI)
 666             - RETE: Exception Return (JTAG/ICE)
 667             - CYCLES: Performance counter
 668
 669           If you are unsure, please select "RETN".
 670
 671 config BFIN_SCRATCH_REG_RETN
 672         bool "RETN"
 673         help
 674           Use the RETN register in the Blackfin exception handler
 675           as a stack scratch register.  This means you cannot
 676           safely use NMI on the Blackfin while running Linux, but
 677           you can debug the system with a JTAG ICE and use the
 678           CYCLES performance registers.
 679
 680           If you are unsure, please select "RETN".
 681
 682 config BFIN_SCRATCH_REG_RETE
 683         bool "RETE"
 684         help
 685           Use the RETE register in the Blackfin exception handler
 686           as a stack scratch register.  This means you cannot
 687           safely use a JTAG ICE while debugging a Blackfin board,
 688           but you can safely use the CYCLES performance registers
 689           and the NMI.
 690
 691           If you are unsure, please select "RETN".
 692
 693 config BFIN_SCRATCH_REG_CYCLES
 694         bool "CYCLES"
 695         help
 696           Use the CYCLES register in the Blackfin exception handler
 697           as a stack scratch register.  This means you cannot
 698           safely use the CYCLES performance registers on a Blackfin
 699           board at anytime, but you can debug the system with a JTAG
 700           ICE and use the NMI.
 701
 702           If you are unsure, please select "RETN".
 703
 704 endchoice
 705
 706 endmenu
 707
 708
 709 menu "Blackfin Kernel Optimizations"
 710         depends on !SMP
 711
 712 comment "Memory Optimizations"
 713
 714 config I_ENTRY_L1
 715         bool "Locate interrupt entry code in L1 Memory"
 716         default y
 717         help
 718           If enabled, interrupt entry code (STORE/RESTORE CONTEXT) is linked
 719           into L1 instruction memory. (less latency)
 720
 721 config EXCPT_IRQ_SYSC_L1
 722         bool "Locate entire ASM lowlevel exception / interrupt - Syscall and CPLB handler code in L1 Memory"
 723         default y
 724         help
 725           If enabled, the entire ASM lowlevel exception and interrupt entry code
 726           (STORE/RESTORE CONTEXT) is linked into L1 instruction memory.
 727           (less latency)
 728
 729 config DO_IRQ_L1
 730         bool "Locate frequently called do_irq dispatcher function in L1 Memory"
 731         default y
 732         help
 733           If enabled, the frequently called do_irq dispatcher function is linked
 734           into L1 instruction memory. (less latency)
 735
 736 config CORE_TIMER_IRQ_L1
 737         bool "Locate frequently called timer_interrupt() function in L1 Memory"
 738         default y
 739         help
 740           If enabled, the frequently called timer_interrupt() function is linked
 741           into L1 instruction memory. (less latency)
 742
 743 config IDLE_L1
 744         bool "Locate frequently idle function in L1 Memory"
 745         default y
 746         help
 747           If enabled, the frequently called idle function is linked
 748           into L1 instruction memory. (less latency)
 749
 750 config SCHEDULE_L1
 751         bool "Locate kernel schedule function in L1 Memory"
 752         default y
 753         help
 754           If enabled, the frequently called kernel schedule is linked
 755           into L1 instruction memory. (less latency)
 756
 757 config ARITHMETIC_OPS_L1
 758         bool "Locate kernel owned arithmetic functions in L1 Memory"
 759         default y
 760         help
 761           If enabled, arithmetic functions are linked
 762           into L1 instruction memory. (less latency)
 763
 764 config ACCESS_OK_L1
 765         bool "Locate access_ok function in L1 Memory"
 766         default y
 767         help
 768           If enabled, the access_ok function is linked
 769           into L1 instruction memory. (less latency)
 770
 771 config MEMSET_L1
 772         bool "Locate memset function in L1 Memory"
 773         default y
 774         help
 775           If enabled, the memset function is linked
 776           into L1 instruction memory. (less latency)
 777
 778 config MEMCPY_L1
 779         bool "Locate memcpy function in L1 Memory"
 780         default y
 781         help
 782           If enabled, the memcpy function is linked
 783           into L1 instruction memory. (less latency)
 784
 785 config SYS_BFIN_SPINLOCK_L1
 786         bool "Locate sys_bfin_spinlock function in L1 Memory"
 787         default y
 788         help
 789           If enabled, sys_bfin_spinlock function is linked
 790           into L1 instruction memory. (less latency)
 791
 792 config IP_CHECKSUM_L1
 793         bool "Locate IP Checksum function in L1 Memory"
 794         default n
 795         help
 796           If enabled, the IP Checksum function is linked
 797           into L1 instruction memory. (less latency)
 798
 799 config CACHELINE_ALIGNED_L1
 800         bool "Locate cacheline_aligned data to L1 Data Memory"
 801         default y if !BF54x
 802         default n if BF54x
 803         depends on !BF531
 804         help
 805           If enabled, cacheline_aligned data is linked
 806           into L1 data memory. (less latency)
 807
 808 config SYSCALL_TAB_L1
 809         bool "Locate Syscall Table L1 Data Memory"
 810         default n
 811         depends on !BF531
 812         help
 813           If enabled, the Syscall LUT is linked
 814           into L1 data memory. (less latency)
 815
 816 config CPLB_SWITCH_TAB_L1
 817         bool "Locate CPLB Switch Tables L1 Data Memory"
 818         default n
 819         depends on !BF531
 820         help
 821           If enabled, the CPLB Switch Tables are linked
 822           into L1 data memory. (less latency)
 823
 824 config APP_STACK_L1
 825         bool "Support locating application stack in L1 Scratch Memory"
 826         default y
 827         help
 828           If enabled the application stack can be located in L1
 829           scratch memory (less latency).
 830
 831           Currently only works with FLAT binaries.
 832
 833 config EXCEPTION_L1_SCRATCH
 834         bool "Locate exception stack in L1 Scratch Memory"
 835         default n
 836         depends on !APP_STACK_L1
 837         help
 838           Whenever an exception occurs, use the L1 Scratch memory for
 839           stack storage.  You cannot place the stacks of FLAT binaries
 840           in L1 when using this option.
 841
 842           If you don't use L1 Scratch, then you should say Y here.
 843
 844 comment "Speed Optimizations"
 845 config BFIN_INS_LOWOVERHEAD
 846         bool "ins[bwl] low overhead, higher interrupt latency"
 847         default y
 848         help
 849           Reads on the Blackfin are speculative. In Blackfin terms, this means
 850           they can be interrupted at any time (even after they have been issued
 851           on to the external bus), and re-issued after the interrupt occurs.
 852           For memory - this is not a big deal, since memory does not change if
 853           it sees a read.
 854
 855           If a FIFO is sitting on the end of the read, it will see two reads,
 856           when the core only sees one since the FIFO receives both the read
 857           which is cancelled (and not delivered to the core) and the one which
 858           is re-issued (which is delivered to the core).
 859
 860           To solve this, interrupts are turned off before reads occur to
 861           I/O space. This option controls which the overhead/latency of
 862           controlling interrupts during this time
 863            "n" turns interrupts off every read
 864                 (higher overhead, but lower interrupt latency)
 865            "y" turns interrupts off every loop
 866                 (low overhead, but longer interrupt latency)
 867
 868           default behavior is to leave this set to on (type "Y"). If you are experiencing
 869           interrupt latency issues, it is safe and OK to turn this off.
 870
 871 endmenu
 872
 873 choice
 874         prompt "Kernel executes from"
 875         help
 876           Choose the memory type that the kernel will be running in.
 877
 878 config RAMKERNEL
 879         bool "RAM"
 880         help
 881           The kernel will be resident in RAM when running.
 882
 883 config ROMKERNEL
 884         bool "ROM"
 885         help
 886           The kernel will be resident in FLASH/ROM when running.
 887
 888 endchoice
 889
 890 source "mm/Kconfig"
 891
 892 config BFIN_GPTIMERS
 893         tristate "Enable Blackfin General Purpose Timers API"
 894         default n
 895         help
 896           Enable support for the General Purpose Timers API.  If you
 897           are unsure, say N.
 898
 899           To compile this driver as a module, choose M here: the module
 900           will be called gptimers.
 901
 902 choice
 903         prompt "Uncached DMA region"
 904         default DMA_UNCACHED_1M
 905 config DMA_UNCACHED_4M
 906         bool "Enable 4M DMA region"
 907 config DMA_UNCACHED_2M
 908         bool "Enable 2M DMA region"
 909 config DMA_UNCACHED_1M
 910         bool "Enable 1M DMA region"
 911 config DMA_UNCACHED_NONE
 912         bool "Disable DMA region"
 913 endchoice
 914
 915
 916 comment "Cache Support"
 917
 918 config BFIN_ICACHE
 919         bool "Enable ICACHE"
 920         default y
 921 config BFIN_EXTMEM_ICACHEABLE
 922         bool "Enable ICACHE for external memory"
 923         depends on BFIN_ICACHE
 924         default y
 925 config BFIN_L2_ICACHEABLE
 926         bool "Enable ICACHE for L2 SRAM"
 927         depends on BFIN_ICACHE
 928         depends on BF54x || BF561
 929         default n
 930
 931 config BFIN_DCACHE
 932         bool "Enable DCACHE"
 933         default y
 934 config BFIN_DCACHE_BANKA
 935         bool "Enable only 16k BankA DCACHE - BankB is SRAM"
 936         depends on BFIN_DCACHE && !BF531
 937         default n
 938 config BFIN_EXTMEM_DCACHEABLE
 939         bool "Enable DCACHE for external memory"
 940         depends on BFIN_DCACHE
 941         default y
 942 choice
 943         prompt "External memory DCACHE policy"
 944         depends on BFIN_EXTMEM_DCACHEABLE
 945         default BFIN_EXTMEM_WRITEBACK if !SMP
 946         default BFIN_EXTMEM_WRITETHROUGH if SMP
 947 config BFIN_EXTMEM_WRITEBACK
 948         bool "Write back"
 949         depends on !SMP
 950         help
 951           Write Back Policy:
 952             Cached data will be written back to SDRAM only when needed.
 953             This can give a nice increase in performance, but beware of
 954             broken drivers that do not properly invalidate/flush their
 955             cache.
 956
 957           Write Through Policy:
 958             Cached data will always be written back to SDRAM when the
 959             cache is updated.  This is a completely safe setting, but
 960             performance is worse than Write Back.
 961
 962           If you are unsure of the options and you want to be safe,
 963           then go with Write Through.
 964
 965 config BFIN_EXTMEM_WRITETHROUGH
 966         bool "Write through"
 967         help
 968           Write Back Policy:
 969             Cached data will be written back to SDRAM only when needed.
 970             This can give a nice increase in performance, but beware of
 971             broken drivers that do not properly invalidate/flush their
 972             cache.
 973
 974           Write Through Policy:
 975             Cached data will always be written back to SDRAM when the
 976             cache is updated.  This is a completely safe setting, but
 977             performance is worse than Write Back.
 978
 979           If you are unsure of the options and you want to be safe,
 980           then go with Write Through.
 981
 982 endchoice
 983
 984 config BFIN_L2_DCACHEABLE
 985         bool "Enable DCACHE for L2 SRAM"
 986         depends on BFIN_DCACHE
 987         depends on (BF54x || BF561) && !SMP
 988         default n
 989 choice
 990         prompt "L2 SRAM DCACHE policy"
 991         depends on BFIN_L2_DCACHEABLE
 992         default BFIN_L2_WRITEBACK
 993 config BFIN_L2_WRITEBACK
 994         bool "Write back"
 995
 996 config BFIN_L2_WRITETHROUGH
 997         bool "Write through"
 998 endchoice
 999
1000
1001 comment "Memory Protection Unit"
1002 config MPU
1003         bool "Enable the memory protection unit (EXPERIMENTAL)"
1004         default n
1005         help
1006           Use the processor's MPU to protect applications from accessing
1007           memory they do not own.  This comes at a performance penalty
1008           and is recommended only for debugging.
1009
1010 comment "Asynchronous Memory Configuration"
1011
1012 menu "EBIU_AMGCTL Global Control"
1013 config C_AMCKEN
1014         bool "Enable CLKOUT"
1015         default y
1016
1017 config C_CDPRIO
1018         bool "DMA has priority over core for ext. accesses"
1019         default n
1020
1021 config C_B0PEN
1022         depends on BF561
1023         bool "Bank 0 16 bit packing enable"
1024         default y
1025
1026 config C_B1PEN
1027         depends on BF561
1028         bool "Bank 1 16 bit packing enable"
1029         default y
1030
1031 config C_B2PEN
1032         depends on BF561
1033         bool "Bank 2 16 bit packing enable"
1034         default y
1035
1036 config C_B3PEN
1037         depends on BF561
1038         bool "Bank 3 16 bit packing enable"
1039         default n
1040
1041 choice
1042         prompt "Enable Asynchronous Memory Banks"
1043         default C_AMBEN_ALL
1044
1045 config C_AMBEN
1046         bool "Disable All Banks"
1047
1048 config C_AMBEN_B0
1049         bool "Enable Bank 0"
1050
1051 config C_AMBEN_B0_B1
1052         bool "Enable Bank 0 & 1"
1053
1054 config C_AMBEN_B0_B1_B2
1055         bool "Enable Bank 0 & 1 & 2"
1056
1057 config C_AMBEN_ALL
1058         bool "Enable All Banks"
1059 endchoice
1060 endmenu
1061
1062 menu "EBIU_AMBCTL Control"
1063 config BANK_0
1064         hex "Bank 0 (AMBCTL0.L)"
1065         default 0x7BB0
1066         help
1067           These are the low 16 bits of the EBIU_AMBCTL0 MMR which are
1068           used to control the Asynchronous Memory Bank 0 settings.
1069
1070 config BANK_1
1071         hex "Bank 1 (AMBCTL0.H)"
1072         default 0x7BB0
1073         default 0x5558 if BF54x
1074         help
1075           These are the high 16 bits of the EBIU_AMBCTL0 MMR which are
1076           used to control the Asynchronous Memory Bank 1 settings.
1077
1078 config BANK_2
1079         hex "Bank 2 (AMBCTL1.L)"
1080         default 0x7BB0
1081         help
1082           These are the low 16 bits of the EBIU_AMBCTL1 MMR which are
1083           used to control the Asynchronous Memory Bank 2 settings.
1084
1085 config BANK_3
1086         hex "Bank 3 (AMBCTL1.H)"
1087         default 0x99B3
1088         help
1089           These are the high 16 bits of the EBIU_AMBCTL1 MMR which are
1090           used to control the Asynchronous Memory Bank 3 settings.
1091
1092 endmenu
1093
1094 config EBIU_MBSCTLVAL
1095         hex "EBIU Bank Select Control Register"
1096         depends on BF54x
1097         default 0
1098
1099 config EBIU_MODEVAL
1100         hex "Flash Memory Mode Control Register"
1101         depends on BF54x
1102         default 1
1103
1104 config EBIU_FCTLVAL
1105         hex "Flash Memory Bank Control Register"
1106         depends on BF54x
1107         default 6
1108 endmenu
1109
1110 #############################################################################
1111 menu "Bus options (PCI, PCMCIA, EISA, MCA, ISA)"
1112
1113 config PCI
1114         bool "PCI support"
1115         depends on BROKEN
1116         help
1117           Support for PCI bus.
1118
1119 source "drivers/pci/Kconfig"
1120
1121 config HOTPLUG
1122         bool "Support for hot-pluggable device"
1123           help
1124           Say Y here if you want to plug devices into your computer while
1125           the system is running, and be able to use them quickly.  In many
1126           cases, the devices can likewise be unplugged at any time too.
1127
1128           One well known example of this is PCMCIA- or PC-cards, credit-card
1129           size devices such as network cards, modems or hard drives which are
1130           plugged into slots found on all modern laptop computers.  Another
1131           example, used on modern desktops as well as laptops, is USB.
1132
1133           Enable HOTPLUG and build a modular kernel.  Get agent software
1134           (from <http://linux-hotplug.sourceforge.net/>) and install it.
1135           Then your kernel will automatically call out to a user mode "policy
1136           agent" (/sbin/hotplug) to load modules and set up software needed
1137           to use devices as you hotplug them.
1138
1139 source "drivers/pcmcia/Kconfig"
1140
1141 source "drivers/pci/hotplug/Kconfig"
1142
1143 endmenu
1144
1145 menu "Executable file formats"
1146
1147 source "fs/Kconfig.binfmt"
1148
1149 endmenu
1150
1151 menu "Power management options"
1152         depends on !SMP
1153
1154 source "kernel/power/Kconfig"
1155
1156 config ARCH_SUSPEND_POSSIBLE
1157         def_bool y
1158
1159 choice
1160         prompt "Standby Power Saving Mode"
1161         depends on PM
1162         default PM_BFIN_SLEEP_DEEPER
1163 config  PM_BFIN_SLEEP_DEEPER
1164         bool "Sleep Deeper"
1165         help
1166           Sleep "Deeper" Mode (High Power Savings) - This mode reduces dynamic
1167           power dissipation by disabling the clock to the processor core (CCLK).
1168           Furthermore, Standby sets the internal power supply voltage (VDDINT)
1169           to 0.85 V to provide the greatest power savings, while preserving the
1170           processor state.
1171           The PLL and system clock (SCLK) continue to operate at a very low
1172           frequency of about 3.3 MHz. To preserve data integrity in the SDRAM,
1173           the SDRAM is put into Self Refresh Mode. Typically an external event
1174           such as GPIO interrupt or RTC activity wakes up the processor.
1175           Various Peripherals such as UART, SPORT, PPI may not function as
1176           normal during Sleep Deeper, due to the reduced SCLK frequency.
1177           When in the sleep mode, system DMA access to L1 memory is not supported.
1178
1179           If unsure, select "Sleep Deeper".
1180
1181 config  PM_BFIN_SLEEP
1182         bool "Sleep"
1183         help
1184           Sleep Mode (High Power Savings) - The sleep mode reduces power
1185           dissipation by disabling the clock to the processor core (CCLK).
1186           The PLL and system clock (SCLK), however, continue to operate in
1187           this mode. Typically an external event or RTC activity will wake
1188           up the processor. When in the sleep mode, system DMA access to L1
1189           memory is not supported.
1190
1191           If unsure, select "Sleep Deeper".
1192 endchoice
1193
1194 config PM_WAKEUP_BY_GPIO
1195         bool "Allow Wakeup from Standby by GPIO"
1196         depends on PM && !BF54x
1197
1198 config PM_WAKEUP_GPIO_NUMBER
1199         int "GPIO number"
1200         range 0 47
1201         depends on PM_WAKEUP_BY_GPIO
1202         default 2
1203
1204 choice
1205         prompt "GPIO Polarity"
1206         depends on PM_WAKEUP_BY_GPIO
1207         default PM_WAKEUP_GPIO_POLAR_H
1208 config  PM_WAKEUP_GPIO_POLAR_H
1209         bool "Active High"
1210 config  PM_WAKEUP_GPIO_POLAR_L
1211         bool "Active Low"
1212 config  PM_WAKEUP_GPIO_POLAR_EDGE_F
1213         bool "Falling EDGE"
1214 config  PM_WAKEUP_GPIO_POLAR_EDGE_R
1215         bool "Rising EDGE"
1216 config  PM_WAKEUP_GPIO_POLAR_EDGE_B
1217         bool "Both EDGE"
1218 endchoice
1219
1220 comment "Possible Suspend Mem / Hibernate Wake-Up Sources"
1221         depends on PM
1222
1223 config PM_BFIN_WAKE_PH6
1224         bool "Allow Wake-Up from on-chip PHY or PH6 GP"
1225         depends on PM && (BF51x || BF52x || BF534 || BF536 || BF537)
1226         default n
1227         help
1228           Enable PHY and PH6 GP Wake-Up (Voltage Regulator Power-Up)
1229
1230 config PM_BFIN_WAKE_GP
1231         bool "Allow Wake-Up from GPIOs"
1232         depends on PM && BF54x
1233         default n
1234         help
1235           Enable General-Purpose Wake-Up (Voltage Regulator Power-Up)
1236           (all processors, except ADSP-BF549). This option sets
1237           the general-purpose wake-up enable (GPWE) control bit to enable
1238           wake-up upon detection of an active low signal on the /GPW (PH7) pin.
1239           On ADSP-BF549 this option enables the the same functionality on the
1240           /MRXON pin also PH7.
1241
1242 endmenu
1243
1244 menu "CPU Frequency scaling"
1245         depends on !SMP
1246
1247 source "drivers/cpufreq/Kconfig"
1248
1249 config BFIN_CPU_FREQ
1250         bool
1251         depends on CPU_FREQ
1252         select CPU_FREQ_TABLE
1253         default y
1254
1255 config CPU_VOLTAGE
1256         bool "CPU Voltage scaling"
1257         depends on EXPERIMENTAL
1258         depends on CPU_FREQ
1259         default n
1260         help
1261           Say Y here if you want CPU voltage scaling according to the CPU frequency.
1262           This option violates the PLL BYPASS recommendation in the Blackfin Processor
1263           manuals. There is a theoretical risk that during VDDINT transitions
1264           the PLL may unlock.
1265
1266 endmenu
1267
1268 source "net/Kconfig"
1269
1270 source "drivers/Kconfig"
1271
1272 source "fs/Kconfig"
1273
1274 source "arch/blackfin/Kconfig.debug"
1275
1276 source "security/Kconfig"
1277
1278 source "crypto/Kconfig"
1279
1280 source "lib/Kconfig"