arch/blackfin/Kconfig

   1 #
   2 # For a description of the syntax of this configuration file,
   3 # see Documentation/kbuild/kconfig-language.txt.
   4 #
   5
   6 mainmenu "Blackfin Kernel Configuration"
   7
   8 config MMU
   9         bool
  10         default n
  11
  12 config FPU
  13         bool
  14         default n
  15
  16 config RWSEM_GENERIC_SPINLOCK
  17         bool
  18         default y
  19
  20 config RWSEM_XCHGADD_ALGORITHM
  21         bool
  22         default n
  23
  24 config BLACKFIN
  25         bool
  26         default y
  27         select HAVE_IDE
  28         select HAVE_OPROFILE
  29         select ARCH_WANT_OPTIONAL_GPIOLIB
  30
  31 config ZONE_DMA
  32         bool
  33         default y
  34
  35 config GENERIC_FIND_NEXT_BIT
  36         bool
  37         default y
  38
  39 config GENERIC_HWEIGHT
  40         bool
  41         default y
  42
  43 config GENERIC_HARDIRQS
  44         bool
  45         default y
  46
  47 config GENERIC_IRQ_PROBE
  48         bool
  49         default y
  50
  51 config GENERIC_GPIO
  52         bool
  53         default y
  54
  55 config FORCE_MAX_ZONEORDER
  56         int
  57         default "14"
  58
  59 config GENERIC_CALIBRATE_DELAY
  60         bool
  61         default y
  62
  63 source "init/Kconfig"
  64
  65 source "kernel/Kconfig.preempt"
  66
  67 source "kernel/Kconfig.freezer"
  68
  69 menu "Blackfin Processor Options"
  70
  71 comment "Processor and Board Settings"
  72
  73 choice
  74         prompt "CPU"
  75         default BF533
  76
  77 config BF512
  78         bool "BF512"
  79         help
  80           BF512 Processor Support.
  81
  82 config BF514
  83         bool "BF514"
  84         help
  85           BF514 Processor Support.
  86
  87 config BF516
  88         bool "BF516"
  89         help
  90           BF516 Processor Support.
  91
  92 config BF518
  93         bool "BF518"
  94         help
  95           BF518 Processor Support.
  96
  97 config BF522
  98         bool "BF522"
  99         help
 100           BF522 Processor Support.
 101
 102 config BF523
 103         bool "BF523"
 104         help
 105           BF523 Processor Support.
 106
 107 config BF524
 108         bool "BF524"
 109         help
 110           BF524 Processor Support.
 111
 112 config BF525
 113         bool "BF525"
 114         help
 115           BF525 Processor Support.
 116
 117 config BF526
 118         bool "BF526"
 119         help
 120           BF526 Processor Support.
 121
 122 config BF527
 123         bool "BF527"
 124         help
 125           BF527 Processor Support.
 126
 127 config BF531
 128         bool "BF531"
 129         help
 130           BF531 Processor Support.
 131
 132 config BF532
 133         bool "BF532"
 134         help
 135           BF532 Processor Support.
 136
 137 config BF533
 138         bool "BF533"
 139         help
 140           BF533 Processor Support.
 141
 142 config BF534
 143         bool "BF534"
 144         help
 145           BF534 Processor Support.
 146
 147 config BF536
 148         bool "BF536"
 149         help
 150           BF536 Processor Support.
 151
 152 config BF537
 153         bool "BF537"
 154         help
 155           BF537 Processor Support.
 156
 157 config BF538
 158         bool "BF538"
 159         help
 160           BF538 Processor Support.
 161
 162 config BF539
 163         bool "BF539"
 164         help
 165           BF539 Processor Support.
 166
 167 config BF542
 168         bool "BF542"
 169         help
 170           BF542 Processor Support.
 171
 172 config BF544
 173         bool "BF544"
 174         help
 175           BF544 Processor Support.
 176
 177 config BF547
 178         bool "BF547"
 179         help
 180           BF547 Processor Support.
 181
 182 config BF548
 183         bool "BF548"
 184         help
 185           BF548 Processor Support.
 186
 187 config BF549
 188         bool "BF549"
 189         help
 190           BF549 Processor Support.
 191
 192 config BF561
 193         bool "BF561"
 194         help
 195           BF561 Processor Support.
 196
 197 endchoice
 198
 199 config SMP
 200         depends on BF561
 201         bool "Symmetric multi-processing support"
 202         ---help---
 203           This enables support for systems with more than one CPU,
 204           like the dual core BF561. If you have a system with only one
 205           CPU, say N. If you have a system with more than one CPU, say Y.
 206
 207           If you don't know what to do here, say N.
 208
 209 config NR_CPUS
 210         int
 211         depends on SMP
 212         default 2 if BF561
 213
 214 config IRQ_PER_CPU
 215         bool
 216         depends on SMP
 217         default y
 218
 219 config TICK_SOURCE_SYSTMR0
 220         bool
 221         select BFIN_GPTIMERS
 222         depends on SMP
 223         default y
 224
 225 config BF_REV_MIN
 226         int
 227         default 0 if (BF51x || BF52x || BF54x)
 228         default 2 if (BF537 || BF536 || BF534)
 229         default 3 if (BF561 ||BF533 || BF532 || BF531)
 230         default 4 if (BF538 || BF539)
 231
 232 config BF_REV_MAX
 233         int
 234         default 2 if (BF51x || BF52x || BF54x)
 235         default 3 if (BF537 || BF536 || BF534)
 236         default 5 if (BF561 || BF538 || BF539)
 237         default 6 if (BF533 || BF532 || BF531)
 238
 239 choice
 240         prompt "Silicon Rev"
 241         default BF_REV_0_1 if (BF51x || BF52x || BF54x)
 242         default BF_REV_0_2 if (BF534 || BF536 || BF537)
 243         default BF_REV_0_3 if (BF531 || BF532 || BF533 || BF561)
 244
 245 config BF_REV_0_0
 246         bool "0.0"
 247         depends on (BF51x || BF52x || BF54x)
 248
 249 config BF_REV_0_1
 250         bool "0.1"
 251         depends on (BF52x || BF54x)
 252
 253 config BF_REV_0_2
 254         bool "0.2"
 255         depends on (BF52x || BF537 || BF536 || BF534 || BF54x)
 256
 257 config BF_REV_0_3
 258         bool "0.3"
 259         depends on (BF561 || BF537 || BF536 || BF534 || BF533 || BF532 || BF531)
 260
 261 config BF_REV_0_4
 262         bool "0.4"
 263         depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539)
 264
 265 config BF_REV_0_5
 266         bool "0.5"
 267         depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539)
 268
 269 config BF_REV_0_6
 270         bool "0.6"
 271         depends on (BF533 || BF532 || BF531)
 272
 273 config BF_REV_ANY
 274         bool "any"
 275
 276 config BF_REV_NONE
 277         bool "none"
 278
 279 endchoice
 280
 281 config BF51x
 282         bool
 283         depends on (BF512 || BF514 || BF516 || BF518)
 284         default y
 285
 286 config BF52x
 287         bool
 288         depends on (BF522 || BF523 || BF524 || BF525 || BF526 || BF527)
 289         default y
 290
 291 config BF53x
 292         bool
 293         depends on (BF531 || BF532 || BF533 || BF534 || BF536 || BF537)
 294         default y
 295
 296 config BF54x
 297         bool
 298         depends on (BF542 || BF544 || BF547 || BF548 || BF549)
 299         default y
 300
 301 config MEM_GENERIC_BOARD
 302         bool
 303         depends on GENERIC_BOARD
 304         default y
 305
 306 config MEM_MT48LC64M4A2FB_7E
 307         bool
 308         depends on (BFIN533_STAMP)
 309         default y
 310
 311 config MEM_MT48LC16M16A2TG_75
 312         bool
 313         depends on (BFIN533_EZKIT || BFIN561_EZKIT \
 314                 || BFIN533_BLUETECHNIX_CM || BFIN537_BLUETECHNIX_CM \
 315                 || H8606_HVSISTEMAS || BFIN527_BLUETECHNIX_CM)
 316         default y
 317
 318 config MEM_MT48LC32M8A2_75
 319         bool
 320         depends on (BFIN537_STAMP || PNAV10 || BFIN538_EZKIT)
 321         default y
 322
 323 config MEM_MT48LC8M32B2B5_7
 324         bool
 325         depends on (BFIN561_BLUETECHNIX_CM)
 326         default y
 327
 328 config MEM_MT48LC32M16A2TG_75
 329         bool
 330         depends on (BFIN527_EZKIT || BFIN532_IP0X || BLACKSTAMP || BFIN526_EZBRD)
 331         default y
 332
 333 config MEM_MT48LC32M8A2_75
 334         bool
 335         depends on (BFIN518F_EZBRD)
 336         default y
 337
 338 source "arch/blackfin/mach-bf518/Kconfig"
 339 source "arch/blackfin/mach-bf527/Kconfig"
 340 source "arch/blackfin/mach-bf533/Kconfig"
 341 source "arch/blackfin/mach-bf561/Kconfig"
 342 source "arch/blackfin/mach-bf537/Kconfig"
 343 source "arch/blackfin/mach-bf538/Kconfig"
 344 source "arch/blackfin/mach-bf548/Kconfig"
 345
 346 menu "Board customizations"
 347
 348 config CMDLINE_BOOL
 349         bool "Default bootloader kernel arguments"
 350
 351 config CMDLINE
 352         string "Initial kernel command string"
 353         depends on CMDLINE_BOOL
 354         default "console=ttyBF0,57600"
 355         help
 356           If you don't have a boot loader capable of passing a command line string
 357           to the kernel, you may specify one here. As a minimum, you should specify
 358           the memory size and the root device (e.g., mem=8M, root=/dev/nfs).
 359
 360 config BOOT_LOAD
 361         hex "Kernel load address for booting"
 362         default "0x1000"
 363         range 0x1000 0x20000000
 364         help
 365           This option allows you to set the load address of the kernel.
 366           This can be useful if you are on a board which has a small amount
 367           of memory or you wish to reserve some memory at the beginning of
 368           the address space.
 369
 370           Note that you need to keep this value above 4k (0x1000) as this
 371           memory region is used to capture NULL pointer references as well
 372           as some core kernel functions.
 373
 374 config ROM_BASE
 375         hex "Kernel ROM Base"
 376         depends on ROMKERNEL
 377         default "0x20040000"
 378         range 0x20000000 0x20400000 if !(BF54x || BF561)
 379         range 0x20000000 0x30000000 if (BF54x || BF561)
 380         help
 381
 382 comment "Clock/PLL Setup"
 383
 384 config CLKIN_HZ
 385         int "Frequency of the crystal on the board in Hz"
 386         default "11059200" if BFIN533_STAMP
 387         default "27000000" if BFIN533_EZKIT
 388         default "25000000" if (BFIN537_STAMP || BFIN527_EZKIT || H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD || BFIN538_EZKIT || BFIN518F-EZBRD)
 389         default "30000000" if BFIN561_EZKIT
 390         default "24576000" if PNAV10
 391         default "10000000" if BFIN532_IP0X
 392         help
 393           The frequency of CLKIN crystal oscillator on the board in Hz.
 394           Warning: This value should match the crystal on the board. Otherwise,
 395           peripherals won't work properly.
 396
 397 config BFIN_KERNEL_CLOCK
 398         bool "Re-program Clocks while Kernel boots?"
 399         default n
 400         help
 401           This option decides if kernel clocks are re-programed from the
 402           bootloader settings. If the clocks are not set, the SDRAM settings
 403           are also not changed, and the Bootloader does 100% of the hardware
 404           configuration.
 405
 406 config PLL_BYPASS
 407         bool "Bypass PLL"
 408         depends on BFIN_KERNEL_CLOCK
 409         default n
 410
 411 config CLKIN_HALF
 412         bool "Half Clock In"
 413         depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
 414         default n
 415         help
 416           If this is set the clock will be divided by 2, before it goes to the PLL.
 417
 418 config VCO_MULT
 419         int "VCO Multiplier"
 420         depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
 421         range 1 64
 422         default "22" if BFIN533_EZKIT
 423         default "45" if BFIN533_STAMP
 424         default "20" if (BFIN537_STAMP || BFIN527_EZKIT || BFIN548_EZKIT || BFIN548_BLUETECHNIX_CM || BFIN538_EZKIT)
 425         default "22" if BFIN533_BLUETECHNIX_CM
 426         default "20" if (BFIN537_BLUETECHNIX_CM || BFIN527_BLUETECHNIX_CM || BFIN561_BLUETECHNIX_CM)
 427         default "20" if BFIN561_EZKIT
 428         default "16" if (H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD || BFIN518F_EZBRD)
 429         help
 430           This controls the frequency of the on-chip PLL. This can be between 1 and 64.
 431           PLL Frequency = (Crystal Frequency) * (this setting)
 432
 433 choice
 434         prompt "Core Clock Divider"
 435         depends on BFIN_KERNEL_CLOCK
 436         default CCLK_DIV_1
 437         help
 438           This sets the frequency of the core. It can be 1, 2, 4 or 8
 439           Core Frequency = (PLL frequency) / (this setting)
 440
 441 config CCLK_DIV_1
 442         bool "1"
 443
 444 config CCLK_DIV_2
 445         bool "2"
 446
 447 config CCLK_DIV_4
 448         bool "4"
 449
 450 config CCLK_DIV_8
 451         bool "8"
 452 endchoice
 453
 454 config SCLK_DIV
 455         int "System Clock Divider"
 456         depends on BFIN_KERNEL_CLOCK
 457         range 1 15
 458         default 5
 459         help
 460           This sets the frequency of the system clock (including SDRAM or DDR).
 461           This can be between 1 and 15
 462           System Clock = (PLL frequency) / (this setting)
 463
 464 choice
 465         prompt "DDR SDRAM Chip Type"
 466         depends on BFIN_KERNEL_CLOCK
 467         depends on BF54x
 468         default MEM_MT46V32M16_5B
 469
 470 config MEM_MT46V32M16_6T
 471         bool "MT46V32M16_6T"
 472
 473 config MEM_MT46V32M16_5B
 474         bool "MT46V32M16_5B"
 475 endchoice
 476
 477 choice
 478         prompt "DDR/SDRAM Timing"
 479         depends on BFIN_KERNEL_CLOCK
 480         default BFIN_KERNEL_CLOCK_MEMINIT_CALC
 481         help
 482           This option allows you to specify Blackfin SDRAM/DDR Timing parameters
 483           The calculated SDRAM timing parameters may not be 100%
 484           accurate - This option is therefore marked experimental.
 485
 486 config BFIN_KERNEL_CLOCK_MEMINIT_CALC
 487         bool "Calculate Timings (EXPERIMENTAL)"
 488         depends on EXPERIMENTAL
 489
 490 config BFIN_KERNEL_CLOCK_MEMINIT_SPEC
 491         bool "Provide accurate Timings based on target SCLK"
 492         help
 493           Please consult the Blackfin Hardware Reference Manuals as well
 494           as the memory device datasheet.
 495           http://docs.blackfin.uclinux.org/doku.php?id=bfin:sdram
 496 endchoice
 497
 498 menu "Memory Init Control"
 499         depends on BFIN_KERNEL_CLOCK_MEMINIT_SPEC
 500
 501 config MEM_DDRCTL0
 502         depends on BF54x
 503         hex "DDRCTL0"
 504         default 0x0
 505
 506 config MEM_DDRCTL1
 507         depends on BF54x
 508         hex "DDRCTL1"
 509         default 0x0
 510
 511 config MEM_DDRCTL2
 512         depends on BF54x
 513         hex "DDRCTL2"
 514         default 0x0
 515
 516 config MEM_EBIU_DDRQUE
 517         depends on BF54x
 518         hex "DDRQUE"
 519         default 0x0
 520
 521 config MEM_SDRRC
 522         depends on !BF54x
 523         hex "SDRRC"
 524         default 0x0
 525
 526 config MEM_SDGCTL
 527         depends on !BF54x
 528         hex "SDGCTL"
 529         default 0x0
 530 endmenu
 531
 532 #
 533 # Max & Min Speeds for various Chips
 534 #
 535 config MAX_VCO_HZ
 536         int
 537         default 400000000 if BF512
 538         default 400000000 if BF514
 539         default 400000000 if BF516
 540         default 400000000 if BF518
 541         default 600000000 if BF522
 542         default 400000000 if BF523
 543         default 400000000 if BF524
 544         default 600000000 if BF525
 545         default 400000000 if BF526
 546         default 600000000 if BF527
 547         default 400000000 if BF531
 548         default 400000000 if BF532
 549         default 750000000 if BF533
 550         default 500000000 if BF534
 551         default 400000000 if BF536
 552         default 600000000 if BF537
 553         default 533333333 if BF538
 554         default 533333333 if BF539
 555         default 600000000 if BF542
 556         default 533333333 if BF544
 557         default 600000000 if BF547
 558         default 600000000 if BF548
 559         default 533333333 if BF549
 560         default 600000000 if BF561
 561
 562 config MIN_VCO_HZ
 563         int
 564         default 50000000
 565
 566 config MAX_SCLK_HZ
 567         int
 568         default 133333333
 569
 570 config MIN_SCLK_HZ
 571         int
 572         default 27000000
 573
 574 comment "Kernel Timer/Scheduler"
 575
 576 source kernel/Kconfig.hz
 577
 578 config GENERIC_TIME
 579         bool "Generic time"
 580         depends on !SMP
 581         default y
 582
 583 config GENERIC_CLOCKEVENTS
 584         bool "Generic clock events"
 585         depends on GENERIC_TIME
 586         default y
 587
 588 config CYCLES_CLOCKSOURCE
 589         bool "Use 'CYCLES' as a clocksource (EXPERIMENTAL)"
 590         depends on EXPERIMENTAL
 591         depends on GENERIC_CLOCKEVENTS
 592         depends on !BFIN_SCRATCH_REG_CYCLES
 593         default n
 594         help
 595           If you say Y here, you will enable support for using the 'cycles'
 596           registers as a clock source.  Doing so means you will be unable to
 597           safely write to the 'cycles' register during runtime.  You will
 598           still be able to read it (such as for performance monitoring), but
 599           writing the registers will most likely crash the kernel.
 600
 601 source kernel/time/Kconfig
 602
 603 comment "Misc"
 604
 605 choice
 606         prompt "Blackfin Exception Scratch Register"
 607         default BFIN_SCRATCH_REG_RETN
 608         help
 609           Select the resource to reserve for the Exception handler:
 610             - RETN: Non-Maskable Interrupt (NMI)
 611             - RETE: Exception Return (JTAG/ICE)
 612             - CYCLES: Performance counter
 613
 614           If you are unsure, please select "RETN".
 615
 616 config BFIN_SCRATCH_REG_RETN
 617         bool "RETN"
 618         help
 619           Use the RETN register in the Blackfin exception handler
 620           as a stack scratch register.  This means you cannot
 621           safely use NMI on the Blackfin while running Linux, but
 622           you can debug the system with a JTAG ICE and use the
 623           CYCLES performance registers.
 624
 625           If you are unsure, please select "RETN".
 626
 627 config BFIN_SCRATCH_REG_RETE
 628         bool "RETE"
 629         help
 630           Use the RETE register in the Blackfin exception handler
 631           as a stack scratch register.  This means you cannot
 632           safely use a JTAG ICE while debugging a Blackfin board,
 633           but you can safely use the CYCLES performance registers
 634           and the NMI.
 635
 636           If you are unsure, please select "RETN".
 637
 638 config BFIN_SCRATCH_REG_CYCLES
 639         bool "CYCLES"
 640         help
 641           Use the CYCLES register in the Blackfin exception handler
 642           as a stack scratch register.  This means you cannot
 643           safely use the CYCLES performance registers on a Blackfin
 644           board at anytime, but you can debug the system with a JTAG
 645           ICE and use the NMI.
 646
 647           If you are unsure, please select "RETN".
 648
 649 endchoice
 650
 651 endmenu
 652
 653
 654 menu "Blackfin Kernel Optimizations"
 655         depends on !SMP
 656
 657 comment "Memory Optimizations"
 658
 659 config I_ENTRY_L1
 660         bool "Locate interrupt entry code in L1 Memory"
 661         default y
 662         help
 663           If enabled, interrupt entry code (STORE/RESTORE CONTEXT) is linked
 664           into L1 instruction memory. (less latency)
 665
 666 config EXCPT_IRQ_SYSC_L1
 667         bool "Locate entire ASM lowlevel exception / interrupt - Syscall and CPLB handler code in L1 Memory"
 668         default y
 669         help
 670           If enabled, the entire ASM lowlevel exception and interrupt entry code
 671           (STORE/RESTORE CONTEXT) is linked into L1 instruction memory.
 672           (less latency)
 673
 674 config DO_IRQ_L1
 675         bool "Locate frequently called do_irq dispatcher function in L1 Memory"
 676         default y
 677         help
 678           If enabled, the frequently called do_irq dispatcher function is linked
 679           into L1 instruction memory. (less latency)
 680
 681 config CORE_TIMER_IRQ_L1
 682         bool "Locate frequently called timer_interrupt() function in L1 Memory"
 683         default y
 684         help
 685           If enabled, the frequently called timer_interrupt() function is linked
 686           into L1 instruction memory. (less latency)
 687
 688 config IDLE_L1
 689         bool "Locate frequently idle function in L1 Memory"
 690         default y
 691         help
 692           If enabled, the frequently called idle function is linked
 693           into L1 instruction memory. (less latency)
 694
 695 config SCHEDULE_L1
 696         bool "Locate kernel schedule function in L1 Memory"
 697         default y
 698         help
 699           If enabled, the frequently called kernel schedule is linked
 700           into L1 instruction memory. (less latency)
 701
 702 config ARITHMETIC_OPS_L1
 703         bool "Locate kernel owned arithmetic functions in L1 Memory"
 704         default y
 705         help
 706           If enabled, arithmetic functions are linked
 707           into L1 instruction memory. (less latency)
 708
 709 config ACCESS_OK_L1
 710         bool "Locate access_ok function in L1 Memory"
 711         default y
 712         help
 713           If enabled, the access_ok function is linked
 714           into L1 instruction memory. (less latency)
 715
 716 config MEMSET_L1
 717         bool "Locate memset function in L1 Memory"
 718         default y
 719         help
 720           If enabled, the memset function is linked
 721           into L1 instruction memory. (less latency)
 722
 723 config MEMCPY_L1
 724         bool "Locate memcpy function in L1 Memory"
 725         default y
 726         help
 727           If enabled, the memcpy function is linked
 728           into L1 instruction memory. (less latency)
 729
 730 config SYS_BFIN_SPINLOCK_L1
 731         bool "Locate sys_bfin_spinlock function in L1 Memory"
 732         default y
 733         help
 734           If enabled, sys_bfin_spinlock function is linked
 735           into L1 instruction memory. (less latency)
 736
 737 config IP_CHECKSUM_L1
 738         bool "Locate IP Checksum function in L1 Memory"
 739         default n
 740         help
 741           If enabled, the IP Checksum function is linked
 742           into L1 instruction memory. (less latency)
 743
 744 config CACHELINE_ALIGNED_L1
 745         bool "Locate cacheline_aligned data to L1 Data Memory"
 746         default y if !BF54x
 747         default n if BF54x
 748         depends on !BF531
 749         help
 750           If enabled, cacheline_anligned data is linked
 751           into L1 data memory. (less latency)
 752
 753 config SYSCALL_TAB_L1
 754         bool "Locate Syscall Table L1 Data Memory"
 755         default n
 756         depends on !BF531
 757         help
 758           If enabled, the Syscall LUT is linked
 759           into L1 data memory. (less latency)
 760
 761 config CPLB_SWITCH_TAB_L1
 762         bool "Locate CPLB Switch Tables L1 Data Memory"
 763         default n
 764         depends on !BF531
 765         help
 766           If enabled, the CPLB Switch Tables are linked
 767           into L1 data memory. (less latency)
 768
 769 config APP_STACK_L1
 770         bool "Support locating application stack in L1 Scratch Memory"
 771         default y
 772         help
 773           If enabled the application stack can be located in L1
 774           scratch memory (less latency).
 775
 776           Currently only works with FLAT binaries.
 777
 778 config EXCEPTION_L1_SCRATCH
 779         bool "Locate exception stack in L1 Scratch Memory"
 780         default n
 781         depends on !APP_STACK_L1 && !SYSCALL_TAB_L1
 782         help
 783           Whenever an exception occurs, use the L1 Scratch memory for
 784           stack storage.  You cannot place the stacks of FLAT binaries
 785           in L1 when using this option.
 786
 787           If you don't use L1 Scratch, then you should say Y here.
 788
 789 comment "Speed Optimizations"
 790 config BFIN_INS_LOWOVERHEAD
 791         bool "ins[bwl] low overhead, higher interrupt latency"
 792         default y
 793         help
 794           Reads on the Blackfin are speculative. In Blackfin terms, this means
 795           they can be interrupted at any time (even after they have been issued
 796           on to the external bus), and re-issued after the interrupt occurs.
 797           For memory - this is not a big deal, since memory does not change if
 798           it sees a read.
 799
 800           If a FIFO is sitting on the end of the read, it will see two reads,
 801           when the core only sees one since the FIFO receives both the read
 802           which is cancelled (and not delivered to the core) and the one which
 803           is re-issued (which is delivered to the core).
 804
 805           To solve this, interrupts are turned off before reads occur to
 806           I/O space. This option controls which the overhead/latency of
 807           controlling interrupts during this time
 808            "n" turns interrupts off every read
 809                 (higher overhead, but lower interrupt latency)
 810            "y" turns interrupts off every loop
 811                 (low overhead, but longer interrupt latency)
 812
 813           default behavior is to leave this set to on (type "Y"). If you are experiencing
 814           interrupt latency issues, it is safe and OK to turn this off.
 815
 816 endmenu
 817
 818 choice
 819         prompt "Kernel executes from"
 820         help
 821           Choose the memory type that the kernel will be running in.
 822
 823 config RAMKERNEL
 824         bool "RAM"
 825         help
 826           The kernel will be resident in RAM when running.
 827
 828 config ROMKERNEL
 829         bool "ROM"
 830         help
 831           The kernel will be resident in FLASH/ROM when running.
 832
 833 endchoice
 834
 835 source "mm/Kconfig"
 836
 837 config BFIN_GPTIMERS
 838         tristate "Enable Blackfin General Purpose Timers API"
 839         default n
 840         help
 841           Enable support for the General Purpose Timers API.  If you
 842           are unsure, say N.
 843
 844           To compile this driver as a module, choose M here: the module
 845           will be called gptimers.ko.
 846
 847 choice
 848         prompt "Uncached DMA region"
 849         default DMA_UNCACHED_1M
 850 config DMA_UNCACHED_4M
 851         bool "Enable 4M DMA region"
 852 config DMA_UNCACHED_2M
 853         bool "Enable 2M DMA region"
 854 config DMA_UNCACHED_1M
 855         bool "Enable 1M DMA region"
 856 config DMA_UNCACHED_NONE
 857         bool "Disable DMA region"
 858 endchoice
 859
 860
 861 comment "Cache Support"
 862 config BFIN_ICACHE
 863         bool "Enable ICACHE"
 864 config BFIN_DCACHE
 865         bool "Enable DCACHE"
 866 config BFIN_DCACHE_BANKA
 867         bool "Enable only 16k BankA DCACHE - BankB is SRAM"
 868         depends on BFIN_DCACHE && !BF531
 869         default n
 870 config BFIN_ICACHE_LOCK
 871         bool "Enable Instruction Cache Locking"
 872
 873 choice
 874         prompt "Policy"
 875         depends on BFIN_DCACHE
 876         default BFIN_WB if !SMP
 877         default BFIN_WT if SMP
 878 config BFIN_WB
 879         bool "Write back"
 880         depends on !SMP
 881         help
 882           Write Back Policy:
 883             Cached data will be written back to SDRAM only when needed.
 884             This can give a nice increase in performance, but beware of
 885             broken drivers that do not properly invalidate/flush their
 886             cache.
 887
 888           Write Through Policy:
 889             Cached data will always be written back to SDRAM when the
 890             cache is updated.  This is a completely safe setting, but
 891             performance is worse than Write Back.
 892
 893           If you are unsure of the options and you want to be safe,
 894           then go with Write Through.
 895
 896 config BFIN_WT
 897         bool "Write through"
 898         help
 899           Write Back Policy:
 900             Cached data will be written back to SDRAM only when needed.
 901             This can give a nice increase in performance, but beware of
 902             broken drivers that do not properly invalidate/flush their
 903             cache.
 904
 905           Write Through Policy:
 906             Cached data will always be written back to SDRAM when the
 907             cache is updated.  This is a completely safe setting, but
 908             performance is worse than Write Back.
 909
 910           If you are unsure of the options and you want to be safe,
 911           then go with Write Through.
 912
 913 endchoice
 914
 915 config BFIN_L2_CACHEABLE
 916         bool "Cache L2 SRAM"
 917         depends on (BFIN_DCACHE || BFIN_ICACHE) && (BF54x || (BF561 && !SMP))
 918         default n
 919         help
 920           Select to make L2 SRAM cacheable in L1 data and instruction cache.
 921
 922 config MPU
 923         bool "Enable the memory protection unit (EXPERIMENTAL)"
 924         default n
 925         help
 926           Use the processor's MPU to protect applications from accessing
 927           memory they do not own.  This comes at a performance penalty
 928           and is recommended only for debugging.
 929
 930 comment "Asynchonous Memory Configuration"
 931
 932 menu "EBIU_AMGCTL Global Control"
 933 config C_AMCKEN
 934         bool "Enable CLKOUT"
 935         default y
 936
 937 config C_CDPRIO
 938         bool "DMA has priority over core for ext. accesses"
 939         default n
 940
 941 config C_B0PEN
 942         depends on BF561
 943         bool "Bank 0 16 bit packing enable"
 944         default y
 945
 946 config C_B1PEN
 947         depends on BF561
 948         bool "Bank 1 16 bit packing enable"
 949         default y
 950
 951 config C_B2PEN
 952         depends on BF561
 953         bool "Bank 2 16 bit packing enable"
 954         default y
 955
 956 config C_B3PEN
 957         depends on BF561
 958         bool "Bank 3 16 bit packing enable"
 959         default n
 960
 961 choice
 962         prompt"Enable Asynchonous Memory Banks"
 963         default C_AMBEN_ALL
 964
 965 config C_AMBEN
 966         bool "Disable All Banks"
 967
 968 config C_AMBEN_B0
 969         bool "Enable Bank 0"
 970
 971 config C_AMBEN_B0_B1
 972         bool "Enable Bank 0 & 1"
 973
 974 config C_AMBEN_B0_B1_B2
 975         bool "Enable Bank 0 & 1 & 2"
 976
 977 config C_AMBEN_ALL
 978         bool "Enable All Banks"
 979 endchoice
 980 endmenu
 981
 982 menu "EBIU_AMBCTL Control"
 983 config BANK_0
 984         hex "Bank 0"
 985         default 0x7BB0
 986
 987 config BANK_1
 988         hex "Bank 1"
 989         default 0x7BB0
 990         default 0x5558 if BF54x
 991
 992 config BANK_2
 993         hex "Bank 2"
 994         default 0x7BB0
 995
 996 config BANK_3
 997         hex "Bank 3"
 998         default 0x99B3
 999 endmenu
1000
1001 config EBIU_MBSCTLVAL
1002         hex "EBIU Bank Select Control Register"
1003         depends on BF54x
1004         default 0
1005
1006 config EBIU_MODEVAL
1007         hex "Flash Memory Mode Control Register"
1008         depends on BF54x
1009         default 1
1010
1011 config EBIU_FCTLVAL
1012         hex "Flash Memory Bank Control Register"
1013         depends on BF54x
1014         default 6
1015 endmenu
1016
1017 #############################################################################
1018 menu "Bus options (PCI, PCMCIA, EISA, MCA, ISA)"
1019
1020 config PCI
1021         bool "PCI support"
1022         depends on BROKEN
1023         help
1024           Support for PCI bus.
1025
1026 source "drivers/pci/Kconfig"
1027
1028 config HOTPLUG
1029         bool "Support for hot-pluggable device"
1030           help
1031           Say Y here if you want to plug devices into your computer while
1032           the system is running, and be able to use them quickly.  In many
1033           cases, the devices can likewise be unplugged at any time too.
1034
1035           One well known example of this is PCMCIA- or PC-cards, credit-card
1036           size devices such as network cards, modems or hard drives which are
1037           plugged into slots found on all modern laptop computers.  Another
1038           example, used on modern desktops as well as laptops, is USB.
1039
1040           Enable HOTPLUG and build a modular kernel.  Get agent software
1041           (from <http://linux-hotplug.sourceforge.net/>) and install it.
1042           Then your kernel will automatically call out to a user mode "policy
1043           agent" (/sbin/hotplug) to load modules and set up software needed
1044           to use devices as you hotplug them.
1045
1046 source "drivers/pcmcia/Kconfig"
1047
1048 source "drivers/pci/hotplug/Kconfig"
1049
1050 endmenu
1051
1052 menu "Executable file formats"
1053
1054 source "fs/Kconfig.binfmt"
1055
1056 endmenu
1057
1058 menu "Power management options"
1059 source "kernel/power/Kconfig"
1060
1061 config ARCH_SUSPEND_POSSIBLE
1062         def_bool y
1063         depends on !SMP
1064
1065 choice
1066         prompt "Standby Power Saving Mode"
1067         depends on PM
1068         default PM_BFIN_SLEEP_DEEPER
1069 config  PM_BFIN_SLEEP_DEEPER
1070         bool "Sleep Deeper"
1071         help
1072           Sleep "Deeper" Mode (High Power Savings) - This mode reduces dynamic
1073           power dissipation by disabling the clock to the processor core (CCLK).
1074           Furthermore, Standby sets the internal power supply voltage (VDDINT)
1075           to 0.85 V to provide the greatest power savings, while preserving the
1076           processor state.
1077           The PLL and system clock (SCLK) continue to operate at a very low
1078           frequency of about 3.3 MHz. To preserve data integrity in the SDRAM,
1079           the SDRAM is put into Self Refresh Mode. Typically an external event
1080           such as GPIO interrupt or RTC activity wakes up the processor.
1081           Various Peripherals such as UART, SPORT, PPI may not function as
1082           normal during Sleep Deeper, due to the reduced SCLK frequency.
1083           When in the sleep mode, system DMA access to L1 memory is not supported.
1084
1085           If unsure, select "Sleep Deeper".
1086
1087 config  PM_BFIN_SLEEP
1088         bool "Sleep"
1089         help
1090           Sleep Mode (High Power Savings) - The sleep mode reduces power
1091           dissipation by disabling the clock to the processor core (CCLK).
1092           The PLL and system clock (SCLK), however, continue to operate in
1093           this mode. Typically an external event or RTC activity will wake
1094           up the processor. When in the sleep mode, system DMA access to L1
1095           memory is not supported.
1096
1097           If unsure, select "Sleep Deeper".
1098 endchoice
1099
1100 config PM_WAKEUP_BY_GPIO
1101         bool "Allow Wakeup from Standby by GPIO"
1102
1103 config PM_WAKEUP_GPIO_NUMBER
1104         int "GPIO number"
1105         range 0 47
1106         depends on PM_WAKEUP_BY_GPIO
1107         default 2
1108
1109 choice
1110         prompt "GPIO Polarity"
1111         depends on PM_WAKEUP_BY_GPIO
1112         default PM_WAKEUP_GPIO_POLAR_H
1113 config  PM_WAKEUP_GPIO_POLAR_H
1114         bool "Active High"
1115 config  PM_WAKEUP_GPIO_POLAR_L
1116         bool "Active Low"
1117 config  PM_WAKEUP_GPIO_POLAR_EDGE_F
1118         bool "Falling EDGE"
1119 config  PM_WAKEUP_GPIO_POLAR_EDGE_R
1120         bool "Rising EDGE"
1121 config  PM_WAKEUP_GPIO_POLAR_EDGE_B
1122         bool "Both EDGE"
1123 endchoice
1124
1125 comment "Possible Suspend Mem / Hibernate Wake-Up Sources"
1126         depends on PM
1127
1128 config PM_BFIN_WAKE_PH6
1129         bool "Allow Wake-Up from on-chip PHY or PH6 GP"
1130         depends on PM && (BF51x || BF52x || BF534 || BF536 || BF537)
1131         default n
1132         help
1133           Enable PHY and PH6 GP Wake-Up (Voltage Regulator Power-Up)
1134
1135 config PM_BFIN_WAKE_GP
1136         bool "Allow Wake-Up from GPIOs"
1137         depends on PM && BF54x
1138         default n
1139         help
1140           Enable General-Purpose Wake-Up (Voltage Regulator Power-Up)
1141 endmenu
1142
1143 menu "CPU Frequency scaling"
1144
1145 source "drivers/cpufreq/Kconfig"
1146
1147 config BFIN_CPU_FREQ
1148         bool
1149         depends on CPU_FREQ
1150         select CPU_FREQ_TABLE
1151         default y
1152
1153 config CPU_VOLTAGE
1154         bool "CPU Voltage scaling"
1155         depends on EXPERIMENTAL
1156         depends on CPU_FREQ
1157         default n
1158         help
1159           Say Y here if you want CPU voltage scaling according to the CPU frequency.
1160           This option violates the PLL BYPASS recommendation in the Blackfin Processor
1161           manuals. There is a theoretical risk that during VDDINT transitions
1162           the PLL may unlock.
1163
1164 endmenu
1165
1166 source "net/Kconfig"
1167
1168 source "drivers/Kconfig"
1169
1170 source "fs/Kconfig"
1171
1172 source "arch/blackfin/Kconfig.debug"
1173
1174 source "security/Kconfig"
1175
1176 source "crypto/Kconfig"
1177
1178 source "lib/Kconfig"