arch/blackfin/Kconfig

   1 #
   2 # For a description of the syntax of this configuration file,
   3 # see Documentation/kbuild/kconfig-language.txt.
   4 #
   5
   6 mainmenu "Blackfin Kernel Configuration"
   7
   8 config MMU
   9         bool
  10         default n
  11
  12 config FPU
  13         bool
  14         default n
  15
  16 config RWSEM_GENERIC_SPINLOCK
  17         bool
  18         default y
  19
  20 config RWSEM_XCHGADD_ALGORITHM
  21         bool
  22         default n
  23
  24 config BLACKFIN
  25         bool
  26         default y
  27         select HAVE_IDE
  28         select HAVE_OPROFILE
  29         select ARCH_WANT_OPTIONAL_GPIOLIB
  30
  31 config ZONE_DMA
  32         bool
  33         default y
  34
  35 config GENERIC_FIND_NEXT_BIT
  36         bool
  37         default y
  38
  39 config GENERIC_HWEIGHT
  40         bool
  41         default y
  42
  43 config GENERIC_HARDIRQS
  44         bool
  45         default y
  46
  47 config GENERIC_IRQ_PROBE
  48         bool
  49         default y
  50
  51 config GENERIC_GPIO
  52         bool
  53         default y
  54
  55 config FORCE_MAX_ZONEORDER
  56         int
  57         default "14"
  58
  59 config GENERIC_CALIBRATE_DELAY
  60         bool
  61         default y
  62
  63 source "init/Kconfig"
  64
  65 source "kernel/Kconfig.preempt"
  66
  67 source "kernel/Kconfig.freezer"
  68
  69 menu "Blackfin Processor Options"
  70
  71 comment "Processor and Board Settings"
  72
  73 choice
  74         prompt "CPU"
  75         default BF533
  76
  77 config BF512
  78         bool "BF512"
  79         help
  80           BF512 Processor Support.
  81
  82 config BF514
  83         bool "BF514"
  84         help
  85           BF514 Processor Support.
  86
  87 config BF516
  88         bool "BF516"
  89         help
  90           BF516 Processor Support.
  91
  92 config BF518
  93         bool "BF518"
  94         help
  95           BF518 Processor Support.
  96
  97 config BF522
  98         bool "BF522"
  99         help
 100           BF522 Processor Support.
 101
 102 config BF523
 103         bool "BF523"
 104         help
 105           BF523 Processor Support.
 106
 107 config BF524
 108         bool "BF524"
 109         help
 110           BF524 Processor Support.
 111
 112 config BF525
 113         bool "BF525"
 114         help
 115           BF525 Processor Support.
 116
 117 config BF526
 118         bool "BF526"
 119         help
 120           BF526 Processor Support.
 121
 122 config BF527
 123         bool "BF527"
 124         help
 125           BF527 Processor Support.
 126
 127 config BF531
 128         bool "BF531"
 129         help
 130           BF531 Processor Support.
 131
 132 config BF532
 133         bool "BF532"
 134         help
 135           BF532 Processor Support.
 136
 137 config BF533
 138         bool "BF533"
 139         help
 140           BF533 Processor Support.
 141
 142 config BF534
 143         bool "BF534"
 144         help
 145           BF534 Processor Support.
 146
 147 config BF536
 148         bool "BF536"
 149         help
 150           BF536 Processor Support.
 151
 152 config BF537
 153         bool "BF537"
 154         help
 155           BF537 Processor Support.
 156
 157 config BF538
 158         bool "BF538"
 159         help
 160           BF538 Processor Support.
 161
 162 config BF539
 163         bool "BF539"
 164         help
 165           BF539 Processor Support.
 166
 167 config BF542
 168         bool "BF542"
 169         help
 170           BF542 Processor Support.
 171
 172 config BF544
 173         bool "BF544"
 174         help
 175           BF544 Processor Support.
 176
 177 config BF547
 178         bool "BF547"
 179         help
 180           BF547 Processor Support.
 181
 182 config BF548
 183         bool "BF548"
 184         help
 185           BF548 Processor Support.
 186
 187 config BF549
 188         bool "BF549"
 189         help
 190           BF549 Processor Support.
 191
 192 config BF561
 193         bool "BF561"
 194         help
 195           BF561 Processor Support.
 196
 197 endchoice
 198
 199 config SMP
 200         depends on BF561
 201         bool "Symmetric multi-processing support"
 202         ---help---
 203           This enables support for systems with more than one CPU,
 204           like the dual core BF561. If you have a system with only one
 205           CPU, say N. If you have a system with more than one CPU, say Y.
 206
 207           If you don't know what to do here, say N.
 208
 209 config NR_CPUS
 210         int
 211         depends on SMP
 212         default 2 if BF561
 213
 214 config IRQ_PER_CPU
 215         bool
 216         depends on SMP
 217         default y
 218
 219 config TICK_SOURCE_SYSTMR0
 220         bool
 221         select BFIN_GPTIMERS
 222         depends on SMP
 223         default y
 224
 225 config BF_REV_MIN
 226         int
 227         default 0 if (BF51x || BF52x || BF54x)
 228         default 2 if (BF537 || BF536 || BF534)
 229         default 3 if (BF561 ||BF533 || BF532 || BF531)
 230         default 4 if (BF538 || BF539)
 231
 232 config BF_REV_MAX
 233         int
 234         default 2 if (BF51x || BF52x || BF54x)
 235         default 3 if (BF537 || BF536 || BF534)
 236         default 5 if (BF561 || BF538 || BF539)
 237         default 6 if (BF533 || BF532 || BF531)
 238
 239 choice
 240         prompt "Silicon Rev"
 241         default BF_REV_0_1 if (BF51x || BF52x || BF54x)
 242         default BF_REV_0_2 if (BF534 || BF536 || BF537)
 243         default BF_REV_0_3 if (BF531 || BF532 || BF533 || BF561)
 244
 245 config BF_REV_0_0
 246         bool "0.0"
 247         depends on (BF51x || BF52x || BF54x)
 248
 249 config BF_REV_0_1
 250         bool "0.1"
 251         depends on (BF52x || BF54x)
 252
 253 config BF_REV_0_2
 254         bool "0.2"
 255         depends on (BF52x || BF537 || BF536 || BF534 || BF54x)
 256
 257 config BF_REV_0_3
 258         bool "0.3"
 259         depends on (BF561 || BF537 || BF536 || BF534 || BF533 || BF532 || BF531)
 260
 261 config BF_REV_0_4
 262         bool "0.4"
 263         depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539)
 264
 265 config BF_REV_0_5
 266         bool "0.5"
 267         depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539)
 268
 269 config BF_REV_0_6
 270         bool "0.6"
 271         depends on (BF533 || BF532 || BF531)
 272
 273 config BF_REV_ANY
 274         bool "any"
 275
 276 config BF_REV_NONE
 277         bool "none"
 278
 279 endchoice
 280
 281 config BF51x
 282         bool
 283         depends on (BF512 || BF514 || BF516 || BF518)
 284         default y
 285
 286 config BF52x
 287         bool
 288         depends on (BF522 || BF523 || BF524 || BF525 || BF526 || BF527)
 289         default y
 290
 291 config BF53x
 292         bool
 293         depends on (BF531 || BF532 || BF533 || BF534 || BF536 || BF537)
 294         default y
 295
 296 config BF54x
 297         bool
 298         depends on (BF542 || BF544 || BF547 || BF548 || BF549)
 299         default y
 300
 301 config MEM_GENERIC_BOARD
 302         bool
 303         depends on GENERIC_BOARD
 304         default y
 305
 306 config MEM_MT48LC64M4A2FB_7E
 307         bool
 308         depends on (BFIN533_STAMP)
 309         default y
 310
 311 config MEM_MT48LC16M16A2TG_75
 312         bool
 313         depends on (BFIN533_EZKIT || BFIN561_EZKIT \
 314                 || BFIN533_BLUETECHNIX_CM || BFIN537_BLUETECHNIX_CM \
 315                 || H8606_HVSISTEMAS || BFIN527_BLUETECHNIX_CM)
 316         default y
 317
 318 config MEM_MT48LC32M8A2_75
 319         bool
 320         depends on (BFIN537_STAMP || PNAV10 || BFIN538_EZKIT)
 321         default y
 322
 323 config MEM_MT48LC8M32B2B5_7
 324         bool
 325         depends on (BFIN561_BLUETECHNIX_CM)
 326         default y
 327
 328 config MEM_MT48LC32M16A2TG_75
 329         bool
 330         depends on (BFIN527_EZKIT || BFIN532_IP0X || BLACKSTAMP || BFIN526_EZBRD)
 331         default y
 332
 333 source "arch/blackfin/mach-bf518/Kconfig"
 334 source "arch/blackfin/mach-bf527/Kconfig"
 335 source "arch/blackfin/mach-bf533/Kconfig"
 336 source "arch/blackfin/mach-bf561/Kconfig"
 337 source "arch/blackfin/mach-bf537/Kconfig"
 338 source "arch/blackfin/mach-bf538/Kconfig"
 339 source "arch/blackfin/mach-bf548/Kconfig"
 340
 341 menu "Board customizations"
 342
 343 config CMDLINE_BOOL
 344         bool "Default bootloader kernel arguments"
 345
 346 config CMDLINE
 347         string "Initial kernel command string"
 348         depends on CMDLINE_BOOL
 349         default "console=ttyBF0,57600"
 350         help
 351           If you don't have a boot loader capable of passing a command line string
 352           to the kernel, you may specify one here. As a minimum, you should specify
 353           the memory size and the root device (e.g., mem=8M, root=/dev/nfs).
 354
 355 config BOOT_LOAD
 356         hex "Kernel load address for booting"
 357         default "0x1000"
 358         range 0x1000 0x20000000
 359         help
 360           This option allows you to set the load address of the kernel.
 361           This can be useful if you are on a board which has a small amount
 362           of memory or you wish to reserve some memory at the beginning of
 363           the address space.
 364
 365           Note that you need to keep this value above 4k (0x1000) as this
 366           memory region is used to capture NULL pointer references as well
 367           as some core kernel functions.
 368
 369 config ROM_BASE
 370         hex "Kernel ROM Base"
 371         depends on ROMKERNEL
 372         default "0x20040000"
 373         range 0x20000000 0x20400000 if !(BF54x || BF561)
 374         range 0x20000000 0x30000000 if (BF54x || BF561)
 375         help
 376
 377 comment "Clock/PLL Setup"
 378
 379 config CLKIN_HZ
 380         int "Frequency of the crystal on the board in Hz"
 381         default "11059200" if BFIN533_STAMP
 382         default "27000000" if BFIN533_EZKIT
 383         default "25000000" if (BFIN537_STAMP || BFIN527_EZKIT || H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD || BFIN538_EZKIT || BFIN518F-EZBRD)
 384         default "30000000" if BFIN561_EZKIT
 385         default "24576000" if PNAV10
 386         default "10000000" if BFIN532_IP0X
 387         help
 388           The frequency of CLKIN crystal oscillator on the board in Hz.
 389           Warning: This value should match the crystal on the board. Otherwise,
 390           peripherals won't work properly.
 391
 392 config BFIN_KERNEL_CLOCK
 393         bool "Re-program Clocks while Kernel boots?"
 394         default n
 395         help
 396           This option decides if kernel clocks are re-programed from the
 397           bootloader settings. If the clocks are not set, the SDRAM settings
 398           are also not changed, and the Bootloader does 100% of the hardware
 399           configuration.
 400
 401 config PLL_BYPASS
 402         bool "Bypass PLL"
 403         depends on BFIN_KERNEL_CLOCK
 404         default n
 405
 406 config CLKIN_HALF
 407         bool "Half Clock In"
 408         depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
 409         default n
 410         help
 411           If this is set the clock will be divided by 2, before it goes to the PLL.
 412
 413 config VCO_MULT
 414         int "VCO Multiplier"
 415         depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
 416         range 1 64
 417         default "22" if BFIN533_EZKIT
 418         default "45" if BFIN533_STAMP
 419         default "20" if (BFIN537_STAMP || BFIN527_EZKIT || BFIN548_EZKIT || BFIN548_BLUETECHNIX_CM || BFIN538_EZKIT)
 420         default "22" if BFIN533_BLUETECHNIX_CM
 421         default "20" if (BFIN537_BLUETECHNIX_CM || BFIN527_BLUETECHNIX_CM || BFIN561_BLUETECHNIX_CM)
 422         default "20" if BFIN561_EZKIT
 423         default "16" if (H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD || BFIN518F_EZBRD)
 424         help
 425           This controls the frequency of the on-chip PLL. This can be between 1 and 64.
 426           PLL Frequency = (Crystal Frequency) * (this setting)
 427
 428 choice
 429         prompt "Core Clock Divider"
 430         depends on BFIN_KERNEL_CLOCK
 431         default CCLK_DIV_1
 432         help
 433           This sets the frequency of the core. It can be 1, 2, 4 or 8
 434           Core Frequency = (PLL frequency) / (this setting)
 435
 436 config CCLK_DIV_1
 437         bool "1"
 438
 439 config CCLK_DIV_2
 440         bool "2"
 441
 442 config CCLK_DIV_4
 443         bool "4"
 444
 445 config CCLK_DIV_8
 446         bool "8"
 447 endchoice
 448
 449 config SCLK_DIV
 450         int "System Clock Divider"
 451         depends on BFIN_KERNEL_CLOCK
 452         range 1 15
 453         default 5
 454         help
 455           This sets the frequency of the system clock (including SDRAM or DDR).
 456           This can be between 1 and 15
 457           System Clock = (PLL frequency) / (this setting)
 458
 459 choice
 460         prompt "DDR SDRAM Chip Type"
 461         depends on BFIN_KERNEL_CLOCK
 462         depends on BF54x
 463         default MEM_MT46V32M16_5B
 464
 465 config MEM_MT46V32M16_6T
 466         bool "MT46V32M16_6T"
 467
 468 config MEM_MT46V32M16_5B
 469         bool "MT46V32M16_5B"
 470 endchoice
 471
 472 choice
 473         prompt "DDR/SDRAM Timing"
 474         depends on BFIN_KERNEL_CLOCK
 475         default BFIN_KERNEL_CLOCK_MEMINIT_CALC
 476         help
 477           This option allows you to specify Blackfin SDRAM/DDR Timing parameters
 478           The calculated SDRAM timing parameters may not be 100%
 479           accurate - This option is therefore marked experimental.
 480
 481 config BFIN_KERNEL_CLOCK_MEMINIT_CALC
 482         bool "Calculate Timings (EXPERIMENTAL)"
 483         depends on EXPERIMENTAL
 484
 485 config BFIN_KERNEL_CLOCK_MEMINIT_SPEC
 486         bool "Provide accurate Timings based on target SCLK"
 487         help
 488           Please consult the Blackfin Hardware Reference Manuals as well
 489           as the memory device datasheet.
 490           http://docs.blackfin.uclinux.org/doku.php?id=bfin:sdram
 491 endchoice
 492
 493 menu "Memory Init Control"
 494         depends on BFIN_KERNEL_CLOCK_MEMINIT_SPEC
 495
 496 config MEM_DDRCTL0
 497         depends on BF54x
 498         hex "DDRCTL0"
 499         default 0x0
 500
 501 config MEM_DDRCTL1
 502         depends on BF54x
 503         hex "DDRCTL1"
 504         default 0x0
 505
 506 config MEM_DDRCTL2
 507         depends on BF54x
 508         hex "DDRCTL2"
 509         default 0x0
 510
 511 config MEM_EBIU_DDRQUE
 512         depends on BF54x
 513         hex "DDRQUE"
 514         default 0x0
 515
 516 config MEM_SDRRC
 517         depends on !BF54x
 518         hex "SDRRC"
 519         default 0x0
 520
 521 config MEM_SDGCTL
 522         depends on !BF54x
 523         hex "SDGCTL"
 524         default 0x0
 525 endmenu
 526
 527 config MAX_MEM_SIZE
 528         int "Max SDRAM Memory Size in MBytes"
 529         depends on !MPU
 530         default 512
 531         help
 532           This is the max memory size that the kernel will create CPLB
 533           tables for.  Your system will not be able to handle any more.
 534
 535 #
 536 # Max & Min Speeds for various Chips
 537 #
 538 config MAX_VCO_HZ
 539         int
 540         default 400000000 if BF512
 541         default 400000000 if BF514
 542         default 400000000 if BF516
 543         default 400000000 if BF518
 544         default 600000000 if BF522
 545         default 400000000 if BF523
 546         default 400000000 if BF524
 547         default 600000000 if BF525
 548         default 400000000 if BF526
 549         default 600000000 if BF527
 550         default 400000000 if BF531
 551         default 400000000 if BF532
 552         default 750000000 if BF533
 553         default 500000000 if BF534
 554         default 400000000 if BF536
 555         default 600000000 if BF537
 556         default 533333333 if BF538
 557         default 533333333 if BF539
 558         default 600000000 if BF542
 559         default 533333333 if BF544
 560         default 600000000 if BF547
 561         default 600000000 if BF548
 562         default 533333333 if BF549
 563         default 600000000 if BF561
 564
 565 config MIN_VCO_HZ
 566         int
 567         default 50000000
 568
 569 config MAX_SCLK_HZ
 570         int
 571         default 133333333
 572
 573 config MIN_SCLK_HZ
 574         int
 575         default 27000000
 576
 577 comment "Kernel Timer/Scheduler"
 578
 579 source kernel/Kconfig.hz
 580
 581 config GENERIC_TIME
 582         bool "Generic time"
 583         depends on !SMP
 584         default y
 585
 586 config GENERIC_CLOCKEVENTS
 587         bool "Generic clock events"
 588         depends on GENERIC_TIME
 589         default y
 590
 591 config CYCLES_CLOCKSOURCE
 592         bool "Use 'CYCLES' as a clocksource (EXPERIMENTAL)"
 593         depends on EXPERIMENTAL
 594         depends on GENERIC_CLOCKEVENTS
 595         depends on !BFIN_SCRATCH_REG_CYCLES
 596         default n
 597         help
 598           If you say Y here, you will enable support for using the 'cycles'
 599           registers as a clock source.  Doing so means you will be unable to
 600           safely write to the 'cycles' register during runtime.  You will
 601           still be able to read it (such as for performance monitoring), but
 602           writing the registers will most likely crash the kernel.
 603
 604 source kernel/time/Kconfig
 605
 606 comment "Misc"
 607
 608 choice
 609         prompt "Blackfin Exception Scratch Register"
 610         default BFIN_SCRATCH_REG_RETN
 611         help
 612           Select the resource to reserve for the Exception handler:
 613             - RETN: Non-Maskable Interrupt (NMI)
 614             - RETE: Exception Return (JTAG/ICE)
 615             - CYCLES: Performance counter
 616
 617           If you are unsure, please select "RETN".
 618
 619 config BFIN_SCRATCH_REG_RETN
 620         bool "RETN"
 621         help
 622           Use the RETN register in the Blackfin exception handler
 623           as a stack scratch register.  This means you cannot
 624           safely use NMI on the Blackfin while running Linux, but
 625           you can debug the system with a JTAG ICE and use the
 626           CYCLES performance registers.
 627
 628           If you are unsure, please select "RETN".
 629
 630 config BFIN_SCRATCH_REG_RETE
 631         bool "RETE"
 632         help
 633           Use the RETE register in the Blackfin exception handler
 634           as a stack scratch register.  This means you cannot
 635           safely use a JTAG ICE while debugging a Blackfin board,
 636           but you can safely use the CYCLES performance registers
 637           and the NMI.
 638
 639           If you are unsure, please select "RETN".
 640
 641 config BFIN_SCRATCH_REG_CYCLES
 642         bool "CYCLES"
 643         help
 644           Use the CYCLES register in the Blackfin exception handler
 645           as a stack scratch register.  This means you cannot
 646           safely use the CYCLES performance registers on a Blackfin
 647           board at anytime, but you can debug the system with a JTAG
 648           ICE and use the NMI.
 649
 650           If you are unsure, please select "RETN".
 651
 652 endchoice
 653
 654 endmenu
 655
 656
 657 menu "Blackfin Kernel Optimizations"
 658         depends on !SMP
 659
 660 comment "Memory Optimizations"
 661
 662 config I_ENTRY_L1
 663         bool "Locate interrupt entry code in L1 Memory"
 664         default y
 665         help
 666           If enabled, interrupt entry code (STORE/RESTORE CONTEXT) is linked
 667           into L1 instruction memory. (less latency)
 668
 669 config EXCPT_IRQ_SYSC_L1
 670         bool "Locate entire ASM lowlevel exception / interrupt - Syscall and CPLB handler code in L1 Memory"
 671         default y
 672         help
 673           If enabled, the entire ASM lowlevel exception and interrupt entry code
 674           (STORE/RESTORE CONTEXT) is linked into L1 instruction memory.
 675           (less latency)
 676
 677 config DO_IRQ_L1
 678         bool "Locate frequently called do_irq dispatcher function in L1 Memory"
 679         default y
 680         help
 681           If enabled, the frequently called do_irq dispatcher function is linked
 682           into L1 instruction memory. (less latency)
 683
 684 config CORE_TIMER_IRQ_L1
 685         bool "Locate frequently called timer_interrupt() function in L1 Memory"
 686         default y
 687         help
 688           If enabled, the frequently called timer_interrupt() function is linked
 689           into L1 instruction memory. (less latency)
 690
 691 config IDLE_L1
 692         bool "Locate frequently idle function in L1 Memory"
 693         default y
 694         help
 695           If enabled, the frequently called idle function is linked
 696           into L1 instruction memory. (less latency)
 697
 698 config SCHEDULE_L1
 699         bool "Locate kernel schedule function in L1 Memory"
 700         default y
 701         help
 702           If enabled, the frequently called kernel schedule is linked
 703           into L1 instruction memory. (less latency)
 704
 705 config ARITHMETIC_OPS_L1
 706         bool "Locate kernel owned arithmetic functions in L1 Memory"
 707         default y
 708         help
 709           If enabled, arithmetic functions are linked
 710           into L1 instruction memory. (less latency)
 711
 712 config ACCESS_OK_L1
 713         bool "Locate access_ok function in L1 Memory"
 714         default y
 715         help
 716           If enabled, the access_ok function is linked
 717           into L1 instruction memory. (less latency)
 718
 719 config MEMSET_L1
 720         bool "Locate memset function in L1 Memory"
 721         default y
 722         help
 723           If enabled, the memset function is linked
 724           into L1 instruction memory. (less latency)
 725
 726 config MEMCPY_L1
 727         bool "Locate memcpy function in L1 Memory"
 728         default y
 729         help
 730           If enabled, the memcpy function is linked
 731           into L1 instruction memory. (less latency)
 732
 733 config SYS_BFIN_SPINLOCK_L1
 734         bool "Locate sys_bfin_spinlock function in L1 Memory"
 735         default y
 736         help
 737           If enabled, sys_bfin_spinlock function is linked
 738           into L1 instruction memory. (less latency)
 739
 740 config IP_CHECKSUM_L1
 741         bool "Locate IP Checksum function in L1 Memory"
 742         default n
 743         help
 744           If enabled, the IP Checksum function is linked
 745           into L1 instruction memory. (less latency)
 746
 747 config CACHELINE_ALIGNED_L1
 748         bool "Locate cacheline_aligned data to L1 Data Memory"
 749         default y if !BF54x
 750         default n if BF54x
 751         depends on !BF531
 752         help
 753           If enabled, cacheline_anligned data is linked
 754           into L1 data memory. (less latency)
 755
 756 config SYSCALL_TAB_L1
 757         bool "Locate Syscall Table L1 Data Memory"
 758         default n
 759         depends on !BF531
 760         help
 761           If enabled, the Syscall LUT is linked
 762           into L1 data memory. (less latency)
 763
 764 config CPLB_SWITCH_TAB_L1
 765         bool "Locate CPLB Switch Tables L1 Data Memory"
 766         default n
 767         depends on !BF531
 768         help
 769           If enabled, the CPLB Switch Tables are linked
 770           into L1 data memory. (less latency)
 771
 772 config APP_STACK_L1
 773         bool "Support locating application stack in L1 Scratch Memory"
 774         default y
 775         help
 776           If enabled the application stack can be located in L1
 777           scratch memory (less latency).
 778
 779           Currently only works with FLAT binaries.
 780
 781 config EXCEPTION_L1_SCRATCH
 782         bool "Locate exception stack in L1 Scratch Memory"
 783         default n
 784         depends on !APP_STACK_L1 && !SYSCALL_TAB_L1
 785         help
 786           Whenever an exception occurs, use the L1 Scratch memory for
 787           stack storage.  You cannot place the stacks of FLAT binaries
 788           in L1 when using this option.
 789
 790           If you don't use L1 Scratch, then you should say Y here.
 791
 792 comment "Speed Optimizations"
 793 config BFIN_INS_LOWOVERHEAD
 794         bool "ins[bwl] low overhead, higher interrupt latency"
 795         default y
 796         help
 797           Reads on the Blackfin are speculative. In Blackfin terms, this means
 798           they can be interrupted at any time (even after they have been issued
 799           on to the external bus), and re-issued after the interrupt occurs.
 800           For memory - this is not a big deal, since memory does not change if
 801           it sees a read.
 802
 803           If a FIFO is sitting on the end of the read, it will see two reads,
 804           when the core only sees one since the FIFO receives both the read
 805           which is cancelled (and not delivered to the core) and the one which
 806           is re-issued (which is delivered to the core).
 807
 808           To solve this, interrupts are turned off before reads occur to
 809           I/O space. This option controls which the overhead/latency of
 810           controlling interrupts during this time
 811            "n" turns interrupts off every read
 812                 (higher overhead, but lower interrupt latency)
 813            "y" turns interrupts off every loop
 814                 (low overhead, but longer interrupt latency)
 815
 816           default behavior is to leave this set to on (type "Y"). If you are experiencing
 817           interrupt latency issues, it is safe and OK to turn this off.
 818
 819 endmenu
 820
 821 choice
 822         prompt "Kernel executes from"
 823         help
 824           Choose the memory type that the kernel will be running in.
 825
 826 config RAMKERNEL
 827         bool "RAM"
 828         help
 829           The kernel will be resident in RAM when running.
 830
 831 config ROMKERNEL
 832         bool "ROM"
 833         help
 834           The kernel will be resident in FLASH/ROM when running.
 835
 836 endchoice
 837
 838 source "mm/Kconfig"
 839
 840 config BFIN_GPTIMERS
 841         tristate "Enable Blackfin General Purpose Timers API"
 842         default n
 843         help
 844           Enable support for the General Purpose Timers API.  If you
 845           are unsure, say N.
 846
 847           To compile this driver as a module, choose M here: the module
 848           will be called gptimers.ko.
 849
 850 choice
 851         prompt "Uncached DMA region"
 852         default DMA_UNCACHED_1M
 853 config DMA_UNCACHED_4M
 854         bool "Enable 4M DMA region"
 855 config DMA_UNCACHED_2M
 856         bool "Enable 2M DMA region"
 857 config DMA_UNCACHED_1M
 858         bool "Enable 1M DMA region"
 859 config DMA_UNCACHED_NONE
 860         bool "Disable DMA region"
 861 endchoice
 862
 863
 864 comment "Cache Support"
 865 config BFIN_ICACHE
 866         bool "Enable ICACHE"
 867 config BFIN_DCACHE
 868         bool "Enable DCACHE"
 869 config BFIN_DCACHE_BANKA
 870         bool "Enable only 16k BankA DCACHE - BankB is SRAM"
 871         depends on BFIN_DCACHE && !BF531
 872         default n
 873 config BFIN_ICACHE_LOCK
 874         bool "Enable Instruction Cache Locking"
 875
 876 choice
 877         prompt "Policy"
 878         depends on BFIN_DCACHE
 879         default BFIN_WB if !SMP
 880         default BFIN_WT if SMP
 881 config BFIN_WB
 882         bool "Write back"
 883         depends on !SMP
 884         help
 885           Write Back Policy:
 886             Cached data will be written back to SDRAM only when needed.
 887             This can give a nice increase in performance, but beware of
 888             broken drivers that do not properly invalidate/flush their
 889             cache.
 890
 891           Write Through Policy:
 892             Cached data will always be written back to SDRAM when the
 893             cache is updated.  This is a completely safe setting, but
 894             performance is worse than Write Back.
 895
 896           If you are unsure of the options and you want to be safe,
 897           then go with Write Through.
 898
 899 config BFIN_WT
 900         bool "Write through"
 901         help
 902           Write Back Policy:
 903             Cached data will be written back to SDRAM only when needed.
 904             This can give a nice increase in performance, but beware of
 905             broken drivers that do not properly invalidate/flush their
 906             cache.
 907
 908           Write Through Policy:
 909             Cached data will always be written back to SDRAM when the
 910             cache is updated.  This is a completely safe setting, but
 911             performance is worse than Write Back.
 912
 913           If you are unsure of the options and you want to be safe,
 914           then go with Write Through.
 915
 916 endchoice
 917
 918 config BFIN_L2_CACHEABLE
 919         bool "Cache L2 SRAM"
 920         depends on (BFIN_DCACHE || BFIN_ICACHE) && (BF54x || (BF561 && !SMP))
 921         default n
 922         help
 923           Select to make L2 SRAM cacheable in L1 data and instruction cache.
 924
 925 config MPU
 926         bool "Enable the memory protection unit (EXPERIMENTAL)"
 927         default n
 928         help
 929           Use the processor's MPU to protect applications from accessing
 930           memory they do not own.  This comes at a performance penalty
 931           and is recommended only for debugging.
 932
 933 comment "Asynchonous Memory Configuration"
 934
 935 menu "EBIU_AMGCTL Global Control"
 936 config C_AMCKEN
 937         bool "Enable CLKOUT"
 938         default y
 939
 940 config C_CDPRIO
 941         bool "DMA has priority over core for ext. accesses"
 942         default n
 943
 944 config C_B0PEN
 945         depends on BF561
 946         bool "Bank 0 16 bit packing enable"
 947         default y
 948
 949 config C_B1PEN
 950         depends on BF561
 951         bool "Bank 1 16 bit packing enable"
 952         default y
 953
 954 config C_B2PEN
 955         depends on BF561
 956         bool "Bank 2 16 bit packing enable"
 957         default y
 958
 959 config C_B3PEN
 960         depends on BF561
 961         bool "Bank 3 16 bit packing enable"
 962         default n
 963
 964 choice
 965         prompt"Enable Asynchonous Memory Banks"
 966         default C_AMBEN_ALL
 967
 968 config C_AMBEN
 969         bool "Disable All Banks"
 970
 971 config C_AMBEN_B0
 972         bool "Enable Bank 0"
 973
 974 config C_AMBEN_B0_B1
 975         bool "Enable Bank 0 & 1"
 976
 977 config C_AMBEN_B0_B1_B2
 978         bool "Enable Bank 0 & 1 & 2"
 979
 980 config C_AMBEN_ALL
 981         bool "Enable All Banks"
 982 endchoice
 983 endmenu
 984
 985 menu "EBIU_AMBCTL Control"
 986 config BANK_0
 987         hex "Bank 0"
 988         default 0x7BB0
 989
 990 config BANK_1
 991         hex "Bank 1"
 992         default 0x7BB0
 993         default 0x5558 if BF54x
 994
 995 config BANK_2
 996         hex "Bank 2"
 997         default 0x7BB0
 998
 999 config BANK_3
1000         hex "Bank 3"
1001         default 0x99B3
1002 endmenu
1003
1004 config EBIU_MBSCTLVAL
1005         hex "EBIU Bank Select Control Register"
1006         depends on BF54x
1007         default 0
1008
1009 config EBIU_MODEVAL
1010         hex "Flash Memory Mode Control Register"
1011         depends on BF54x
1012         default 1
1013
1014 config EBIU_FCTLVAL
1015         hex "Flash Memory Bank Control Register"
1016         depends on BF54x
1017         default 6
1018
1019 config HARDWARE_PM
1020         bool "OProfile use hardware porformance monitor"
1021         depends on OPROFILE=y
1022         default n
1023
1024 endmenu
1025
1026 #############################################################################
1027 menu "Bus options (PCI, PCMCIA, EISA, MCA, ISA)"
1028
1029 config PCI
1030         bool "PCI support"
1031         depends on BROKEN
1032         help
1033           Support for PCI bus.
1034
1035 source "drivers/pci/Kconfig"
1036
1037 config HOTPLUG
1038         bool "Support for hot-pluggable device"
1039           help
1040           Say Y here if you want to plug devices into your computer while
1041           the system is running, and be able to use them quickly.  In many
1042           cases, the devices can likewise be unplugged at any time too.
1043
1044           One well known example of this is PCMCIA- or PC-cards, credit-card
1045           size devices such as network cards, modems or hard drives which are
1046           plugged into slots found on all modern laptop computers.  Another
1047           example, used on modern desktops as well as laptops, is USB.
1048
1049           Enable HOTPLUG and build a modular kernel.  Get agent software
1050           (from <http://linux-hotplug.sourceforge.net/>) and install it.
1051           Then your kernel will automatically call out to a user mode "policy
1052           agent" (/sbin/hotplug) to load modules and set up software needed
1053           to use devices as you hotplug them.
1054
1055 source "drivers/pcmcia/Kconfig"
1056
1057 source "drivers/pci/hotplug/Kconfig"
1058
1059 endmenu
1060
1061 menu "Executable file formats"
1062
1063 source "fs/Kconfig.binfmt"
1064
1065 endmenu
1066
1067 menu "Power management options"
1068 source "kernel/power/Kconfig"
1069
1070 config ARCH_SUSPEND_POSSIBLE
1071         def_bool y
1072         depends on !SMP
1073
1074 choice
1075         prompt "Standby Power Saving Mode"
1076         depends on PM
1077         default PM_BFIN_SLEEP_DEEPER
1078 config  PM_BFIN_SLEEP_DEEPER
1079         bool "Sleep Deeper"
1080         help
1081           Sleep "Deeper" Mode (High Power Savings) - This mode reduces dynamic
1082           power dissipation by disabling the clock to the processor core (CCLK).
1083           Furthermore, Standby sets the internal power supply voltage (VDDINT)
1084           to 0.85 V to provide the greatest power savings, while preserving the
1085           processor state.
1086           The PLL and system clock (SCLK) continue to operate at a very low
1087           frequency of about 3.3 MHz. To preserve data integrity in the SDRAM,
1088           the SDRAM is put into Self Refresh Mode. Typically an external event
1089           such as GPIO interrupt or RTC activity wakes up the processor.
1090           Various Peripherals such as UART, SPORT, PPI may not function as
1091           normal during Sleep Deeper, due to the reduced SCLK frequency.
1092           When in the sleep mode, system DMA access to L1 memory is not supported.
1093
1094           If unsure, select "Sleep Deeper".
1095
1096 config  PM_BFIN_SLEEP
1097         bool "Sleep"
1098         help
1099           Sleep Mode (High Power Savings) - The sleep mode reduces power
1100           dissipation by disabling the clock to the processor core (CCLK).
1101           The PLL and system clock (SCLK), however, continue to operate in
1102           this mode. Typically an external event or RTC activity will wake
1103           up the processor. When in the sleep mode, system DMA access to L1
1104           memory is not supported.
1105
1106           If unsure, select "Sleep Deeper".
1107 endchoice
1108
1109 config PM_WAKEUP_BY_GPIO
1110         bool "Allow Wakeup from Standby by GPIO"
1111
1112 config PM_WAKEUP_GPIO_NUMBER
1113         int "GPIO number"
1114         range 0 47
1115         depends on PM_WAKEUP_BY_GPIO
1116         default 2
1117
1118 choice
1119         prompt "GPIO Polarity"
1120         depends on PM_WAKEUP_BY_GPIO
1121         default PM_WAKEUP_GPIO_POLAR_H
1122 config  PM_WAKEUP_GPIO_POLAR_H
1123         bool "Active High"
1124 config  PM_WAKEUP_GPIO_POLAR_L
1125         bool "Active Low"
1126 config  PM_WAKEUP_GPIO_POLAR_EDGE_F
1127         bool "Falling EDGE"
1128 config  PM_WAKEUP_GPIO_POLAR_EDGE_R
1129         bool "Rising EDGE"
1130 config  PM_WAKEUP_GPIO_POLAR_EDGE_B
1131         bool "Both EDGE"
1132 endchoice
1133
1134 comment "Possible Suspend Mem / Hibernate Wake-Up Sources"
1135         depends on PM
1136
1137 config PM_BFIN_WAKE_PH6
1138         bool "Allow Wake-Up from on-chip PHY or PH6 GP"
1139         depends on PM && (BF51x || BF52x || BF534 || BF536 || BF537)
1140         default n
1141         help
1142           Enable PHY and PH6 GP Wake-Up (Voltage Regulator Power-Up)
1143
1144 config PM_BFIN_WAKE_GP
1145         bool "Allow Wake-Up from GPIOs"
1146         depends on PM && BF54x
1147         default n
1148         help
1149           Enable General-Purpose Wake-Up (Voltage Regulator Power-Up)
1150 endmenu
1151
1152 menu "CPU Frequency scaling"
1153
1154 source "drivers/cpufreq/Kconfig"
1155
1156 config BFIN_CPU_FREQ
1157         bool
1158         depends on CPU_FREQ
1159         select CPU_FREQ_TABLE
1160         default y
1161
1162 config CPU_VOLTAGE
1163         bool "CPU Voltage scaling"
1164         depends on EXPERIMENTAL
1165         depends on CPU_FREQ
1166         default n
1167         help
1168           Say Y here if you want CPU voltage scaling according to the CPU frequency.
1169           This option violates the PLL BYPASS recommendation in the Blackfin Processor
1170           manuals. There is a theoretical risk that during VDDINT transitions
1171           the PLL may unlock.
1172
1173 endmenu
1174
1175 source "net/Kconfig"
1176
1177 source "drivers/Kconfig"
1178
1179 source "fs/Kconfig"
1180
1181 source "arch/blackfin/Kconfig.debug"
1182
1183 source "security/Kconfig"
1184
1185 source "crypto/Kconfig"
1186
1187 source "lib/Kconfig"