arch/blackfin/Kconfig

   1 #
   2 # For a description of the syntax of this configuration file,
   3 # see Documentation/kbuild/kconfig-language.txt.
   4 #
   5
   6 mainmenu "Blackfin Kernel Configuration"
   7
   8 config MMU
   9         bool
  10         default n
  11
  12 config FPU
  13         bool
  14         default n
  15
  16 config RWSEM_GENERIC_SPINLOCK
  17         bool
  18         default y
  19
  20 config RWSEM_XCHGADD_ALGORITHM
  21         bool
  22         default n
  23
  24 config BLACKFIN
  25         bool
  26         default y
  27         select HAVE_IDE
  28         select HAVE_OPROFILE
  29         select ARCH_WANT_OPTIONAL_GPIOLIB
  30
  31 config ZONE_DMA
  32         bool
  33         default y
  34
  35 config GENERIC_FIND_NEXT_BIT
  36         bool
  37         default y
  38
  39 config GENERIC_HWEIGHT
  40         bool
  41         default y
  42
  43 config GENERIC_HARDIRQS
  44         bool
  45         default y
  46
  47 config GENERIC_IRQ_PROBE
  48         bool
  49         default y
  50
  51 config GENERIC_GPIO
  52         bool
  53         default y
  54
  55 config FORCE_MAX_ZONEORDER
  56         int
  57         default "14"
  58
  59 config GENERIC_CALIBRATE_DELAY
  60         bool
  61         default y
  62
  63 source "init/Kconfig"
  64
  65 source "kernel/Kconfig.preempt"
  66
  67 source "kernel/Kconfig.freezer"
  68
  69 menu "Blackfin Processor Options"
  70
  71 comment "Processor and Board Settings"
  72
  73 choice
  74         prompt "CPU"
  75         default BF533
  76
  77 config BF512
  78         bool "BF512"
  79         help
  80           BF512 Processor Support.
  81
  82 config BF514
  83         bool "BF514"
  84         help
  85           BF514 Processor Support.
  86
  87 config BF516
  88         bool "BF516"
  89         help
  90           BF516 Processor Support.
  91
  92 config BF518
  93         bool "BF518"
  94         help
  95           BF518 Processor Support.
  96
  97 config BF522
  98         bool "BF522"
  99         help
 100           BF522 Processor Support.
 101
 102 config BF523
 103         bool "BF523"
 104         help
 105           BF523 Processor Support.
 106
 107 config BF524
 108         bool "BF524"
 109         help
 110           BF524 Processor Support.
 111
 112 config BF525
 113         bool "BF525"
 114         help
 115           BF525 Processor Support.
 116
 117 config BF526
 118         bool "BF526"
 119         help
 120           BF526 Processor Support.
 121
 122 config BF527
 123         bool "BF527"
 124         help
 125           BF527 Processor Support.
 126
 127 config BF531
 128         bool "BF531"
 129         help
 130           BF531 Processor Support.
 131
 132 config BF532
 133         bool "BF532"
 134         help
 135           BF532 Processor Support.
 136
 137 config BF533
 138         bool "BF533"
 139         help
 140           BF533 Processor Support.
 141
 142 config BF534
 143         bool "BF534"
 144         help
 145           BF534 Processor Support.
 146
 147 config BF536
 148         bool "BF536"
 149         help
 150           BF536 Processor Support.
 151
 152 config BF537
 153         bool "BF537"
 154         help
 155           BF537 Processor Support.
 156
 157 config BF538
 158         bool "BF538"
 159         help
 160           BF538 Processor Support.
 161
 162 config BF539
 163         bool "BF539"
 164         help
 165           BF539 Processor Support.
 166
 167 config BF542
 168         bool "BF542"
 169         help
 170           BF542 Processor Support.
 171
 172 config BF544
 173         bool "BF544"
 174         help
 175           BF544 Processor Support.
 176
 177 config BF547
 178         bool "BF547"
 179         help
 180           BF547 Processor Support.
 181
 182 config BF548
 183         bool "BF548"
 184         help
 185           BF548 Processor Support.
 186
 187 config BF549
 188         bool "BF549"
 189         help
 190           BF549 Processor Support.
 191
 192 config BF561
 193         bool "BF561"
 194         help
 195           BF561 Processor Support.
 196
 197 endchoice
 198
 199 config SMP
 200         depends on BF561
 201         bool "Symmetric multi-processing support"
 202         ---help---
 203           This enables support for systems with more than one CPU,
 204           like the dual core BF561. If you have a system with only one
 205           CPU, say N. If you have a system with more than one CPU, say Y.
 206
 207           If you don't know what to do here, say N.
 208
 209 config NR_CPUS
 210         int
 211         depends on SMP
 212         default 2 if BF561
 213
 214 config IRQ_PER_CPU
 215         bool
 216         depends on SMP
 217         default y
 218
 219 config TICK_SOURCE_SYSTMR0
 220         bool
 221         select BFIN_GPTIMERS
 222         depends on SMP
 223         default y
 224
 225 config BF_REV_MIN
 226         int
 227         default 0 if (BF51x || BF52x || BF54x)
 228         default 2 if (BF537 || BF536 || BF534)
 229         default 3 if (BF561 ||BF533 || BF532 || BF531)
 230         default 4 if (BF538 || BF539)
 231
 232 config BF_REV_MAX
 233         int
 234         default 2 if (BF51x || BF52x || BF54x)
 235         default 3 if (BF537 || BF536 || BF534)
 236         default 5 if (BF561 || BF538 || BF539)
 237         default 6 if (BF533 || BF532 || BF531)
 238
 239 choice
 240         prompt "Silicon Rev"
 241         default BF_REV_0_1 if (BF51x || BF52x || BF54x)
 242         default BF_REV_0_2 if (BF534 || BF536 || BF537)
 243         default BF_REV_0_3 if (BF531 || BF532 || BF533 || BF561)
 244
 245 config BF_REV_0_0
 246         bool "0.0"
 247         depends on (BF51x || BF52x || BF54x)
 248
 249 config BF_REV_0_1
 250         bool "0.1"
 251         depends on (BF52x || BF54x)
 252
 253 config BF_REV_0_2
 254         bool "0.2"
 255         depends on (BF52x || BF537 || BF536 || BF534 || BF54x)
 256
 257 config BF_REV_0_3
 258         bool "0.3"
 259         depends on (BF561 || BF537 || BF536 || BF534 || BF533 || BF532 || BF531)
 260
 261 config BF_REV_0_4
 262         bool "0.4"
 263         depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539)
 264
 265 config BF_REV_0_5
 266         bool "0.5"
 267         depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539)
 268
 269 config BF_REV_0_6
 270         bool "0.6"
 271         depends on (BF533 || BF532 || BF531)
 272
 273 config BF_REV_ANY
 274         bool "any"
 275
 276 config BF_REV_NONE
 277         bool "none"
 278
 279 endchoice
 280
 281 config BF51x
 282         bool
 283         depends on (BF512 || BF514 || BF516 || BF518)
 284         default y
 285
 286 config BF52x
 287         bool
 288         depends on (BF522 || BF523 || BF524 || BF525 || BF526 || BF527)
 289         default y
 290
 291 config BF53x
 292         bool
 293         depends on (BF531 || BF532 || BF533 || BF534 || BF536 || BF537)
 294         default y
 295
 296 config BF54x
 297         bool
 298         depends on (BF542 || BF544 || BF547 || BF548 || BF549)
 299         default y
 300
 301 config MEM_GENERIC_BOARD
 302         bool
 303         depends on GENERIC_BOARD
 304         default y
 305
 306 config MEM_MT48LC64M4A2FB_7E
 307         bool
 308         depends on (BFIN533_STAMP)
 309         default y
 310
 311 config MEM_MT48LC16M16A2TG_75
 312         bool
 313         depends on (BFIN533_EZKIT || BFIN561_EZKIT \
 314                 || BFIN533_BLUETECHNIX_CM || BFIN537_BLUETECHNIX_CM \
 315                 || H8606_HVSISTEMAS || BFIN527_BLUETECHNIX_CM)
 316         default y
 317
 318 config MEM_MT48LC32M8A2_75
 319         bool
 320         depends on (BFIN537_STAMP || PNAV10 || BFIN538_EZKIT)
 321         default y
 322
 323 config MEM_MT48LC8M32B2B5_7
 324         bool
 325         depends on (BFIN561_BLUETECHNIX_CM)
 326         default y
 327
 328 config MEM_MT48LC32M16A2TG_75
 329         bool
 330         depends on (BFIN527_EZKIT || BFIN532_IP0X || BLACKSTAMP || BFIN526_EZBRD)
 331         default y
 332
 333 source "arch/blackfin/mach-bf518/Kconfig"
 334 source "arch/blackfin/mach-bf527/Kconfig"
 335 source "arch/blackfin/mach-bf533/Kconfig"
 336 source "arch/blackfin/mach-bf561/Kconfig"
 337 source "arch/blackfin/mach-bf537/Kconfig"
 338 source "arch/blackfin/mach-bf538/Kconfig"
 339 source "arch/blackfin/mach-bf548/Kconfig"
 340
 341 menu "Board customizations"
 342
 343 config CMDLINE_BOOL
 344         bool "Default bootloader kernel arguments"
 345
 346 config CMDLINE
 347         string "Initial kernel command string"
 348         depends on CMDLINE_BOOL
 349         default "console=ttyBF0,57600"
 350         help
 351           If you don't have a boot loader capable of passing a command line string
 352           to the kernel, you may specify one here. As a minimum, you should specify
 353           the memory size and the root device (e.g., mem=8M, root=/dev/nfs).
 354
 355 config BOOT_LOAD
 356         hex "Kernel load address for booting"
 357         default "0x1000"
 358         range 0x1000 0x20000000
 359         help
 360           This option allows you to set the load address of the kernel.
 361           This can be useful if you are on a board which has a small amount
 362           of memory or you wish to reserve some memory at the beginning of
 363           the address space.
 364
 365           Note that you need to keep this value above 4k (0x1000) as this
 366           memory region is used to capture NULL pointer references as well
 367           as some core kernel functions.
 368
 369 config ROM_BASE
 370         hex "Kernel ROM Base"
 371         depends on ROMKERNEL
 372         default "0x20040000"
 373         range 0x20000000 0x20400000 if !(BF54x || BF561)
 374         range 0x20000000 0x30000000 if (BF54x || BF561)
 375         help
 376
 377 comment "Clock/PLL Setup"
 378
 379 config CLKIN_HZ
 380         int "Frequency of the crystal on the board in Hz"
 381         default "11059200" if BFIN533_STAMP
 382         default "27000000" if BFIN533_EZKIT
 383         default "25000000" if (BFIN537_STAMP || BFIN527_EZKIT || H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD || BFIN538_EZKIT || BFIN518F-EZBRD)
 384         default "30000000" if BFIN561_EZKIT
 385         default "24576000" if PNAV10
 386         default "10000000" if BFIN532_IP0X
 387         help
 388           The frequency of CLKIN crystal oscillator on the board in Hz.
 389           Warning: This value should match the crystal on the board. Otherwise,
 390           peripherals won't work properly.
 391
 392 config BFIN_KERNEL_CLOCK
 393         bool "Re-program Clocks while Kernel boots?"
 394         default n
 395         help
 396           This option decides if kernel clocks are re-programed from the
 397           bootloader settings. If the clocks are not set, the SDRAM settings
 398           are also not changed, and the Bootloader does 100% of the hardware
 399           configuration.
 400
 401 config PLL_BYPASS
 402         bool "Bypass PLL"
 403         depends on BFIN_KERNEL_CLOCK
 404         default n
 405
 406 config CLKIN_HALF
 407         bool "Half Clock In"
 408         depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
 409         default n
 410         help
 411           If this is set the clock will be divided by 2, before it goes to the PLL.
 412
 413 config VCO_MULT
 414         int "VCO Multiplier"
 415         depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
 416         range 1 64
 417         default "22" if BFIN533_EZKIT
 418         default "45" if BFIN533_STAMP
 419         default "20" if (BFIN537_STAMP || BFIN527_EZKIT || BFIN548_EZKIT || BFIN548_BLUETECHNIX_CM || BFIN538_EZKIT)
 420         default "22" if BFIN533_BLUETECHNIX_CM
 421         default "20" if (BFIN537_BLUETECHNIX_CM || BFIN527_BLUETECHNIX_CM || BFIN561_BLUETECHNIX_CM)
 422         default "20" if BFIN561_EZKIT
 423         default "16" if (H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD || BFIN518F_EZBRD)
 424         help
 425           This controls the frequency of the on-chip PLL. This can be between 1 and 64.
 426           PLL Frequency = (Crystal Frequency) * (this setting)
 427
 428 choice
 429         prompt "Core Clock Divider"
 430         depends on BFIN_KERNEL_CLOCK
 431         default CCLK_DIV_1
 432         help
 433           This sets the frequency of the core. It can be 1, 2, 4 or 8
 434           Core Frequency = (PLL frequency) / (this setting)
 435
 436 config CCLK_DIV_1
 437         bool "1"
 438
 439 config CCLK_DIV_2
 440         bool "2"
 441
 442 config CCLK_DIV_4
 443         bool "4"
 444
 445 config CCLK_DIV_8
 446         bool "8"
 447 endchoice
 448
 449 config SCLK_DIV
 450         int "System Clock Divider"
 451         depends on BFIN_KERNEL_CLOCK
 452         range 1 15
 453         default 5
 454         help
 455           This sets the frequency of the system clock (including SDRAM or DDR).
 456           This can be between 1 and 15
 457           System Clock = (PLL frequency) / (this setting)
 458
 459 choice
 460         prompt "DDR SDRAM Chip Type"
 461         depends on BFIN_KERNEL_CLOCK
 462         depends on BF54x
 463         default MEM_MT46V32M16_5B
 464
 465 config MEM_MT46V32M16_6T
 466         bool "MT46V32M16_6T"
 467
 468 config MEM_MT46V32M16_5B
 469         bool "MT46V32M16_5B"
 470 endchoice
 471
 472 choice
 473         prompt "DDR/SDRAM Timing"
 474         depends on BFIN_KERNEL_CLOCK
 475         default BFIN_KERNEL_CLOCK_MEMINIT_CALC
 476         help
 477           This option allows you to specify Blackfin SDRAM/DDR Timing parameters
 478           The calculated SDRAM timing parameters may not be 100%
 479           accurate - This option is therefore marked experimental.
 480
 481 config BFIN_KERNEL_CLOCK_MEMINIT_CALC
 482         bool "Calculate Timings (EXPERIMENTAL)"
 483         depends on EXPERIMENTAL
 484
 485 config BFIN_KERNEL_CLOCK_MEMINIT_SPEC
 486         bool "Provide accurate Timings based on target SCLK"
 487         help
 488           Please consult the Blackfin Hardware Reference Manuals as well
 489           as the memory device datasheet.
 490           http://docs.blackfin.uclinux.org/doku.php?id=bfin:sdram
 491 endchoice
 492
 493 menu "Memory Init Control"
 494         depends on BFIN_KERNEL_CLOCK_MEMINIT_SPEC
 495
 496 config MEM_DDRCTL0
 497         depends on BF54x
 498         hex "DDRCTL0"
 499         default 0x0
 500
 501 config MEM_DDRCTL1
 502         depends on BF54x
 503         hex "DDRCTL1"
 504         default 0x0
 505
 506 config MEM_DDRCTL2
 507         depends on BF54x
 508         hex "DDRCTL2"
 509         default 0x0
 510
 511 config MEM_EBIU_DDRQUE
 512         depends on BF54x
 513         hex "DDRQUE"
 514         default 0x0
 515
 516 config MEM_SDRRC
 517         depends on !BF54x
 518         hex "SDRRC"
 519         default 0x0
 520
 521 config MEM_SDGCTL
 522         depends on !BF54x
 523         hex "SDGCTL"
 524         default 0x0
 525 endmenu
 526
 527 #
 528 # Max & Min Speeds for various Chips
 529 #
 530 config MAX_VCO_HZ
 531         int
 532         default 400000000 if BF512
 533         default 400000000 if BF514
 534         default 400000000 if BF516
 535         default 400000000 if BF518
 536         default 600000000 if BF522
 537         default 400000000 if BF523
 538         default 400000000 if BF524
 539         default 600000000 if BF525
 540         default 400000000 if BF526
 541         default 600000000 if BF527
 542         default 400000000 if BF531
 543         default 400000000 if BF532
 544         default 750000000 if BF533
 545         default 500000000 if BF534
 546         default 400000000 if BF536
 547         default 600000000 if BF537
 548         default 533333333 if BF538
 549         default 533333333 if BF539
 550         default 600000000 if BF542
 551         default 533333333 if BF544
 552         default 600000000 if BF547
 553         default 600000000 if BF548
 554         default 533333333 if BF549
 555         default 600000000 if BF561
 556
 557 config MIN_VCO_HZ
 558         int
 559         default 50000000
 560
 561 config MAX_SCLK_HZ
 562         int
 563         default 133333333
 564
 565 config MIN_SCLK_HZ
 566         int
 567         default 27000000
 568
 569 comment "Kernel Timer/Scheduler"
 570
 571 source kernel/Kconfig.hz
 572
 573 config GENERIC_TIME
 574         bool "Generic time"
 575         depends on !SMP
 576         default y
 577
 578 config GENERIC_CLOCKEVENTS
 579         bool "Generic clock events"
 580         depends on GENERIC_TIME
 581         default y
 582
 583 config CYCLES_CLOCKSOURCE
 584         bool "Use 'CYCLES' as a clocksource (EXPERIMENTAL)"
 585         depends on EXPERIMENTAL
 586         depends on GENERIC_CLOCKEVENTS
 587         depends on !BFIN_SCRATCH_REG_CYCLES
 588         default n
 589         help
 590           If you say Y here, you will enable support for using the 'cycles'
 591           registers as a clock source.  Doing so means you will be unable to
 592           safely write to the 'cycles' register during runtime.  You will
 593           still be able to read it (such as for performance monitoring), but
 594           writing the registers will most likely crash the kernel.
 595
 596 source kernel/time/Kconfig
 597
 598 comment "Misc"
 599
 600 choice
 601         prompt "Blackfin Exception Scratch Register"
 602         default BFIN_SCRATCH_REG_RETN
 603         help
 604           Select the resource to reserve for the Exception handler:
 605             - RETN: Non-Maskable Interrupt (NMI)
 606             - RETE: Exception Return (JTAG/ICE)
 607             - CYCLES: Performance counter
 608
 609           If you are unsure, please select "RETN".
 610
 611 config BFIN_SCRATCH_REG_RETN
 612         bool "RETN"
 613         help
 614           Use the RETN register in the Blackfin exception handler
 615           as a stack scratch register.  This means you cannot
 616           safely use NMI on the Blackfin while running Linux, but
 617           you can debug the system with a JTAG ICE and use the
 618           CYCLES performance registers.
 619
 620           If you are unsure, please select "RETN".
 621
 622 config BFIN_SCRATCH_REG_RETE
 623         bool "RETE"
 624         help
 625           Use the RETE register in the Blackfin exception handler
 626           as a stack scratch register.  This means you cannot
 627           safely use a JTAG ICE while debugging a Blackfin board,
 628           but you can safely use the CYCLES performance registers
 629           and the NMI.
 630
 631           If you are unsure, please select "RETN".
 632
 633 config BFIN_SCRATCH_REG_CYCLES
 634         bool "CYCLES"
 635         help
 636           Use the CYCLES register in the Blackfin exception handler
 637           as a stack scratch register.  This means you cannot
 638           safely use the CYCLES performance registers on a Blackfin
 639           board at anytime, but you can debug the system with a JTAG
 640           ICE and use the NMI.
 641
 642           If you are unsure, please select "RETN".
 643
 644 endchoice
 645
 646 endmenu
 647
 648
 649 menu "Blackfin Kernel Optimizations"
 650         depends on !SMP
 651
 652 comment "Memory Optimizations"
 653
 654 config I_ENTRY_L1
 655         bool "Locate interrupt entry code in L1 Memory"
 656         default y
 657         help
 658           If enabled, interrupt entry code (STORE/RESTORE CONTEXT) is linked
 659           into L1 instruction memory. (less latency)
 660
 661 config EXCPT_IRQ_SYSC_L1
 662         bool "Locate entire ASM lowlevel exception / interrupt - Syscall and CPLB handler code in L1 Memory"
 663         default y
 664         help
 665           If enabled, the entire ASM lowlevel exception and interrupt entry code
 666           (STORE/RESTORE CONTEXT) is linked into L1 instruction memory.
 667           (less latency)
 668
 669 config DO_IRQ_L1
 670         bool "Locate frequently called do_irq dispatcher function in L1 Memory"
 671         default y
 672         help
 673           If enabled, the frequently called do_irq dispatcher function is linked
 674           into L1 instruction memory. (less latency)
 675
 676 config CORE_TIMER_IRQ_L1
 677         bool "Locate frequently called timer_interrupt() function in L1 Memory"
 678         default y
 679         help
 680           If enabled, the frequently called timer_interrupt() function is linked
 681           into L1 instruction memory. (less latency)
 682
 683 config IDLE_L1
 684         bool "Locate frequently idle function in L1 Memory"
 685         default y
 686         help
 687           If enabled, the frequently called idle function is linked
 688           into L1 instruction memory. (less latency)
 689
 690 config SCHEDULE_L1
 691         bool "Locate kernel schedule function in L1 Memory"
 692         default y
 693         help
 694           If enabled, the frequently called kernel schedule is linked
 695           into L1 instruction memory. (less latency)
 696
 697 config ARITHMETIC_OPS_L1
 698         bool "Locate kernel owned arithmetic functions in L1 Memory"
 699         default y
 700         help
 701           If enabled, arithmetic functions are linked
 702           into L1 instruction memory. (less latency)
 703
 704 config ACCESS_OK_L1
 705         bool "Locate access_ok function in L1 Memory"
 706         default y
 707         help
 708           If enabled, the access_ok function is linked
 709           into L1 instruction memory. (less latency)
 710
 711 config MEMSET_L1
 712         bool "Locate memset function in L1 Memory"
 713         default y
 714         help
 715           If enabled, the memset function is linked
 716           into L1 instruction memory. (less latency)
 717
 718 config MEMCPY_L1
 719         bool "Locate memcpy function in L1 Memory"
 720         default y
 721         help
 722           If enabled, the memcpy function is linked
 723           into L1 instruction memory. (less latency)
 724
 725 config SYS_BFIN_SPINLOCK_L1
 726         bool "Locate sys_bfin_spinlock function in L1 Memory"
 727         default y
 728         help
 729           If enabled, sys_bfin_spinlock function is linked
 730           into L1 instruction memory. (less latency)
 731
 732 config IP_CHECKSUM_L1
 733         bool "Locate IP Checksum function in L1 Memory"
 734         default n
 735         help
 736           If enabled, the IP Checksum function is linked
 737           into L1 instruction memory. (less latency)
 738
 739 config CACHELINE_ALIGNED_L1
 740         bool "Locate cacheline_aligned data to L1 Data Memory"
 741         default y if !BF54x
 742         default n if BF54x
 743         depends on !BF531
 744         help
 745           If enabled, cacheline_anligned data is linked
 746           into L1 data memory. (less latency)
 747
 748 config SYSCALL_TAB_L1
 749         bool "Locate Syscall Table L1 Data Memory"
 750         default n
 751         depends on !BF531
 752         help
 753           If enabled, the Syscall LUT is linked
 754           into L1 data memory. (less latency)
 755
 756 config CPLB_SWITCH_TAB_L1
 757         bool "Locate CPLB Switch Tables L1 Data Memory"
 758         default n
 759         depends on !BF531
 760         help
 761           If enabled, the CPLB Switch Tables are linked
 762           into L1 data memory. (less latency)
 763
 764 config APP_STACK_L1
 765         bool "Support locating application stack in L1 Scratch Memory"
 766         default y
 767         help
 768           If enabled the application stack can be located in L1
 769           scratch memory (less latency).
 770
 771           Currently only works with FLAT binaries.
 772
 773 config EXCEPTION_L1_SCRATCH
 774         bool "Locate exception stack in L1 Scratch Memory"
 775         default n
 776         depends on !APP_STACK_L1 && !SYSCALL_TAB_L1
 777         help
 778           Whenever an exception occurs, use the L1 Scratch memory for
 779           stack storage.  You cannot place the stacks of FLAT binaries
 780           in L1 when using this option.
 781
 782           If you don't use L1 Scratch, then you should say Y here.
 783
 784 comment "Speed Optimizations"
 785 config BFIN_INS_LOWOVERHEAD
 786         bool "ins[bwl] low overhead, higher interrupt latency"
 787         default y
 788         help
 789           Reads on the Blackfin are speculative. In Blackfin terms, this means
 790           they can be interrupted at any time (even after they have been issued
 791           on to the external bus), and re-issued after the interrupt occurs.
 792           For memory - this is not a big deal, since memory does not change if
 793           it sees a read.
 794
 795           If a FIFO is sitting on the end of the read, it will see two reads,
 796           when the core only sees one since the FIFO receives both the read
 797           which is cancelled (and not delivered to the core) and the one which
 798           is re-issued (which is delivered to the core).
 799
 800           To solve this, interrupts are turned off before reads occur to
 801           I/O space. This option controls which the overhead/latency of
 802           controlling interrupts during this time
 803            "n" turns interrupts off every read
 804                 (higher overhead, but lower interrupt latency)
 805            "y" turns interrupts off every loop
 806                 (low overhead, but longer interrupt latency)
 807
 808           default behavior is to leave this set to on (type "Y"). If you are experiencing
 809           interrupt latency issues, it is safe and OK to turn this off.
 810
 811 endmenu
 812
 813 choice
 814         prompt "Kernel executes from"
 815         help
 816           Choose the memory type that the kernel will be running in.
 817
 818 config RAMKERNEL
 819         bool "RAM"
 820         help
 821           The kernel will be resident in RAM when running.
 822
 823 config ROMKERNEL
 824         bool "ROM"
 825         help
 826           The kernel will be resident in FLASH/ROM when running.
 827
 828 endchoice
 829
 830 source "mm/Kconfig"
 831
 832 config BFIN_GPTIMERS
 833         tristate "Enable Blackfin General Purpose Timers API"
 834         default n
 835         help
 836           Enable support for the General Purpose Timers API.  If you
 837           are unsure, say N.
 838
 839           To compile this driver as a module, choose M here: the module
 840           will be called gptimers.ko.
 841
 842 choice
 843         prompt "Uncached DMA region"
 844         default DMA_UNCACHED_1M
 845 config DMA_UNCACHED_4M
 846         bool "Enable 4M DMA region"
 847 config DMA_UNCACHED_2M
 848         bool "Enable 2M DMA region"
 849 config DMA_UNCACHED_1M
 850         bool "Enable 1M DMA region"
 851 config DMA_UNCACHED_NONE
 852         bool "Disable DMA region"
 853 endchoice
 854
 855
 856 comment "Cache Support"
 857 config BFIN_ICACHE
 858         bool "Enable ICACHE"
 859 config BFIN_DCACHE
 860         bool "Enable DCACHE"
 861 config BFIN_DCACHE_BANKA
 862         bool "Enable only 16k BankA DCACHE - BankB is SRAM"
 863         depends on BFIN_DCACHE && !BF531
 864         default n
 865 config BFIN_ICACHE_LOCK
 866         bool "Enable Instruction Cache Locking"
 867
 868 choice
 869         prompt "Policy"
 870         depends on BFIN_DCACHE
 871         default BFIN_WB if !SMP
 872         default BFIN_WT if SMP
 873 config BFIN_WB
 874         bool "Write back"
 875         depends on !SMP
 876         help
 877           Write Back Policy:
 878             Cached data will be written back to SDRAM only when needed.
 879             This can give a nice increase in performance, but beware of
 880             broken drivers that do not properly invalidate/flush their
 881             cache.
 882
 883           Write Through Policy:
 884             Cached data will always be written back to SDRAM when the
 885             cache is updated.  This is a completely safe setting, but
 886             performance is worse than Write Back.
 887
 888           If you are unsure of the options and you want to be safe,
 889           then go with Write Through.
 890
 891 config BFIN_WT
 892         bool "Write through"
 893         help
 894           Write Back Policy:
 895             Cached data will be written back to SDRAM only when needed.
 896             This can give a nice increase in performance, but beware of
 897             broken drivers that do not properly invalidate/flush their
 898             cache.
 899
 900           Write Through Policy:
 901             Cached data will always be written back to SDRAM when the
 902             cache is updated.  This is a completely safe setting, but
 903             performance is worse than Write Back.
 904
 905           If you are unsure of the options and you want to be safe,
 906           then go with Write Through.
 907
 908 endchoice
 909
 910 config BFIN_L2_CACHEABLE
 911         bool "Cache L2 SRAM"
 912         depends on (BFIN_DCACHE || BFIN_ICACHE) && (BF54x || (BF561 && !SMP))
 913         default n
 914         help
 915           Select to make L2 SRAM cacheable in L1 data and instruction cache.
 916
 917 config MPU
 918         bool "Enable the memory protection unit (EXPERIMENTAL)"
 919         default n
 920         help
 921           Use the processor's MPU to protect applications from accessing
 922           memory they do not own.  This comes at a performance penalty
 923           and is recommended only for debugging.
 924
 925 comment "Asynchonous Memory Configuration"
 926
 927 menu "EBIU_AMGCTL Global Control"
 928 config C_AMCKEN
 929         bool "Enable CLKOUT"
 930         default y
 931
 932 config C_CDPRIO
 933         bool "DMA has priority over core for ext. accesses"
 934         default n
 935
 936 config C_B0PEN
 937         depends on BF561
 938         bool "Bank 0 16 bit packing enable"
 939         default y
 940
 941 config C_B1PEN
 942         depends on BF561
 943         bool "Bank 1 16 bit packing enable"
 944         default y
 945
 946 config C_B2PEN
 947         depends on BF561
 948         bool "Bank 2 16 bit packing enable"
 949         default y
 950
 951 config C_B3PEN
 952         depends on BF561
 953         bool "Bank 3 16 bit packing enable"
 954         default n
 955
 956 choice
 957         prompt"Enable Asynchonous Memory Banks"
 958         default C_AMBEN_ALL
 959
 960 config C_AMBEN
 961         bool "Disable All Banks"
 962
 963 config C_AMBEN_B0
 964         bool "Enable Bank 0"
 965
 966 config C_AMBEN_B0_B1
 967         bool "Enable Bank 0 & 1"
 968
 969 config C_AMBEN_B0_B1_B2
 970         bool "Enable Bank 0 & 1 & 2"
 971
 972 config C_AMBEN_ALL
 973         bool "Enable All Banks"
 974 endchoice
 975 endmenu
 976
 977 menu "EBIU_AMBCTL Control"
 978 config BANK_0
 979         hex "Bank 0"
 980         default 0x7BB0
 981
 982 config BANK_1
 983         hex "Bank 1"
 984         default 0x7BB0
 985         default 0x5558 if BF54x
 986
 987 config BANK_2
 988         hex "Bank 2"
 989         default 0x7BB0
 990
 991 config BANK_3
 992         hex "Bank 3"
 993         default 0x99B3
 994 endmenu
 995
 996 config EBIU_MBSCTLVAL
 997         hex "EBIU Bank Select Control Register"
 998         depends on BF54x
 999         default 0
1000
1001 config EBIU_MODEVAL
1002         hex "Flash Memory Mode Control Register"
1003         depends on BF54x
1004         default 1
1005
1006 config EBIU_FCTLVAL
1007         hex "Flash Memory Bank Control Register"
1008         depends on BF54x
1009         default 6
1010
1011 config HARDWARE_PM
1012         bool "OProfile use hardware porformance monitor"
1013         depends on OPROFILE=y
1014         default n
1015
1016 endmenu
1017
1018 #############################################################################
1019 menu "Bus options (PCI, PCMCIA, EISA, MCA, ISA)"
1020
1021 config PCI
1022         bool "PCI support"
1023         depends on BROKEN
1024         help
1025           Support for PCI bus.
1026
1027 source "drivers/pci/Kconfig"
1028
1029 config HOTPLUG
1030         bool "Support for hot-pluggable device"
1031           help
1032           Say Y here if you want to plug devices into your computer while
1033           the system is running, and be able to use them quickly.  In many
1034           cases, the devices can likewise be unplugged at any time too.
1035
1036           One well known example of this is PCMCIA- or PC-cards, credit-card
1037           size devices such as network cards, modems or hard drives which are
1038           plugged into slots found on all modern laptop computers.  Another
1039           example, used on modern desktops as well as laptops, is USB.
1040
1041           Enable HOTPLUG and build a modular kernel.  Get agent software
1042           (from <http://linux-hotplug.sourceforge.net/>) and install it.
1043           Then your kernel will automatically call out to a user mode "policy
1044           agent" (/sbin/hotplug) to load modules and set up software needed
1045           to use devices as you hotplug them.
1046
1047 source "drivers/pcmcia/Kconfig"
1048
1049 source "drivers/pci/hotplug/Kconfig"
1050
1051 endmenu
1052
1053 menu "Executable file formats"
1054
1055 source "fs/Kconfig.binfmt"
1056
1057 endmenu
1058
1059 menu "Power management options"
1060 source "kernel/power/Kconfig"
1061
1062 config ARCH_SUSPEND_POSSIBLE
1063         def_bool y
1064         depends on !SMP
1065
1066 choice
1067         prompt "Standby Power Saving Mode"
1068         depends on PM
1069         default PM_BFIN_SLEEP_DEEPER
1070 config  PM_BFIN_SLEEP_DEEPER
1071         bool "Sleep Deeper"
1072         help
1073           Sleep "Deeper" Mode (High Power Savings) - This mode reduces dynamic
1074           power dissipation by disabling the clock to the processor core (CCLK).
1075           Furthermore, Standby sets the internal power supply voltage (VDDINT)
1076           to 0.85 V to provide the greatest power savings, while preserving the
1077           processor state.
1078           The PLL and system clock (SCLK) continue to operate at a very low
1079           frequency of about 3.3 MHz. To preserve data integrity in the SDRAM,
1080           the SDRAM is put into Self Refresh Mode. Typically an external event
1081           such as GPIO interrupt or RTC activity wakes up the processor.
1082           Various Peripherals such as UART, SPORT, PPI may not function as
1083           normal during Sleep Deeper, due to the reduced SCLK frequency.
1084           When in the sleep mode, system DMA access to L1 memory is not supported.
1085
1086           If unsure, select "Sleep Deeper".
1087
1088 config  PM_BFIN_SLEEP
1089         bool "Sleep"
1090         help
1091           Sleep Mode (High Power Savings) - The sleep mode reduces power
1092           dissipation by disabling the clock to the processor core (CCLK).
1093           The PLL and system clock (SCLK), however, continue to operate in
1094           this mode. Typically an external event or RTC activity will wake
1095           up the processor. When in the sleep mode, system DMA access to L1
1096           memory is not supported.
1097
1098           If unsure, select "Sleep Deeper".
1099 endchoice
1100
1101 config PM_WAKEUP_BY_GPIO
1102         bool "Allow Wakeup from Standby by GPIO"
1103
1104 config PM_WAKEUP_GPIO_NUMBER
1105         int "GPIO number"
1106         range 0 47
1107         depends on PM_WAKEUP_BY_GPIO
1108         default 2
1109
1110 choice
1111         prompt "GPIO Polarity"
1112         depends on PM_WAKEUP_BY_GPIO
1113         default PM_WAKEUP_GPIO_POLAR_H
1114 config  PM_WAKEUP_GPIO_POLAR_H
1115         bool "Active High"
1116 config  PM_WAKEUP_GPIO_POLAR_L
1117         bool "Active Low"
1118 config  PM_WAKEUP_GPIO_POLAR_EDGE_F
1119         bool "Falling EDGE"
1120 config  PM_WAKEUP_GPIO_POLAR_EDGE_R
1121         bool "Rising EDGE"
1122 config  PM_WAKEUP_GPIO_POLAR_EDGE_B
1123         bool "Both EDGE"
1124 endchoice
1125
1126 comment "Possible Suspend Mem / Hibernate Wake-Up Sources"
1127         depends on PM
1128
1129 config PM_BFIN_WAKE_PH6
1130         bool "Allow Wake-Up from on-chip PHY or PH6 GP"
1131         depends on PM && (BF51x || BF52x || BF534 || BF536 || BF537)
1132         default n
1133         help
1134           Enable PHY and PH6 GP Wake-Up (Voltage Regulator Power-Up)
1135
1136 config PM_BFIN_WAKE_GP
1137         bool "Allow Wake-Up from GPIOs"
1138         depends on PM && BF54x
1139         default n
1140         help
1141           Enable General-Purpose Wake-Up (Voltage Regulator Power-Up)
1142 endmenu
1143
1144 menu "CPU Frequency scaling"
1145
1146 source "drivers/cpufreq/Kconfig"
1147
1148 config BFIN_CPU_FREQ
1149         bool
1150         depends on CPU_FREQ
1151         select CPU_FREQ_TABLE
1152         default y
1153
1154 config CPU_VOLTAGE
1155         bool "CPU Voltage scaling"
1156         depends on EXPERIMENTAL
1157         depends on CPU_FREQ
1158         default n
1159         help
1160           Say Y here if you want CPU voltage scaling according to the CPU frequency.
1161           This option violates the PLL BYPASS recommendation in the Blackfin Processor
1162           manuals. There is a theoretical risk that during VDDINT transitions
1163           the PLL may unlock.
1164
1165 endmenu
1166
1167 source "net/Kconfig"
1168
1169 source "drivers/Kconfig"
1170
1171 source "fs/Kconfig"
1172
1173 source "arch/blackfin/Kconfig.debug"
1174
1175 source "security/Kconfig"
1176
1177 source "crypto/Kconfig"
1178
1179 source "lib/Kconfig"