arch/blackfin/Kconfig

   1 config SYMBOL_PREFIX
   2         string
   3         default "_"
   4
   5 config MMU
   6         def_bool n
   7
   8 config FPU
   9         def_bool n
  10
  11 config RWSEM_GENERIC_SPINLOCK
  12         def_bool y
  13
  14 config RWSEM_XCHGADD_ALGORITHM
  15         def_bool n
  16
  17 config BLACKFIN
  18         def_bool y
  19         select HAVE_ARCH_KGDB
  20         select HAVE_ARCH_TRACEHOOK
  21         select HAVE_DYNAMIC_FTRACE
  22         select HAVE_FTRACE_MCOUNT_RECORD
  23         select HAVE_FUNCTION_GRAPH_TRACER
  24         select HAVE_FUNCTION_TRACER
  25         select HAVE_FUNCTION_TRACE_MCOUNT_TEST
  26         select HAVE_IDE
  27         select HAVE_IRQ_WORK
  28         select HAVE_KERNEL_GZIP if RAMKERNEL
  29         select HAVE_KERNEL_BZIP2 if RAMKERNEL
  30         select HAVE_KERNEL_LZMA if RAMKERNEL
  31         select HAVE_KERNEL_LZO if RAMKERNEL
  32         select HAVE_OPROFILE
  33         select HAVE_PERF_EVENTS
  34         select ARCH_HAVE_CUSTOM_GPIO_H
  35         select ARCH_WANT_OPTIONAL_GPIOLIB
  36         select ARCH_WANT_IPC_PARSE_VERSION
  37         select HAVE_GENERIC_HARDIRQS
  38         select GENERIC_ATOMIC64
  39         select GENERIC_IRQ_PROBE
  40         select IRQ_PER_CPU if SMP
  41         select HAVE_NMI_WATCHDOG if NMI_WATCHDOG
  42         select GENERIC_SMP_IDLE_THREAD
  43         select ARCH_USES_GETTIMEOFFSET if !GENERIC_CLOCKEVENTS
  44
  45 config GENERIC_CSUM
  46         def_bool y
  47
  48 config GENERIC_BUG
  49         def_bool y
  50         depends on BUG
  51
  52 config ZONE_DMA
  53         def_bool y
  54
  55 config GENERIC_GPIO
  56         def_bool y
  57
  58 config FORCE_MAX_ZONEORDER
  59         int
  60         default "14"
  61
  62 config GENERIC_CALIBRATE_DELAY
  63         def_bool y
  64
  65 config LOCKDEP_SUPPORT
  66         def_bool y
  67
  68 config STACKTRACE_SUPPORT
  69         def_bool y
  70
  71 config TRACE_IRQFLAGS_SUPPORT
  72         def_bool y
  73
  74 source "init/Kconfig"
  75
  76 source "kernel/Kconfig.preempt"
  77
  78 source "kernel/Kconfig.freezer"
  79
  80 menu "Blackfin Processor Options"
  81
  82 comment "Processor and Board Settings"
  83
  84 choice
  85         prompt "CPU"
  86         default BF533
  87
  88 config BF512
  89         bool "BF512"
  90         help
  91           BF512 Processor Support.
  92
  93 config BF514
  94         bool "BF514"
  95         help
  96           BF514 Processor Support.
  97
  98 config BF516
  99         bool "BF516"
 100         help
 101           BF516 Processor Support.
 102
 103 config BF518
 104         bool "BF518"
 105         help
 106           BF518 Processor Support.
 107
 108 config BF522
 109         bool "BF522"
 110         help
 111           BF522 Processor Support.
 112
 113 config BF523
 114         bool "BF523"
 115         help
 116           BF523 Processor Support.
 117
 118 config BF524
 119         bool "BF524"
 120         help
 121           BF524 Processor Support.
 122
 123 config BF525
 124         bool "BF525"
 125         help
 126           BF525 Processor Support.
 127
 128 config BF526
 129         bool "BF526"
 130         help
 131           BF526 Processor Support.
 132
 133 config BF527
 134         bool "BF527"
 135         help
 136           BF527 Processor Support.
 137
 138 config BF531
 139         bool "BF531"
 140         help
 141           BF531 Processor Support.
 142
 143 config BF532
 144         bool "BF532"
 145         help
 146           BF532 Processor Support.
 147
 148 config BF533
 149         bool "BF533"
 150         help
 151           BF533 Processor Support.
 152
 153 config BF534
 154         bool "BF534"
 155         help
 156           BF534 Processor Support.
 157
 158 config BF536
 159         bool "BF536"
 160         help
 161           BF536 Processor Support.
 162
 163 config BF537
 164         bool "BF537"
 165         help
 166           BF537 Processor Support.
 167
 168 config BF538
 169         bool "BF538"
 170         help
 171           BF538 Processor Support.
 172
 173 config BF539
 174         bool "BF539"
 175         help
 176           BF539 Processor Support.
 177
 178 config BF542_std
 179         bool "BF542"
 180         help
 181           BF542 Processor Support.
 182
 183 config BF542M
 184         bool "BF542m"
 185         help
 186           BF542 Processor Support.
 187
 188 config BF544_std
 189         bool "BF544"
 190         help
 191           BF544 Processor Support.
 192
 193 config BF544M
 194         bool "BF544m"
 195         help
 196           BF544 Processor Support.
 197
 198 config BF547_std
 199         bool "BF547"
 200         help
 201           BF547 Processor Support.
 202
 203 config BF547M
 204         bool "BF547m"
 205         help
 206           BF547 Processor Support.
 207
 208 config BF548_std
 209         bool "BF548"
 210         help
 211           BF548 Processor Support.
 212
 213 config BF548M
 214         bool "BF548m"
 215         help
 216           BF548 Processor Support.
 217
 218 config BF549_std
 219         bool "BF549"
 220         help
 221           BF549 Processor Support.
 222
 223 config BF549M
 224         bool "BF549m"
 225         help
 226           BF549 Processor Support.
 227
 228 config BF561
 229         bool "BF561"
 230         help
 231           BF561 Processor Support.
 232
 233 config BF609
 234         bool "BF609"
 235         select CLKDEV_LOOKUP
 236         help
 237           BF609 Processor Support.
 238
 239 endchoice
 240
 241 config SMP
 242         depends on BF561
 243         select TICKSOURCE_CORETMR
 244         bool "Symmetric multi-processing support"
 245         ---help---
 246           This enables support for systems with more than one CPU,
 247           like the dual core BF561. If you have a system with only one
 248           CPU, say N. If you have a system with more than one CPU, say Y.
 249
 250           If you don't know what to do here, say N.
 251
 252 config NR_CPUS
 253         int
 254         depends on SMP
 255         default 2 if BF561
 256
 257 config HOTPLUG_CPU
 258         bool "Support for hot-pluggable CPUs"
 259         depends on SMP && HOTPLUG
 260         default y
 261
 262 config BF_REV_MIN
 263         int
 264         default 0 if (BF51x || BF52x || (BF54x && !BF54xM)) || BF60x
 265         default 2 if (BF537 || BF536 || BF534)
 266         default 3 if (BF561 || BF533 || BF532 || BF531 || BF54xM)
 267         default 4 if (BF538 || BF539)
 268
 269 config BF_REV_MAX
 270         int
 271         default 2 if (BF51x || BF52x || (BF54x && !BF54xM)) || BF60x
 272         default 3 if (BF537 || BF536 || BF534 || BF54xM)
 273         default 5 if (BF561 || BF538 || BF539)
 274         default 6 if (BF533 || BF532 || BF531)
 275
 276 choice
 277         prompt "Silicon Rev"
 278         default BF_REV_0_0 if (BF51x || BF52x || BF60x)
 279         default BF_REV_0_2 if (BF534 || BF536 || BF537 || (BF54x && !BF54xM))
 280         default BF_REV_0_3 if (BF531 || BF532 || BF533 || BF54xM || BF561)
 281
 282 config BF_REV_0_0
 283         bool "0.0"
 284         depends on (BF51x || BF52x || (BF54x && !BF54xM) || BF60x)
 285
 286 config BF_REV_0_1
 287         bool "0.1"
 288         depends on (BF51x || BF52x || (BF54x && !BF54xM))
 289
 290 config BF_REV_0_2
 291         bool "0.2"
 292         depends on (BF51x || BF52x || BF537 || BF536 || BF534 || (BF54x && !BF54xM))
 293
 294 config BF_REV_0_3
 295         bool "0.3"
 296         depends on (BF54xM || BF561 || BF537 || BF536 || BF534 || BF533 || BF532 || BF531)
 297
 298 config BF_REV_0_4
 299         bool "0.4"
 300         depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539)
 301
 302 config BF_REV_0_5
 303         bool "0.5"
 304         depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539)
 305
 306 config BF_REV_0_6
 307         bool "0.6"
 308         depends on (BF533 || BF532 || BF531)
 309
 310 config BF_REV_ANY
 311         bool "any"
 312
 313 config BF_REV_NONE
 314         bool "none"
 315
 316 endchoice
 317
 318 config BF53x
 319         bool
 320         depends on (BF531 || BF532 || BF533 || BF534 || BF536 || BF537)
 321         default y
 322
 323 config MEM_MT48LC64M4A2FB_7E
 324         bool
 325         depends on (BFIN533_STAMP)
 326         default y
 327
 328 config MEM_MT48LC16M16A2TG_75
 329         bool
 330         depends on (BFIN533_EZKIT || BFIN561_EZKIT \
 331                 || BFIN533_BLUETECHNIX_CM || BFIN537_BLUETECHNIX_CM_E \
 332                 || BFIN537_BLUETECHNIX_CM_U || H8606_HVSISTEMAS \
 333                 || BFIN527_BLUETECHNIX_CM)
 334         default y
 335
 336 config MEM_MT48LC32M8A2_75
 337         bool
 338         depends on (BFIN518F_EZBRD || BFIN537_STAMP || PNAV10 || BFIN538_EZKIT)
 339         default y
 340
 341 config MEM_MT48LC8M32B2B5_7
 342         bool
 343         depends on (BFIN561_BLUETECHNIX_CM)
 344         default y
 345
 346 config MEM_MT48LC32M16A2TG_75
 347         bool
 348         depends on (BFIN527_EZKIT || BFIN527_EZKIT_V2 || BFIN532_IP0X || BLACKSTAMP || BFIN527_AD7160EVAL)
 349         default y
 350
 351 config MEM_MT48H32M16LFCJ_75
 352         bool
 353         depends on (BFIN526_EZBRD)
 354         default y
 355
 356 config MEM_MT47H64M16
 357         bool
 358         depends on (BFIN609_EZKIT)
 359         default y
 360
 361 source "arch/blackfin/mach-bf518/Kconfig"
 362 source "arch/blackfin/mach-bf527/Kconfig"
 363 source "arch/blackfin/mach-bf533/Kconfig"
 364 source "arch/blackfin/mach-bf561/Kconfig"
 365 source "arch/blackfin/mach-bf537/Kconfig"
 366 source "arch/blackfin/mach-bf538/Kconfig"
 367 source "arch/blackfin/mach-bf548/Kconfig"
 368 source "arch/blackfin/mach-bf609/Kconfig"
 369
 370 menu "Board customizations"
 371
 372 config CMDLINE_BOOL
 373         bool "Default bootloader kernel arguments"
 374
 375 config CMDLINE
 376         string "Initial kernel command string"
 377         depends on CMDLINE_BOOL
 378         default "console=ttyBF0,57600"
 379         help
 380           If you don't have a boot loader capable of passing a command line string
 381           to the kernel, you may specify one here. As a minimum, you should specify
 382           the memory size and the root device (e.g., mem=8M, root=/dev/nfs).
 383
 384 config BOOT_LOAD
 385         hex "Kernel load address for booting"
 386         default "0x1000"
 387         range 0x1000 0x20000000
 388         help
 389           This option allows you to set the load address of the kernel.
 390           This can be useful if you are on a board which has a small amount
 391           of memory or you wish to reserve some memory at the beginning of
 392           the address space.
 393
 394           Note that you need to keep this value above 4k (0x1000) as this
 395           memory region is used to capture NULL pointer references as well
 396           as some core kernel functions.
 397
 398 config PHY_RAM_BASE_ADDRESS
 399         hex "Physical RAM Base"
 400         default 0x0
 401         help
 402           set BF609 FPGA physical SRAM base address
 403
 404 config ROM_BASE
 405         hex "Kernel ROM Base"
 406         depends on ROMKERNEL
 407         default "0x20040040"
 408         range 0x20000000 0x20400000 if !(BF54x || BF561 || BF60x)
 409         range 0x20000000 0x30000000 if (BF54x || BF561)
 410         range 0xB0000000 0xC0000000 if (BF60x)
 411         help
 412           Make sure your ROM base does not include any file-header
 413           information that is prepended to the kernel.
 414
 415           For example, the bootable U-Boot format (created with
 416           mkimage) has a 64 byte header (0x40).  So while the image
 417           you write to flash might start at say 0x20080000, you have
 418           to add 0x40 to get the kernel's ROM base as it will come
 419           after the header.
 420
 421 comment "Clock/PLL Setup"
 422
 423 config CLKIN_HZ
 424         int "Frequency of the crystal on the board in Hz"
 425         default "10000000" if BFIN532_IP0X
 426         default "11059200" if BFIN533_STAMP
 427         default "24576000" if PNAV10
 428         default "25000000" # most people use this
 429         default "27000000" if BFIN533_EZKIT
 430         default "30000000" if BFIN561_EZKIT
 431         default "24000000" if BFIN527_AD7160EVAL
 432         help
 433           The frequency of CLKIN crystal oscillator on the board in Hz.
 434           Warning: This value should match the crystal on the board. Otherwise,
 435           peripherals won't work properly.
 436
 437 config BFIN_KERNEL_CLOCK
 438         bool "Re-program Clocks while Kernel boots?"
 439         default n
 440         help
 441           This option decides if kernel clocks are re-programed from the
 442           bootloader settings. If the clocks are not set, the SDRAM settings
 443           are also not changed, and the Bootloader does 100% of the hardware
 444           configuration.
 445
 446 config PLL_BYPASS
 447         bool "Bypass PLL"
 448         depends on BFIN_KERNEL_CLOCK && (!BF60x)
 449         default n
 450
 451 config CLKIN_HALF
 452         bool "Half Clock In"
 453         depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
 454         default n
 455         help
 456           If this is set the clock will be divided by 2, before it goes to the PLL.
 457
 458 config VCO_MULT
 459         int "VCO Multiplier"
 460         depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
 461         range 1 64
 462         default "22" if BFIN533_EZKIT
 463         default "45" if BFIN533_STAMP
 464         default "20" if (BFIN537_STAMP || BFIN527_EZKIT || BFIN527_EZKIT_V2 || BFIN548_EZKIT || BFIN548_BLUETECHNIX_CM || BFIN538_EZKIT)
 465         default "22" if BFIN533_BLUETECHNIX_CM
 466         default "20" if (BFIN537_BLUETECHNIX_CM_E || BFIN537_BLUETECHNIX_CM_U || BFIN527_BLUETECHNIX_CM || BFIN561_BLUETECHNIX_CM)
 467         default "20" if (BFIN561_EZKIT || BF609)
 468         default "16" if (H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD || BFIN518F_EZBRD)
 469         default "25" if BFIN527_AD7160EVAL
 470         help
 471           This controls the frequency of the on-chip PLL. This can be between 1 and 64.
 472           PLL Frequency = (Crystal Frequency) * (this setting)
 473
 474 choice
 475         prompt "Core Clock Divider"
 476         depends on BFIN_KERNEL_CLOCK
 477         default CCLK_DIV_1
 478         help
 479           This sets the frequency of the core. It can be 1, 2, 4 or 8
 480           Core Frequency = (PLL frequency) / (this setting)
 481
 482 config CCLK_DIV_1
 483         bool "1"
 484
 485 config CCLK_DIV_2
 486         bool "2"
 487
 488 config CCLK_DIV_4
 489         bool "4"
 490
 491 config CCLK_DIV_8
 492         bool "8"
 493 endchoice
 494
 495 config SCLK_DIV
 496         int "System Clock Divider"
 497         depends on BFIN_KERNEL_CLOCK
 498         range 1 15
 499         default 4
 500         help
 501           This sets the frequency of the system clock (including SDRAM or DDR) on
 502           !BF60x else it set the clock for system buses and provides the
 503           source from which SCLK0 and SCLK1 are derived.
 504           This can be between 1 and 15
 505           System Clock = (PLL frequency) / (this setting)
 506
 507 config SCLK0_DIV
 508         int "System Clock0 Divider"
 509         depends on BFIN_KERNEL_CLOCK && BF60x
 510         range 1 15
 511         default 1
 512         help
 513           This sets the frequency of the system clock0 for PVP and all other
 514           peripherals not clocked by SCLK1.
 515           This can be between 1 and 15
 516           System Clock0 = (System Clock) / (this setting)
 517
 518 config SCLK1_DIV
 519         int "System Clock1 Divider"
 520         depends on BFIN_KERNEL_CLOCK && BF60x
 521         range 1 15
 522         default 1
 523         help
 524           This sets the frequency of the system clock1 (including SPORT, SPI and ACM).
 525           This can be between 1 and 15
 526           System Clock1 = (System Clock) / (this setting)
 527
 528 config DCLK_DIV
 529         int "DDR Clock Divider"
 530         depends on BFIN_KERNEL_CLOCK && BF60x
 531         range 1 15
 532         default 2
 533         help
 534           This sets the frequency of the DDR memory.
 535           This can be between 1 and 15
 536           DDR Clock = (PLL frequency) / (this setting)
 537
 538 choice
 539         prompt "DDR SDRAM Chip Type"
 540         depends on BFIN_KERNEL_CLOCK
 541         depends on BF54x
 542         default MEM_MT46V32M16_5B
 543
 544 config MEM_MT46V32M16_6T
 545         bool "MT46V32M16_6T"
 546
 547 config MEM_MT46V32M16_5B
 548         bool "MT46V32M16_5B"
 549 endchoice
 550
 551 choice
 552         prompt "DDR/SDRAM Timing"
 553         depends on BFIN_KERNEL_CLOCK && !BF60x
 554         default BFIN_KERNEL_CLOCK_MEMINIT_CALC
 555         help
 556           This option allows you to specify Blackfin SDRAM/DDR Timing parameters
 557           The calculated SDRAM timing parameters may not be 100%
 558           accurate - This option is therefore marked experimental.
 559
 560 config BFIN_KERNEL_CLOCK_MEMINIT_CALC
 561         bool "Calculate Timings (EXPERIMENTAL)"
 562         depends on EXPERIMENTAL
 563
 564 config BFIN_KERNEL_CLOCK_MEMINIT_SPEC
 565         bool "Provide accurate Timings based on target SCLK"
 566         help
 567           Please consult the Blackfin Hardware Reference Manuals as well
 568           as the memory device datasheet.
 569           http://docs.blackfin.uclinux.org/doku.php?id=bfin:sdram
 570 endchoice
 571
 572 menu "Memory Init Control"
 573         depends on BFIN_KERNEL_CLOCK_MEMINIT_SPEC
 574
 575 config MEM_DDRCTL0
 576         depends on BF54x
 577         hex "DDRCTL0"
 578         default 0x0
 579
 580 config MEM_DDRCTL1
 581         depends on BF54x
 582         hex "DDRCTL1"
 583         default 0x0
 584
 585 config MEM_DDRCTL2
 586         depends on BF54x
 587         hex "DDRCTL2"
 588         default 0x0
 589
 590 config MEM_EBIU_DDRQUE
 591         depends on BF54x
 592         hex "DDRQUE"
 593         default 0x0
 594
 595 config MEM_SDRRC
 596         depends on !BF54x
 597         hex "SDRRC"
 598         default 0x0
 599
 600 config MEM_SDGCTL
 601         depends on !BF54x
 602         hex "SDGCTL"
 603         default 0x0
 604 endmenu
 605
 606 #
 607 # Max & Min Speeds for various Chips
 608 #
 609 config MAX_VCO_HZ
 610         int
 611         default 400000000 if BF512
 612         default 400000000 if BF514
 613         default 400000000 if BF516
 614         default 400000000 if BF518
 615         default 400000000 if BF522
 616         default 600000000 if BF523
 617         default 400000000 if BF524
 618         default 600000000 if BF525
 619         default 400000000 if BF526
 620         default 600000000 if BF527
 621         default 400000000 if BF531
 622         default 400000000 if BF532
 623         default 750000000 if BF533
 624         default 500000000 if BF534
 625         default 400000000 if BF536
 626         default 600000000 if BF537
 627         default 533333333 if BF538
 628         default 533333333 if BF539
 629         default 600000000 if BF542
 630         default 533333333 if BF544
 631         default 600000000 if BF547
 632         default 600000000 if BF548
 633         default 533333333 if BF549
 634         default 600000000 if BF561
 635         default 800000000 if BF609
 636
 637 config MIN_VCO_HZ
 638         int
 639         default 50000000
 640
 641 config MAX_SCLK_HZ
 642         int
 643         default 200000000 if BF609
 644         default 133333333
 645
 646 config MIN_SCLK_HZ
 647         int
 648         default 27000000
 649
 650 comment "Kernel Timer/Scheduler"
 651
 652 source kernel/Kconfig.hz
 653
 654 config SET_GENERIC_CLOCKEVENTS
 655         bool "Generic clock events"
 656         default y
 657         select GENERIC_CLOCKEVENTS
 658
 659 menu "Clock event device"
 660         depends on GENERIC_CLOCKEVENTS
 661 config TICKSOURCE_GPTMR0
 662         bool "GPTimer0"
 663         depends on !SMP
 664         select BFIN_GPTIMERS
 665
 666 config TICKSOURCE_CORETMR
 667         bool "Core timer"
 668         default y
 669 endmenu
 670
 671 menu "Clock souce"
 672         depends on GENERIC_CLOCKEVENTS
 673 config CYCLES_CLOCKSOURCE
 674         bool "CYCLES"
 675         default y
 676         depends on !BFIN_SCRATCH_REG_CYCLES
 677         depends on !SMP
 678         help
 679           If you say Y here, you will enable support for using the 'cycles'
 680           registers as a clock source.  Doing so means you will be unable to
 681           safely write to the 'cycles' register during runtime.  You will
 682           still be able to read it (such as for performance monitoring), but
 683           writing the registers will most likely crash the kernel.
 684
 685 config GPTMR0_CLOCKSOURCE
 686         bool "GPTimer0"
 687         select BFIN_GPTIMERS
 688         depends on !TICKSOURCE_GPTMR0
 689 endmenu
 690
 691 comment "Misc"
 692
 693 choice
 694         prompt "Blackfin Exception Scratch Register"
 695         default BFIN_SCRATCH_REG_RETN
 696         help
 697           Select the resource to reserve for the Exception handler:
 698             - RETN: Non-Maskable Interrupt (NMI)
 699             - RETE: Exception Return (JTAG/ICE)
 700             - CYCLES: Performance counter
 701
 702           If you are unsure, please select "RETN".
 703
 704 config BFIN_SCRATCH_REG_RETN
 705         bool "RETN"
 706         help
 707           Use the RETN register in the Blackfin exception handler
 708           as a stack scratch register.  This means you cannot
 709           safely use NMI on the Blackfin while running Linux, but
 710           you can debug the system with a JTAG ICE and use the
 711           CYCLES performance registers.
 712
 713           If you are unsure, please select "RETN".
 714
 715 config BFIN_SCRATCH_REG_RETE
 716         bool "RETE"
 717         help
 718           Use the RETE register in the Blackfin exception handler
 719           as a stack scratch register.  This means you cannot
 720           safely use a JTAG ICE while debugging a Blackfin board,
 721           but you can safely use the CYCLES performance registers
 722           and the NMI.
 723
 724           If you are unsure, please select "RETN".
 725
 726 config BFIN_SCRATCH_REG_CYCLES
 727         bool "CYCLES"
 728         help
 729           Use the CYCLES register in the Blackfin exception handler
 730           as a stack scratch register.  This means you cannot
 731           safely use the CYCLES performance registers on a Blackfin
 732           board at anytime, but you can debug the system with a JTAG
 733           ICE and use the NMI.
 734
 735           If you are unsure, please select "RETN".
 736
 737 endchoice
 738
 739 endmenu
 740
 741
 742 menu "Blackfin Kernel Optimizations"
 743
 744 comment "Memory Optimizations"
 745
 746 config I_ENTRY_L1
 747         bool "Locate interrupt entry code in L1 Memory"
 748         default y
 749         depends on !SMP
 750         help
 751           If enabled, interrupt entry code (STORE/RESTORE CONTEXT) is linked
 752           into L1 instruction memory. (less latency)
 753
 754 config EXCPT_IRQ_SYSC_L1
 755         bool "Locate entire ASM lowlevel exception / interrupt - Syscall and CPLB handler code in L1 Memory"
 756         default y
 757         depends on !SMP
 758         help
 759           If enabled, the entire ASM lowlevel exception and interrupt entry code
 760           (STORE/RESTORE CONTEXT) is linked into L1 instruction memory.
 761           (less latency)
 762
 763 config DO_IRQ_L1
 764         bool "Locate frequently called do_irq dispatcher function in L1 Memory"
 765         default y
 766         depends on !SMP
 767         help
 768           If enabled, the frequently called do_irq dispatcher function is linked
 769           into L1 instruction memory. (less latency)
 770
 771 config CORE_TIMER_IRQ_L1
 772         bool "Locate frequently called timer_interrupt() function in L1 Memory"
 773         default y
 774         depends on !SMP
 775         help
 776           If enabled, the frequently called timer_interrupt() function is linked
 777           into L1 instruction memory. (less latency)
 778
 779 config IDLE_L1
 780         bool "Locate frequently idle function in L1 Memory"
 781         default y
 782         depends on !SMP
 783         help
 784           If enabled, the frequently called idle function is linked
 785           into L1 instruction memory. (less latency)
 786
 787 config SCHEDULE_L1
 788         bool "Locate kernel schedule function in L1 Memory"
 789         default y
 790         depends on !SMP
 791         help
 792           If enabled, the frequently called kernel schedule is linked
 793           into L1 instruction memory. (less latency)
 794
 795 config ARITHMETIC_OPS_L1
 796         bool "Locate kernel owned arithmetic functions in L1 Memory"
 797         default y
 798         depends on !SMP
 799         help
 800           If enabled, arithmetic functions are linked
 801           into L1 instruction memory. (less latency)
 802
 803 config ACCESS_OK_L1
 804         bool "Locate access_ok function in L1 Memory"
 805         default y
 806         depends on !SMP
 807         help
 808           If enabled, the access_ok function is linked
 809           into L1 instruction memory. (less latency)
 810
 811 config MEMSET_L1
 812         bool "Locate memset function in L1 Memory"
 813         default y
 814         depends on !SMP
 815         help
 816           If enabled, the memset function is linked
 817           into L1 instruction memory. (less latency)
 818
 819 config MEMCPY_L1
 820         bool "Locate memcpy function in L1 Memory"
 821         default y
 822         depends on !SMP
 823         help
 824           If enabled, the memcpy function is linked
 825           into L1 instruction memory. (less latency)
 826
 827 config STRCMP_L1
 828         bool "locate strcmp function in L1 Memory"
 829         default y
 830         depends on !SMP
 831         help
 832           If enabled, the strcmp function is linked
 833           into L1 instruction memory (less latency).
 834
 835 config STRNCMP_L1
 836         bool "locate strncmp function in L1 Memory"
 837         default y
 838         depends on !SMP
 839         help
 840           If enabled, the strncmp function is linked
 841           into L1 instruction memory (less latency).
 842
 843 config STRCPY_L1
 844         bool "locate strcpy function in L1 Memory"
 845         default y
 846         depends on !SMP
 847         help
 848           If enabled, the strcpy function is linked
 849           into L1 instruction memory (less latency).
 850
 851 config STRNCPY_L1
 852         bool "locate strncpy function in L1 Memory"
 853         default y
 854         depends on !SMP
 855         help
 856           If enabled, the strncpy function is linked
 857           into L1 instruction memory (less latency).
 858
 859 config SYS_BFIN_SPINLOCK_L1
 860         bool "Locate sys_bfin_spinlock function in L1 Memory"
 861         default y
 862         depends on !SMP
 863         help
 864           If enabled, sys_bfin_spinlock function is linked
 865           into L1 instruction memory. (less latency)
 866
 867 config IP_CHECKSUM_L1
 868         bool "Locate IP Checksum function in L1 Memory"
 869         default n
 870         depends on !SMP
 871         help
 872           If enabled, the IP Checksum function is linked
 873           into L1 instruction memory. (less latency)
 874
 875 config CACHELINE_ALIGNED_L1
 876         bool "Locate cacheline_aligned data to L1 Data Memory"
 877         default y if !BF54x
 878         default n if BF54x
 879         depends on !SMP && !BF531 && !CRC32
 880         help
 881           If enabled, cacheline_aligned data is linked
 882           into L1 data memory. (less latency)
 883
 884 config SYSCALL_TAB_L1
 885         bool "Locate Syscall Table L1 Data Memory"
 886         default n
 887         depends on !SMP && !BF531
 888         help
 889           If enabled, the Syscall LUT is linked
 890           into L1 data memory. (less latency)
 891
 892 config CPLB_SWITCH_TAB_L1
 893         bool "Locate CPLB Switch Tables L1 Data Memory"
 894         default n
 895         depends on !SMP && !BF531
 896         help
 897           If enabled, the CPLB Switch Tables are linked
 898           into L1 data memory. (less latency)
 899
 900 config ICACHE_FLUSH_L1
 901         bool "Locate icache flush funcs in L1 Inst Memory"
 902         default y
 903         help
 904           If enabled, the Blackfin icache flushing functions are linked
 905           into L1 instruction memory.
 906
 907           Note that this might be required to address anomalies, but
 908           these functions are pretty small, so it shouldn't be too bad.
 909           If you are using a processor affected by an anomaly, the build
 910           system will double check for you and prevent it.
 911
 912 config DCACHE_FLUSH_L1
 913         bool "Locate dcache flush funcs in L1 Inst Memory"
 914         default y
 915         depends on !SMP
 916         help
 917           If enabled, the Blackfin dcache flushing functions are linked
 918           into L1 instruction memory.
 919
 920 config APP_STACK_L1
 921         bool "Support locating application stack in L1 Scratch Memory"
 922         default y
 923         depends on !SMP
 924         help
 925           If enabled the application stack can be located in L1
 926           scratch memory (less latency).
 927
 928           Currently only works with FLAT binaries.
 929
 930 config EXCEPTION_L1_SCRATCH
 931         bool "Locate exception stack in L1 Scratch Memory"
 932         default n
 933         depends on !SMP && !APP_STACK_L1
 934         help
 935           Whenever an exception occurs, use the L1 Scratch memory for
 936           stack storage.  You cannot place the stacks of FLAT binaries
 937           in L1 when using this option.
 938
 939           If you don't use L1 Scratch, then you should say Y here.
 940
 941 comment "Speed Optimizations"
 942 config BFIN_INS_LOWOVERHEAD
 943         bool "ins[bwl] low overhead, higher interrupt latency"
 944         default y
 945         depends on !SMP
 946         help
 947           Reads on the Blackfin are speculative. In Blackfin terms, this means
 948           they can be interrupted at any time (even after they have been issued
 949           on to the external bus), and re-issued after the interrupt occurs.
 950           For memory - this is not a big deal, since memory does not change if
 951           it sees a read.
 952
 953           If a FIFO is sitting on the end of the read, it will see two reads,
 954           when the core only sees one since the FIFO receives both the read
 955           which is cancelled (and not delivered to the core) and the one which
 956           is re-issued (which is delivered to the core).
 957
 958           To solve this, interrupts are turned off before reads occur to
 959           I/O space. This option controls which the overhead/latency of
 960           controlling interrupts during this time
 961            "n" turns interrupts off every read
 962                 (higher overhead, but lower interrupt latency)
 963            "y" turns interrupts off every loop
 964                 (low overhead, but longer interrupt latency)
 965
 966           default behavior is to leave this set to on (type "Y"). If you are experiencing
 967           interrupt latency issues, it is safe and OK to turn this off.
 968
 969 endmenu
 970
 971 choice
 972         prompt "Kernel executes from"
 973         help
 974           Choose the memory type that the kernel will be running in.
 975
 976 config RAMKERNEL
 977         bool "RAM"
 978         help
 979           The kernel will be resident in RAM when running.
 980
 981 config ROMKERNEL
 982         bool "ROM"
 983         help
 984           The kernel will be resident in FLASH/ROM when running.
 985
 986 endchoice
 987
 988 # Common code uses "ROMKERNEL" or "XIP_KERNEL", so define both
 989 config XIP_KERNEL
 990         bool
 991         default y
 992         depends on ROMKERNEL
 993
 994 source "mm/Kconfig"
 995
 996 config BFIN_GPTIMERS
 997         tristate "Enable Blackfin General Purpose Timers API"
 998         default n
 999         help
1000           Enable support for the General Purpose Timers API.  If you
1001           are unsure, say N.
1002
1003           To compile this driver as a module, choose M here: the module
1004           will be called gptimers.
1005
1006 config HAVE_PWM
1007         tristate "Enable PWM API support"
1008         depends on BFIN_GPTIMERS
1009         help
1010           Enable support for the Pulse Width Modulation framework (as
1011           found in linux/pwm.h).
1012
1013           To compile this driver as a module, choose M here: the module
1014           will be called pwm.
1015
1016 choice
1017         prompt "Uncached DMA region"
1018         default DMA_UNCACHED_1M
1019 config DMA_UNCACHED_32M
1020         bool "Enable 32M DMA region"
1021 config DMA_UNCACHED_16M
1022         bool "Enable 16M DMA region"
1023 config DMA_UNCACHED_8M
1024         bool "Enable 8M DMA region"
1025 config DMA_UNCACHED_4M
1026         bool "Enable 4M DMA region"
1027 config DMA_UNCACHED_2M
1028         bool "Enable 2M DMA region"
1029 config DMA_UNCACHED_1M
1030         bool "Enable 1M DMA region"
1031 config DMA_UNCACHED_512K
1032         bool "Enable 512K DMA region"
1033 config DMA_UNCACHED_256K
1034         bool "Enable 256K DMA region"
1035 config DMA_UNCACHED_128K
1036         bool "Enable 128K DMA region"
1037 config DMA_UNCACHED_NONE
1038         bool "Disable DMA region"
1039 endchoice
1040
1041
1042 comment "Cache Support"
1043
1044 config BFIN_ICACHE
1045         bool "Enable ICACHE"
1046         default y
1047 config BFIN_EXTMEM_ICACHEABLE
1048         bool "Enable ICACHE for external memory"
1049         depends on BFIN_ICACHE
1050         default y
1051 config BFIN_L2_ICACHEABLE
1052         bool "Enable ICACHE for L2 SRAM"
1053         depends on BFIN_ICACHE
1054         depends on (BF54x || BF561 || BF60x) && !SMP
1055         default n
1056
1057 config BFIN_DCACHE
1058         bool "Enable DCACHE"
1059         default y
1060 config BFIN_DCACHE_BANKA
1061         bool "Enable only 16k BankA DCACHE - BankB is SRAM"
1062         depends on BFIN_DCACHE && !BF531
1063         default n
1064 config BFIN_EXTMEM_DCACHEABLE
1065         bool "Enable DCACHE for external memory"
1066         depends on BFIN_DCACHE
1067         default y
1068 choice
1069         prompt "External memory DCACHE policy"
1070         depends on BFIN_EXTMEM_DCACHEABLE
1071         default BFIN_EXTMEM_WRITEBACK if !SMP
1072         default BFIN_EXTMEM_WRITETHROUGH if SMP
1073 config BFIN_EXTMEM_WRITEBACK
1074         bool "Write back"
1075         depends on !SMP
1076         help
1077           Write Back Policy:
1078             Cached data will be written back to SDRAM only when needed.
1079             This can give a nice increase in performance, but beware of
1080             broken drivers that do not properly invalidate/flush their
1081             cache.
1082
1083           Write Through Policy:
1084             Cached data will always be written back to SDRAM when the
1085             cache is updated.  This is a completely safe setting, but
1086             performance is worse than Write Back.
1087
1088           If you are unsure of the options and you want to be safe,
1089           then go with Write Through.
1090
1091 config BFIN_EXTMEM_WRITETHROUGH
1092         bool "Write through"
1093         help
1094           Write Back Policy:
1095             Cached data will be written back to SDRAM only when needed.
1096             This can give a nice increase in performance, but beware of
1097             broken drivers that do not properly invalidate/flush their
1098             cache.
1099
1100           Write Through Policy:
1101             Cached data will always be written back to SDRAM when the
1102             cache is updated.  This is a completely safe setting, but
1103             performance is worse than Write Back.
1104
1105           If you are unsure of the options and you want to be safe,
1106           then go with Write Through.
1107
1108 endchoice
1109
1110 config BFIN_L2_DCACHEABLE
1111         bool "Enable DCACHE for L2 SRAM"
1112         depends on BFIN_DCACHE
1113         depends on (BF54x || BF561 || BF60x) && !SMP
1114         default n
1115 choice
1116         prompt "L2 SRAM DCACHE policy"
1117         depends on BFIN_L2_DCACHEABLE
1118         default BFIN_L2_WRITEBACK
1119 config BFIN_L2_WRITEBACK
1120         bool "Write back"
1121
1122 config BFIN_L2_WRITETHROUGH
1123         bool "Write through"
1124 endchoice
1125
1126
1127 comment "Memory Protection Unit"
1128 config MPU
1129         bool "Enable the memory protection unit (EXPERIMENTAL)"
1130         default n
1131         help
1132           Use the processor's MPU to protect applications from accessing
1133           memory they do not own.  This comes at a performance penalty
1134           and is recommended only for debugging.
1135
1136 comment "Asynchronous Memory Configuration"
1137
1138 menu "EBIU_AMGCTL Global Control"
1139         depends on !BF60x
1140 config C_AMCKEN
1141         bool "Enable CLKOUT"
1142         default y
1143
1144 config C_CDPRIO
1145         bool "DMA has priority over core for ext. accesses"
1146         default n
1147
1148 config C_B0PEN
1149         depends on BF561
1150         bool "Bank 0 16 bit packing enable"
1151         default y
1152
1153 config C_B1PEN
1154         depends on BF561
1155         bool "Bank 1 16 bit packing enable"
1156         default y
1157
1158 config C_B2PEN
1159         depends on BF561
1160         bool "Bank 2 16 bit packing enable"
1161         default y
1162
1163 config C_B3PEN
1164         depends on BF561
1165         bool "Bank 3 16 bit packing enable"
1166         default n
1167
1168 choice
1169         prompt "Enable Asynchronous Memory Banks"
1170         default C_AMBEN_ALL
1171
1172 config C_AMBEN
1173         bool "Disable All Banks"
1174
1175 config C_AMBEN_B0
1176         bool "Enable Bank 0"
1177
1178 config C_AMBEN_B0_B1
1179         bool "Enable Bank 0 & 1"
1180
1181 config C_AMBEN_B0_B1_B2
1182         bool "Enable Bank 0 & 1 & 2"
1183
1184 config C_AMBEN_ALL
1185         bool "Enable All Banks"
1186 endchoice
1187 endmenu
1188
1189 menu "EBIU_AMBCTL Control"
1190         depends on !BF60x
1191 config BANK_0
1192         hex "Bank 0 (AMBCTL0.L)"
1193         default 0x7BB0
1194         help
1195           These are the low 16 bits of the EBIU_AMBCTL0 MMR which are
1196           used to control the Asynchronous Memory Bank 0 settings.
1197
1198 config BANK_1
1199         hex "Bank 1 (AMBCTL0.H)"
1200         default 0x7BB0
1201         default 0x5558 if BF54x
1202         help
1203           These are the high 16 bits of the EBIU_AMBCTL0 MMR which are
1204           used to control the Asynchronous Memory Bank 1 settings.
1205
1206 config BANK_2
1207         hex "Bank 2 (AMBCTL1.L)"
1208         default 0x7BB0
1209         help
1210           These are the low 16 bits of the EBIU_AMBCTL1 MMR which are
1211           used to control the Asynchronous Memory Bank 2 settings.
1212
1213 config BANK_3
1214         hex "Bank 3 (AMBCTL1.H)"
1215         default 0x99B3
1216         help
1217           These are the high 16 bits of the EBIU_AMBCTL1 MMR which are
1218           used to control the Asynchronous Memory Bank 3 settings.
1219
1220 endmenu
1221
1222 config EBIU_MBSCTLVAL
1223         hex "EBIU Bank Select Control Register"
1224         depends on BF54x
1225         default 0
1226
1227 config EBIU_MODEVAL
1228         hex "Flash Memory Mode Control Register"
1229         depends on BF54x
1230         default 1
1231
1232 config EBIU_FCTLVAL
1233         hex "Flash Memory Bank Control Register"
1234         depends on BF54x
1235         default 6
1236 endmenu
1237
1238 #############################################################################
1239 menu "Bus options (PCI, PCMCIA, EISA, MCA, ISA)"
1240
1241 config PCI
1242         bool "PCI support"
1243         depends on BROKEN
1244         help
1245           Support for PCI bus.
1246
1247 source "drivers/pci/Kconfig"
1248
1249 source "drivers/pcmcia/Kconfig"
1250
1251 source "drivers/pci/hotplug/Kconfig"
1252
1253 endmenu
1254
1255 menu "Executable file formats"
1256
1257 source "fs/Kconfig.binfmt"
1258
1259 endmenu
1260
1261 menu "Power management options"
1262
1263 source "kernel/power/Kconfig"
1264
1265 config ARCH_SUSPEND_POSSIBLE
1266         def_bool y
1267
1268 choice
1269         prompt "Standby Power Saving Mode"
1270         depends on PM && !BF60x
1271         default PM_BFIN_SLEEP_DEEPER
1272 config  PM_BFIN_SLEEP_DEEPER
1273         bool "Sleep Deeper"
1274         help
1275           Sleep "Deeper" Mode (High Power Savings) - This mode reduces dynamic
1276           power dissipation by disabling the clock to the processor core (CCLK).
1277           Furthermore, Standby sets the internal power supply voltage (VDDINT)
1278           to 0.85 V to provide the greatest power savings, while preserving the
1279           processor state.
1280           The PLL and system clock (SCLK) continue to operate at a very low
1281           frequency of about 3.3 MHz. To preserve data integrity in the SDRAM,
1282           the SDRAM is put into Self Refresh Mode. Typically an external event
1283           such as GPIO interrupt or RTC activity wakes up the processor.
1284           Various Peripherals such as UART, SPORT, PPI may not function as
1285           normal during Sleep Deeper, due to the reduced SCLK frequency.
1286           When in the sleep mode, system DMA access to L1 memory is not supported.
1287
1288           If unsure, select "Sleep Deeper".
1289
1290 config  PM_BFIN_SLEEP
1291         bool "Sleep"
1292         help
1293           Sleep Mode (High Power Savings) - The sleep mode reduces power
1294           dissipation by disabling the clock to the processor core (CCLK).
1295           The PLL and system clock (SCLK), however, continue to operate in
1296           this mode. Typically an external event or RTC activity will wake
1297           up the processor. When in the sleep mode, system DMA access to L1
1298           memory is not supported.
1299
1300           If unsure, select "Sleep Deeper".
1301 endchoice
1302
1303 comment "Possible Suspend Mem / Hibernate Wake-Up Sources"
1304         depends on PM
1305
1306 config PM_BFIN_WAKE_PH6
1307         bool "Allow Wake-Up from on-chip PHY or PH6 GP"
1308         depends on PM && (BF51x || BF52x || BF534 || BF536 || BF537)
1309         default n
1310         help
1311           Enable PHY and PH6 GP Wake-Up (Voltage Regulator Power-Up)
1312
1313 config PM_BFIN_WAKE_GP
1314         bool "Allow Wake-Up from GPIOs"
1315         depends on PM && BF54x
1316         default n
1317         help
1318           Enable General-Purpose Wake-Up (Voltage Regulator Power-Up)
1319           (all processors, except ADSP-BF549). This option sets
1320           the general-purpose wake-up enable (GPWE) control bit to enable
1321           wake-up upon detection of an active low signal on the /GPW (PH7) pin.
1322           On ADSP-BF549 this option enables the same functionality on the
1323           /MRXON pin also PH7.
1324
1325 config PM_BFIN_WAKE_PA15
1326         bool "Allow Wake-Up from PA15"
1327         depends on PM && BF60x
1328         default n
1329         help
1330           Enable PA15 Wake-Up
1331
1332 config PM_BFIN_WAKE_PA15_POL
1333         int "Wake-up priority"
1334         depends on PM_BFIN_WAKE_PA15
1335         default 0
1336         help
1337           Wake-Up priority 0(low) 1(high)
1338
1339 config PM_BFIN_WAKE_PB15
1340         bool "Allow Wake-Up from PB15"
1341         depends on PM && BF60x
1342         default n
1343         help
1344           Enable PB15 Wake-Up
1345
1346 config PM_BFIN_WAKE_PB15_POL
1347         int "Wake-up priority"
1348         depends on PM_BFIN_WAKE_PB15
1349         default 0
1350         help
1351           Wake-Up priority 0(low) 1(high)
1352
1353 config PM_BFIN_WAKE_PC15
1354         bool "Allow Wake-Up from PC15"
1355         depends on PM && BF60x
1356         default n
1357         help
1358           Enable PC15 Wake-Up
1359
1360 config PM_BFIN_WAKE_PC15_POL
1361         int "Wake-up priority"
1362         depends on PM_BFIN_WAKE_PC15
1363         default 0
1364         help
1365           Wake-Up priority 0(low) 1(high)
1366
1367 config PM_BFIN_WAKE_PD06
1368         bool "Allow Wake-Up from PD06(ETH0_PHYINT)"
1369         depends on PM && BF60x
1370         default n
1371         help
1372           Enable PD06(ETH0_PHYINT) Wake-up
1373
1374 config PM_BFIN_WAKE_PD06_POL
1375         int "Wake-up priority"
1376         depends on PM_BFIN_WAKE_PD06
1377         default 0
1378         help
1379           Wake-Up priority 0(low) 1(high)
1380
1381 config PM_BFIN_WAKE_PE12
1382         bool "Allow Wake-Up from PE12(ETH1_PHYINT, PUSH BUTTON)"
1383         depends on PM && BF60x
1384         default n
1385         help
1386           Enable PE12(ETH1_PHYINT, PUSH BUTTON) Wake-up
1387
1388 config PM_BFIN_WAKE_PE12_POL
1389         int "Wake-up priority"
1390         depends on PM_BFIN_WAKE_PE12
1391         default 0
1392         help
1393           Wake-Up priority 0(low) 1(high)
1394
1395 config PM_BFIN_WAKE_PG04
1396         bool "Allow Wake-Up from PG04(CAN0_RX)"
1397         depends on PM && BF60x
1398         default n
1399         help
1400           Enable PG04(CAN0_RX) Wake-up
1401
1402 config PM_BFIN_WAKE_PG04_POL
1403         int "Wake-up priority"
1404         depends on PM_BFIN_WAKE_PG04
1405         default 0
1406         help
1407           Wake-Up priority 0(low) 1(high)
1408
1409 config PM_BFIN_WAKE_PG13
1410         bool "Allow Wake-Up from PG13"
1411         depends on PM && BF60x
1412         default n
1413         help
1414           Enable PG13 Wake-Up
1415
1416 config PM_BFIN_WAKE_PG13_POL
1417         int "Wake-up priority"
1418         depends on PM_BFIN_WAKE_PG13
1419         default 0
1420         help
1421           Wake-Up priority 0(low) 1(high)
1422
1423 config PM_BFIN_WAKE_USB
1424         bool "Allow Wake-Up from (USB)"
1425         depends on PM && BF60x
1426         default n
1427         help
1428           Enable (USB) Wake-up
1429
1430 config PM_BFIN_WAKE_USB_POL
1431         int "Wake-up priority"
1432         depends on PM_BFIN_WAKE_USB
1433         default 0
1434         help
1435           Wake-Up priority 0(low) 1(high)
1436
1437 endmenu
1438
1439 menu "CPU Frequency scaling"
1440
1441 source "drivers/cpufreq/Kconfig"
1442
1443 config BFIN_CPU_FREQ
1444         bool
1445         depends on CPU_FREQ
1446         select CPU_FREQ_TABLE
1447         default y
1448
1449 config CPU_VOLTAGE
1450         bool "CPU Voltage scaling"
1451         depends on EXPERIMENTAL
1452         depends on CPU_FREQ
1453         default n
1454         help
1455           Say Y here if you want CPU voltage scaling according to the CPU frequency.
1456           This option violates the PLL BYPASS recommendation in the Blackfin Processor
1457           manuals. There is a theoretical risk that during VDDINT transitions
1458           the PLL may unlock.
1459
1460 endmenu
1461
1462 source "net/Kconfig"
1463
1464 source "drivers/Kconfig"
1465
1466 source "drivers/firmware/Kconfig"
1467
1468 source "fs/Kconfig"
1469
1470 source "arch/blackfin/Kconfig.debug"
1471
1472 source "security/Kconfig"
1473
1474 source "crypto/Kconfig"
1475
1476 source "lib/Kconfig"