arch/blackfin/Kconfig

   1 config SYMBOL_PREFIX
   2         string
   3         default "_"
   4
   5 config MMU
   6         def_bool n
   7
   8 config FPU
   9         def_bool n
  10
  11 config RWSEM_GENERIC_SPINLOCK
  12         def_bool y
  13
  14 config RWSEM_XCHGADD_ALGORITHM
  15         def_bool n
  16
  17 config BLACKFIN
  18         def_bool y
  19         select HAVE_ARCH_KGDB
  20         select HAVE_ARCH_TRACEHOOK
  21         select HAVE_DYNAMIC_FTRACE
  22         select HAVE_FTRACE_MCOUNT_RECORD
  23         select HAVE_FUNCTION_GRAPH_TRACER
  24         select HAVE_FUNCTION_TRACER
  25         select HAVE_FUNCTION_TRACE_MCOUNT_TEST
  26         select HAVE_IDE
  27         select HAVE_IRQ_WORK
  28         select HAVE_KERNEL_GZIP if RAMKERNEL
  29         select HAVE_KERNEL_BZIP2 if RAMKERNEL
  30         select HAVE_KERNEL_LZMA if RAMKERNEL
  31         select HAVE_KERNEL_LZO if RAMKERNEL
  32         select HAVE_OPROFILE
  33         select HAVE_PERF_EVENTS
  34         select ARCH_HAVE_CUSTOM_GPIO_H
  35         select ARCH_WANT_OPTIONAL_GPIOLIB
  36         select HAVE_GENERIC_HARDIRQS
  37         select GENERIC_ATOMIC64
  38         select GENERIC_IRQ_PROBE
  39         select IRQ_PER_CPU if SMP
  40         select HAVE_NMI_WATCHDOG if NMI_WATCHDOG
  41         select GENERIC_SMP_IDLE_THREAD
  42         select ARCH_USES_GETTIMEOFFSET if !GENERIC_CLOCKEVENTS
  43
  44 config GENERIC_CSUM
  45         def_bool y
  46
  47 config GENERIC_BUG
  48         def_bool y
  49         depends on BUG
  50
  51 config ZONE_DMA
  52         def_bool y
  53
  54 config GENERIC_GPIO
  55         def_bool y
  56
  57 config FORCE_MAX_ZONEORDER
  58         int
  59         default "14"
  60
  61 config GENERIC_CALIBRATE_DELAY
  62         def_bool y
  63
  64 config LOCKDEP_SUPPORT
  65         def_bool y
  66
  67 config STACKTRACE_SUPPORT
  68         def_bool y
  69
  70 config TRACE_IRQFLAGS_SUPPORT
  71         def_bool y
  72
  73 source "init/Kconfig"
  74
  75 source "kernel/Kconfig.preempt"
  76
  77 source "kernel/Kconfig.freezer"
  78
  79 menu "Blackfin Processor Options"
  80
  81 comment "Processor and Board Settings"
  82
  83 choice
  84         prompt "CPU"
  85         default BF533
  86
  87 config BF512
  88         bool "BF512"
  89         help
  90           BF512 Processor Support.
  91
  92 config BF514
  93         bool "BF514"
  94         help
  95           BF514 Processor Support.
  96
  97 config BF516
  98         bool "BF516"
  99         help
 100           BF516 Processor Support.
 101
 102 config BF518
 103         bool "BF518"
 104         help
 105           BF518 Processor Support.
 106
 107 config BF522
 108         bool "BF522"
 109         help
 110           BF522 Processor Support.
 111
 112 config BF523
 113         bool "BF523"
 114         help
 115           BF523 Processor Support.
 116
 117 config BF524
 118         bool "BF524"
 119         help
 120           BF524 Processor Support.
 121
 122 config BF525
 123         bool "BF525"
 124         help
 125           BF525 Processor Support.
 126
 127 config BF526
 128         bool "BF526"
 129         help
 130           BF526 Processor Support.
 131
 132 config BF527
 133         bool "BF527"
 134         help
 135           BF527 Processor Support.
 136
 137 config BF531
 138         bool "BF531"
 139         help
 140           BF531 Processor Support.
 141
 142 config BF532
 143         bool "BF532"
 144         help
 145           BF532 Processor Support.
 146
 147 config BF533
 148         bool "BF533"
 149         help
 150           BF533 Processor Support.
 151
 152 config BF534
 153         bool "BF534"
 154         help
 155           BF534 Processor Support.
 156
 157 config BF536
 158         bool "BF536"
 159         help
 160           BF536 Processor Support.
 161
 162 config BF537
 163         bool "BF537"
 164         help
 165           BF537 Processor Support.
 166
 167 config BF538
 168         bool "BF538"
 169         help
 170           BF538 Processor Support.
 171
 172 config BF539
 173         bool "BF539"
 174         help
 175           BF539 Processor Support.
 176
 177 config BF542_std
 178         bool "BF542"
 179         help
 180           BF542 Processor Support.
 181
 182 config BF542M
 183         bool "BF542m"
 184         help
 185           BF542 Processor Support.
 186
 187 config BF544_std
 188         bool "BF544"
 189         help
 190           BF544 Processor Support.
 191
 192 config BF544M
 193         bool "BF544m"
 194         help
 195           BF544 Processor Support.
 196
 197 config BF547_std
 198         bool "BF547"
 199         help
 200           BF547 Processor Support.
 201
 202 config BF547M
 203         bool "BF547m"
 204         help
 205           BF547 Processor Support.
 206
 207 config BF548_std
 208         bool "BF548"
 209         help
 210           BF548 Processor Support.
 211
 212 config BF548M
 213         bool "BF548m"
 214         help
 215           BF548 Processor Support.
 216
 217 config BF549_std
 218         bool "BF549"
 219         help
 220           BF549 Processor Support.
 221
 222 config BF549M
 223         bool "BF549m"
 224         help
 225           BF549 Processor Support.
 226
 227 config BF561
 228         bool "BF561"
 229         help
 230           BF561 Processor Support.
 231
 232 config BF609
 233         bool "BF609"
 234         select CLKDEV_LOOKUP
 235         help
 236           BF609 Processor Support.
 237
 238 endchoice
 239
 240 config SMP
 241         depends on BF561
 242         select TICKSOURCE_CORETMR
 243         bool "Symmetric multi-processing support"
 244         ---help---
 245           This enables support for systems with more than one CPU,
 246           like the dual core BF561. If you have a system with only one
 247           CPU, say N. If you have a system with more than one CPU, say Y.
 248
 249           If you don't know what to do here, say N.
 250
 251 config NR_CPUS
 252         int
 253         depends on SMP
 254         default 2 if BF561
 255
 256 config HOTPLUG_CPU
 257         bool "Support for hot-pluggable CPUs"
 258         depends on SMP && HOTPLUG
 259         default y
 260
 261 config BF_REV_MIN
 262         int
 263         default 0 if (BF51x || BF52x || (BF54x && !BF54xM)) || BF60x
 264         default 2 if (BF537 || BF536 || BF534)
 265         default 3 if (BF561 || BF533 || BF532 || BF531 || BF54xM)
 266         default 4 if (BF538 || BF539)
 267
 268 config BF_REV_MAX
 269         int
 270         default 2 if (BF51x || BF52x || (BF54x && !BF54xM)) || BF60x
 271         default 3 if (BF537 || BF536 || BF534 || BF54xM)
 272         default 5 if (BF561 || BF538 || BF539)
 273         default 6 if (BF533 || BF532 || BF531)
 274
 275 choice
 276         prompt "Silicon Rev"
 277         default BF_REV_0_0 if (BF51x || BF52x || BF60x)
 278         default BF_REV_0_2 if (BF534 || BF536 || BF537 || (BF54x && !BF54xM))
 279         default BF_REV_0_3 if (BF531 || BF532 || BF533 || BF54xM || BF561)
 280
 281 config BF_REV_0_0
 282         bool "0.0"
 283         depends on (BF51x || BF52x || (BF54x && !BF54xM) || BF60x)
 284
 285 config BF_REV_0_1
 286         bool "0.1"
 287         depends on (BF51x || BF52x || (BF54x && !BF54xM))
 288
 289 config BF_REV_0_2
 290         bool "0.2"
 291         depends on (BF51x || BF52x || BF537 || BF536 || BF534 || (BF54x && !BF54xM))
 292
 293 config BF_REV_0_3
 294         bool "0.3"
 295         depends on (BF54xM || BF561 || BF537 || BF536 || BF534 || BF533 || BF532 || BF531)
 296
 297 config BF_REV_0_4
 298         bool "0.4"
 299         depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539)
 300
 301 config BF_REV_0_5
 302         bool "0.5"
 303         depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539)
 304
 305 config BF_REV_0_6
 306         bool "0.6"
 307         depends on (BF533 || BF532 || BF531)
 308
 309 config BF_REV_ANY
 310         bool "any"
 311
 312 config BF_REV_NONE
 313         bool "none"
 314
 315 endchoice
 316
 317 config BF53x
 318         bool
 319         depends on (BF531 || BF532 || BF533 || BF534 || BF536 || BF537)
 320         default y
 321
 322 config MEM_MT48LC64M4A2FB_7E
 323         bool
 324         depends on (BFIN533_STAMP)
 325         default y
 326
 327 config MEM_MT48LC16M16A2TG_75
 328         bool
 329         depends on (BFIN533_EZKIT || BFIN561_EZKIT \
 330                 || BFIN533_BLUETECHNIX_CM || BFIN537_BLUETECHNIX_CM_E \
 331                 || BFIN537_BLUETECHNIX_CM_U || H8606_HVSISTEMAS \
 332                 || BFIN527_BLUETECHNIX_CM)
 333         default y
 334
 335 config MEM_MT48LC32M8A2_75
 336         bool
 337         depends on (BFIN518F_EZBRD || BFIN537_STAMP || PNAV10 || BFIN538_EZKIT)
 338         default y
 339
 340 config MEM_MT48LC8M32B2B5_7
 341         bool
 342         depends on (BFIN561_BLUETECHNIX_CM)
 343         default y
 344
 345 config MEM_MT48LC32M16A2TG_75
 346         bool
 347         depends on (BFIN527_EZKIT || BFIN527_EZKIT_V2 || BFIN532_IP0X || BLACKSTAMP || BFIN527_AD7160EVAL)
 348         default y
 349
 350 config MEM_MT48H32M16LFCJ_75
 351         bool
 352         depends on (BFIN526_EZBRD)
 353         default y
 354
 355 source "arch/blackfin/mach-bf518/Kconfig"
 356 source "arch/blackfin/mach-bf527/Kconfig"
 357 source "arch/blackfin/mach-bf533/Kconfig"
 358 source "arch/blackfin/mach-bf561/Kconfig"
 359 source "arch/blackfin/mach-bf537/Kconfig"
 360 source "arch/blackfin/mach-bf538/Kconfig"
 361 source "arch/blackfin/mach-bf548/Kconfig"
 362 source "arch/blackfin/mach-bf609/Kconfig"
 363
 364 menu "Board customizations"
 365
 366 config CMDLINE_BOOL
 367         bool "Default bootloader kernel arguments"
 368
 369 config CMDLINE
 370         string "Initial kernel command string"
 371         depends on CMDLINE_BOOL
 372         default "console=ttyBF0,57600"
 373         help
 374           If you don't have a boot loader capable of passing a command line string
 375           to the kernel, you may specify one here. As a minimum, you should specify
 376           the memory size and the root device (e.g., mem=8M, root=/dev/nfs).
 377
 378 config BOOT_LOAD
 379         hex "Kernel load address for booting"
 380         default "0x1000"
 381         range 0x1000 0x20000000
 382         help
 383           This option allows you to set the load address of the kernel.
 384           This can be useful if you are on a board which has a small amount
 385           of memory or you wish to reserve some memory at the beginning of
 386           the address space.
 387
 388           Note that you need to keep this value above 4k (0x1000) as this
 389           memory region is used to capture NULL pointer references as well
 390           as some core kernel functions.
 391
 392 config PHY_RAM_BASE_ADDRESS
 393         hex "Physical RAM Base"
 394         default 0x0
 395         help
 396           set BF609 FPGA physical SRAM base address
 397
 398 config ROM_BASE
 399         hex "Kernel ROM Base"
 400         depends on ROMKERNEL
 401         default "0x20040040"
 402         range 0x20000000 0x20400000 if !(BF54x || BF561)
 403         range 0x20000000 0x30000000 if (BF54x || BF561)
 404         help
 405           Make sure your ROM base does not include any file-header
 406           information that is prepended to the kernel.
 407
 408           For example, the bootable U-Boot format (created with
 409           mkimage) has a 64 byte header (0x40).  So while the image
 410           you write to flash might start at say 0x20080000, you have
 411           to add 0x40 to get the kernel's ROM base as it will come
 412           after the header.
 413
 414 comment "Clock/PLL Setup"
 415
 416 config CLKIN_HZ
 417         int "Frequency of the crystal on the board in Hz"
 418         default "10000000" if BFIN532_IP0X
 419         default "11059200" if BFIN533_STAMP
 420         default "24576000" if PNAV10
 421         default "25000000" # most people use this
 422         default "27000000" if BFIN533_EZKIT
 423         default "30000000" if BFIN561_EZKIT
 424         default "24000000" if BFIN527_AD7160EVAL
 425         help
 426           The frequency of CLKIN crystal oscillator on the board in Hz.
 427           Warning: This value should match the crystal on the board. Otherwise,
 428           peripherals won't work properly.
 429
 430 config BFIN_KERNEL_CLOCK
 431         bool "Re-program Clocks while Kernel boots?"
 432         default n
 433         help
 434           This option decides if kernel clocks are re-programed from the
 435           bootloader settings. If the clocks are not set, the SDRAM settings
 436           are also not changed, and the Bootloader does 100% of the hardware
 437           configuration.
 438
 439 config PLL_BYPASS
 440         bool "Bypass PLL"
 441         depends on BFIN_KERNEL_CLOCK && (!BF60x)
 442         default n
 443
 444 config CLKIN_HALF
 445         bool "Half Clock In"
 446         depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
 447         default n
 448         help
 449           If this is set the clock will be divided by 2, before it goes to the PLL.
 450
 451 config VCO_MULT
 452         int "VCO Multiplier"
 453         depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
 454         range 1 64
 455         default "22" if BFIN533_EZKIT
 456         default "45" if BFIN533_STAMP
 457         default "20" if (BFIN537_STAMP || BFIN527_EZKIT || BFIN527_EZKIT_V2 || BFIN548_EZKIT || BFIN548_BLUETECHNIX_CM || BFIN538_EZKIT)
 458         default "22" if BFIN533_BLUETECHNIX_CM
 459         default "20" if (BFIN537_BLUETECHNIX_CM_E || BFIN537_BLUETECHNIX_CM_U || BFIN527_BLUETECHNIX_CM || BFIN561_BLUETECHNIX_CM)
 460         default "20" if (BFIN561_EZKIT || BF609)
 461         default "16" if (H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD || BFIN518F_EZBRD)
 462         default "25" if BFIN527_AD7160EVAL
 463         help
 464           This controls the frequency of the on-chip PLL. This can be between 1 and 64.
 465           PLL Frequency = (Crystal Frequency) * (this setting)
 466
 467 choice
 468         prompt "Core Clock Divider"
 469         depends on BFIN_KERNEL_CLOCK
 470         default CCLK_DIV_1
 471         help
 472           This sets the frequency of the core. It can be 1, 2, 4 or 8
 473           Core Frequency = (PLL frequency) / (this setting)
 474
 475 config CCLK_DIV_1
 476         bool "1"
 477
 478 config CCLK_DIV_2
 479         bool "2"
 480
 481 config CCLK_DIV_4
 482         bool "4"
 483
 484 config CCLK_DIV_8
 485         bool "8"
 486 endchoice
 487
 488 config SCLK_DIV
 489         int "System Clock Divider"
 490         depends on BFIN_KERNEL_CLOCK
 491         range 1 15
 492         default 4
 493         help
 494           This sets the frequency of the system clock (including SDRAM or DDR) on
 495           !BF60x else it set the clock for system buses and provides the
 496           source from which SCLK0 and SCLK1 are derived.
 497           This can be between 1 and 15
 498           System Clock = (PLL frequency) / (this setting)
 499
 500 config SCLK0_DIV
 501         int "System Clock0 Divider"
 502         depends on BFIN_KERNEL_CLOCK && BF60x
 503         range 1 15
 504         default 1
 505         help
 506           This sets the frequency of the system clock0 for PVP and all other
 507           peripherals not clocked by SCLK1.
 508           This can be between 1 and 15
 509           System Clock0 = (System Clock) / (this setting)
 510
 511 config SCLK1_DIV
 512         int "System Clock1 Divider"
 513         depends on BFIN_KERNEL_CLOCK && BF60x
 514         range 1 15
 515         default 1
 516         help
 517           This sets the frequency of the system clock1 (including SPORT, SPI and ACM).
 518           This can be between 1 and 15
 519           System Clock1 = (System Clock) / (this setting)
 520
 521 config DCLK_DIV
 522         int "DDR Clock Divider"
 523         depends on BFIN_KERNEL_CLOCK && BF60x
 524         range 1 15
 525         default 2
 526         help
 527           This sets the frequency of the DDR memory.
 528           This can be between 1 and 15
 529           DDR Clock = (PLL frequency) / (this setting)
 530
 531 choice
 532         prompt "DDR SDRAM Chip Type"
 533         depends on BFIN_KERNEL_CLOCK
 534         depends on BF54x
 535         default MEM_MT46V32M16_5B
 536
 537 config MEM_MT46V32M16_6T
 538         bool "MT46V32M16_6T"
 539
 540 config MEM_MT46V32M16_5B
 541         bool "MT46V32M16_5B"
 542 endchoice
 543
 544 choice
 545         prompt "DDR/SDRAM Timing"
 546         depends on BFIN_KERNEL_CLOCK && !BF60x
 547         default BFIN_KERNEL_CLOCK_MEMINIT_CALC
 548         help
 549           This option allows you to specify Blackfin SDRAM/DDR Timing parameters
 550           The calculated SDRAM timing parameters may not be 100%
 551           accurate - This option is therefore marked experimental.
 552
 553 config BFIN_KERNEL_CLOCK_MEMINIT_CALC
 554         bool "Calculate Timings (EXPERIMENTAL)"
 555         depends on EXPERIMENTAL
 556
 557 config BFIN_KERNEL_CLOCK_MEMINIT_SPEC
 558         bool "Provide accurate Timings based on target SCLK"
 559         help
 560           Please consult the Blackfin Hardware Reference Manuals as well
 561           as the memory device datasheet.
 562           http://docs.blackfin.uclinux.org/doku.php?id=bfin:sdram
 563 endchoice
 564
 565 menu "Memory Init Control"
 566         depends on BFIN_KERNEL_CLOCK_MEMINIT_SPEC
 567
 568 config MEM_DDRCTL0
 569         depends on BF54x
 570         hex "DDRCTL0"
 571         default 0x0
 572
 573 config MEM_DDRCTL1
 574         depends on BF54x
 575         hex "DDRCTL1"
 576         default 0x0
 577
 578 config MEM_DDRCTL2
 579         depends on BF54x
 580         hex "DDRCTL2"
 581         default 0x0
 582
 583 config MEM_EBIU_DDRQUE
 584         depends on BF54x
 585         hex "DDRQUE"
 586         default 0x0
 587
 588 config MEM_SDRRC
 589         depends on !BF54x
 590         hex "SDRRC"
 591         default 0x0
 592
 593 config MEM_SDGCTL
 594         depends on !BF54x
 595         hex "SDGCTL"
 596         default 0x0
 597 endmenu
 598
 599 #
 600 # Max & Min Speeds for various Chips
 601 #
 602 config MAX_VCO_HZ
 603         int
 604         default 400000000 if BF512
 605         default 400000000 if BF514
 606         default 400000000 if BF516
 607         default 400000000 if BF518
 608         default 400000000 if BF522
 609         default 600000000 if BF523
 610         default 400000000 if BF524
 611         default 600000000 if BF525
 612         default 400000000 if BF526
 613         default 600000000 if BF527
 614         default 400000000 if BF531
 615         default 400000000 if BF532
 616         default 750000000 if BF533
 617         default 500000000 if BF534
 618         default 400000000 if BF536
 619         default 600000000 if BF537
 620         default 533333333 if BF538
 621         default 533333333 if BF539
 622         default 600000000 if BF542
 623         default 533333333 if BF544
 624         default 600000000 if BF547
 625         default 600000000 if BF548
 626         default 533333333 if BF549
 627         default 600000000 if BF561
 628         default 800000000 if BF609
 629
 630 config MIN_VCO_HZ
 631         int
 632         default 50000000
 633
 634 config MAX_SCLK_HZ
 635         int
 636         default 200000000 if BF609
 637         default 133333333
 638
 639 config MIN_SCLK_HZ
 640         int
 641         default 27000000
 642
 643 comment "Kernel Timer/Scheduler"
 644
 645 source kernel/Kconfig.hz
 646
 647 config SET_GENERIC_CLOCKEVENTS
 648         bool "Generic clock events"
 649         default y
 650         select GENERIC_CLOCKEVENTS
 651
 652 menu "Clock event device"
 653         depends on GENERIC_CLOCKEVENTS
 654 config TICKSOURCE_GPTMR0
 655         bool "GPTimer0"
 656         depends on !SMP
 657         select BFIN_GPTIMERS
 658
 659 config TICKSOURCE_CORETMR
 660         bool "Core timer"
 661         default y
 662 endmenu
 663
 664 menu "Clock souce"
 665         depends on GENERIC_CLOCKEVENTS
 666 config CYCLES_CLOCKSOURCE
 667         bool "CYCLES"
 668         default y
 669         depends on !BFIN_SCRATCH_REG_CYCLES
 670         depends on !SMP
 671         help
 672           If you say Y here, you will enable support for using the 'cycles'
 673           registers as a clock source.  Doing so means you will be unable to
 674           safely write to the 'cycles' register during runtime.  You will
 675           still be able to read it (such as for performance monitoring), but
 676           writing the registers will most likely crash the kernel.
 677
 678 config GPTMR0_CLOCKSOURCE
 679         bool "GPTimer0"
 680         select BFIN_GPTIMERS
 681         depends on !TICKSOURCE_GPTMR0
 682 endmenu
 683
 684 comment "Misc"
 685
 686 choice
 687         prompt "Blackfin Exception Scratch Register"
 688         default BFIN_SCRATCH_REG_RETN
 689         help
 690           Select the resource to reserve for the Exception handler:
 691             - RETN: Non-Maskable Interrupt (NMI)
 692             - RETE: Exception Return (JTAG/ICE)
 693             - CYCLES: Performance counter
 694
 695           If you are unsure, please select "RETN".
 696
 697 config BFIN_SCRATCH_REG_RETN
 698         bool "RETN"
 699         help
 700           Use the RETN register in the Blackfin exception handler
 701           as a stack scratch register.  This means you cannot
 702           safely use NMI on the Blackfin while running Linux, but
 703           you can debug the system with a JTAG ICE and use the
 704           CYCLES performance registers.
 705
 706           If you are unsure, please select "RETN".
 707
 708 config BFIN_SCRATCH_REG_RETE
 709         bool "RETE"
 710         help
 711           Use the RETE register in the Blackfin exception handler
 712           as a stack scratch register.  This means you cannot
 713           safely use a JTAG ICE while debugging a Blackfin board,
 714           but you can safely use the CYCLES performance registers
 715           and the NMI.
 716
 717           If you are unsure, please select "RETN".
 718
 719 config BFIN_SCRATCH_REG_CYCLES
 720         bool "CYCLES"
 721         help
 722           Use the CYCLES register in the Blackfin exception handler
 723           as a stack scratch register.  This means you cannot
 724           safely use the CYCLES performance registers on a Blackfin
 725           board at anytime, but you can debug the system with a JTAG
 726           ICE and use the NMI.
 727
 728           If you are unsure, please select "RETN".
 729
 730 endchoice
 731
 732 endmenu
 733
 734
 735 menu "Blackfin Kernel Optimizations"
 736
 737 comment "Memory Optimizations"
 738
 739 config I_ENTRY_L1
 740         bool "Locate interrupt entry code in L1 Memory"
 741         default y
 742         depends on !SMP
 743         help
 744           If enabled, interrupt entry code (STORE/RESTORE CONTEXT) is linked
 745           into L1 instruction memory. (less latency)
 746
 747 config EXCPT_IRQ_SYSC_L1
 748         bool "Locate entire ASM lowlevel exception / interrupt - Syscall and CPLB handler code in L1 Memory"
 749         default y
 750         depends on !SMP
 751         help
 752           If enabled, the entire ASM lowlevel exception and interrupt entry code
 753           (STORE/RESTORE CONTEXT) is linked into L1 instruction memory.
 754           (less latency)
 755
 756 config DO_IRQ_L1
 757         bool "Locate frequently called do_irq dispatcher function in L1 Memory"
 758         default y
 759         depends on !SMP
 760         help
 761           If enabled, the frequently called do_irq dispatcher function is linked
 762           into L1 instruction memory. (less latency)
 763
 764 config CORE_TIMER_IRQ_L1
 765         bool "Locate frequently called timer_interrupt() function in L1 Memory"
 766         default y
 767         depends on !SMP
 768         help
 769           If enabled, the frequently called timer_interrupt() function is linked
 770           into L1 instruction memory. (less latency)
 771
 772 config IDLE_L1
 773         bool "Locate frequently idle function in L1 Memory"
 774         default y
 775         depends on !SMP
 776         help
 777           If enabled, the frequently called idle function is linked
 778           into L1 instruction memory. (less latency)
 779
 780 config SCHEDULE_L1
 781         bool "Locate kernel schedule function in L1 Memory"
 782         default y
 783         depends on !SMP
 784         help
 785           If enabled, the frequently called kernel schedule is linked
 786           into L1 instruction memory. (less latency)
 787
 788 config ARITHMETIC_OPS_L1
 789         bool "Locate kernel owned arithmetic functions in L1 Memory"
 790         default y
 791         depends on !SMP
 792         help
 793           If enabled, arithmetic functions are linked
 794           into L1 instruction memory. (less latency)
 795
 796 config ACCESS_OK_L1
 797         bool "Locate access_ok function in L1 Memory"
 798         default y
 799         depends on !SMP
 800         help
 801           If enabled, the access_ok function is linked
 802           into L1 instruction memory. (less latency)
 803
 804 config MEMSET_L1
 805         bool "Locate memset function in L1 Memory"
 806         default y
 807         depends on !SMP
 808         help
 809           If enabled, the memset function is linked
 810           into L1 instruction memory. (less latency)
 811
 812 config MEMCPY_L1
 813         bool "Locate memcpy function in L1 Memory"
 814         default y
 815         depends on !SMP
 816         help
 817           If enabled, the memcpy function is linked
 818           into L1 instruction memory. (less latency)
 819
 820 config STRCMP_L1
 821         bool "locate strcmp function in L1 Memory"
 822         default y
 823         depends on !SMP
 824         help
 825           If enabled, the strcmp function is linked
 826           into L1 instruction memory (less latency).
 827
 828 config STRNCMP_L1
 829         bool "locate strncmp function in L1 Memory"
 830         default y
 831         depends on !SMP
 832         help
 833           If enabled, the strncmp function is linked
 834           into L1 instruction memory (less latency).
 835
 836 config STRCPY_L1
 837         bool "locate strcpy function in L1 Memory"
 838         default y
 839         depends on !SMP
 840         help
 841           If enabled, the strcpy function is linked
 842           into L1 instruction memory (less latency).
 843
 844 config STRNCPY_L1
 845         bool "locate strncpy function in L1 Memory"
 846         default y
 847         depends on !SMP
 848         help
 849           If enabled, the strncpy function is linked
 850           into L1 instruction memory (less latency).
 851
 852 config SYS_BFIN_SPINLOCK_L1
 853         bool "Locate sys_bfin_spinlock function in L1 Memory"
 854         default y
 855         depends on !SMP
 856         help
 857           If enabled, sys_bfin_spinlock function is linked
 858           into L1 instruction memory. (less latency)
 859
 860 config IP_CHECKSUM_L1
 861         bool "Locate IP Checksum function in L1 Memory"
 862         default n
 863         depends on !SMP
 864         help
 865           If enabled, the IP Checksum function is linked
 866           into L1 instruction memory. (less latency)
 867
 868 config CACHELINE_ALIGNED_L1
 869         bool "Locate cacheline_aligned data to L1 Data Memory"
 870         default y if !BF54x
 871         default n if BF54x
 872         depends on !SMP && !BF531 && !CRC32
 873         help
 874           If enabled, cacheline_aligned data is linked
 875           into L1 data memory. (less latency)
 876
 877 config SYSCALL_TAB_L1
 878         bool "Locate Syscall Table L1 Data Memory"
 879         default n
 880         depends on !SMP && !BF531
 881         help
 882           If enabled, the Syscall LUT is linked
 883           into L1 data memory. (less latency)
 884
 885 config CPLB_SWITCH_TAB_L1
 886         bool "Locate CPLB Switch Tables L1 Data Memory"
 887         default n
 888         depends on !SMP && !BF531
 889         help
 890           If enabled, the CPLB Switch Tables are linked
 891           into L1 data memory. (less latency)
 892
 893 config ICACHE_FLUSH_L1
 894         bool "Locate icache flush funcs in L1 Inst Memory"
 895         default y
 896         help
 897           If enabled, the Blackfin icache flushing functions are linked
 898           into L1 instruction memory.
 899
 900           Note that this might be required to address anomalies, but
 901           these functions are pretty small, so it shouldn't be too bad.
 902           If you are using a processor affected by an anomaly, the build
 903           system will double check for you and prevent it.
 904
 905 config DCACHE_FLUSH_L1
 906         bool "Locate dcache flush funcs in L1 Inst Memory"
 907         default y
 908         depends on !SMP
 909         help
 910           If enabled, the Blackfin dcache flushing functions are linked
 911           into L1 instruction memory.
 912
 913 config APP_STACK_L1
 914         bool "Support locating application stack in L1 Scratch Memory"
 915         default y
 916         depends on !SMP
 917         help
 918           If enabled the application stack can be located in L1
 919           scratch memory (less latency).
 920
 921           Currently only works with FLAT binaries.
 922
 923 config EXCEPTION_L1_SCRATCH
 924         bool "Locate exception stack in L1 Scratch Memory"
 925         default n
 926         depends on !SMP && !APP_STACK_L1
 927         help
 928           Whenever an exception occurs, use the L1 Scratch memory for
 929           stack storage.  You cannot place the stacks of FLAT binaries
 930           in L1 when using this option.
 931
 932           If you don't use L1 Scratch, then you should say Y here.
 933
 934 comment "Speed Optimizations"
 935 config BFIN_INS_LOWOVERHEAD
 936         bool "ins[bwl] low overhead, higher interrupt latency"
 937         default y
 938         depends on !SMP
 939         help
 940           Reads on the Blackfin are speculative. In Blackfin terms, this means
 941           they can be interrupted at any time (even after they have been issued
 942           on to the external bus), and re-issued after the interrupt occurs.
 943           For memory - this is not a big deal, since memory does not change if
 944           it sees a read.
 945
 946           If a FIFO is sitting on the end of the read, it will see two reads,
 947           when the core only sees one since the FIFO receives both the read
 948           which is cancelled (and not delivered to the core) and the one which
 949           is re-issued (which is delivered to the core).
 950
 951           To solve this, interrupts are turned off before reads occur to
 952           I/O space. This option controls which the overhead/latency of
 953           controlling interrupts during this time
 954            "n" turns interrupts off every read
 955                 (higher overhead, but lower interrupt latency)
 956            "y" turns interrupts off every loop
 957                 (low overhead, but longer interrupt latency)
 958
 959           default behavior is to leave this set to on (type "Y"). If you are experiencing
 960           interrupt latency issues, it is safe and OK to turn this off.
 961
 962 endmenu
 963
 964 choice
 965         prompt "Kernel executes from"
 966         help
 967           Choose the memory type that the kernel will be running in.
 968
 969 config RAMKERNEL
 970         bool "RAM"
 971         help
 972           The kernel will be resident in RAM when running.
 973
 974 config ROMKERNEL
 975         bool "ROM"
 976         help
 977           The kernel will be resident in FLASH/ROM when running.
 978
 979 endchoice
 980
 981 # Common code uses "ROMKERNEL" or "XIP_KERNEL", so define both
 982 config XIP_KERNEL
 983         bool
 984         default y
 985         depends on ROMKERNEL
 986
 987 source "mm/Kconfig"
 988
 989 config BFIN_GPTIMERS
 990         tristate "Enable Blackfin General Purpose Timers API"
 991         default n
 992         help
 993           Enable support for the General Purpose Timers API.  If you
 994           are unsure, say N.
 995
 996           To compile this driver as a module, choose M here: the module
 997           will be called gptimers.
 998
 999 config HAVE_PWM
1000         tristate "Enable PWM API support"
1001         depends on BFIN_GPTIMERS
1002         help
1003           Enable support for the Pulse Width Modulation framework (as
1004           found in linux/pwm.h).
1005
1006           To compile this driver as a module, choose M here: the module
1007           will be called pwm.
1008
1009 choice
1010         prompt "Uncached DMA region"
1011         default DMA_UNCACHED_1M
1012 config DMA_UNCACHED_4M
1013         bool "Enable 4M DMA region"
1014 config DMA_UNCACHED_2M
1015         bool "Enable 2M DMA region"
1016 config DMA_UNCACHED_1M
1017         bool "Enable 1M DMA region"
1018 config DMA_UNCACHED_512K
1019         bool "Enable 512K DMA region"
1020 config DMA_UNCACHED_256K
1021         bool "Enable 256K DMA region"
1022 config DMA_UNCACHED_128K
1023         bool "Enable 128K DMA region"
1024 config DMA_UNCACHED_NONE
1025         bool "Disable DMA region"
1026 endchoice
1027
1028
1029 comment "Cache Support"
1030
1031 config BFIN_ICACHE
1032         bool "Enable ICACHE"
1033         default y
1034 config BFIN_EXTMEM_ICACHEABLE
1035         bool "Enable ICACHE for external memory"
1036         depends on BFIN_ICACHE
1037         default y
1038 config BFIN_L2_ICACHEABLE
1039         bool "Enable ICACHE for L2 SRAM"
1040         depends on BFIN_ICACHE
1041         depends on BF54x || BF561
1042         default n
1043
1044 config BFIN_DCACHE
1045         bool "Enable DCACHE"
1046         default y
1047 config BFIN_DCACHE_BANKA
1048         bool "Enable only 16k BankA DCACHE - BankB is SRAM"
1049         depends on BFIN_DCACHE && !BF531
1050         default n
1051 config BFIN_EXTMEM_DCACHEABLE
1052         bool "Enable DCACHE for external memory"
1053         depends on BFIN_DCACHE
1054         default y
1055 choice
1056         prompt "External memory DCACHE policy"
1057         depends on BFIN_EXTMEM_DCACHEABLE
1058         default BFIN_EXTMEM_WRITEBACK if !SMP
1059         default BFIN_EXTMEM_WRITETHROUGH if SMP
1060 config BFIN_EXTMEM_WRITEBACK
1061         bool "Write back"
1062         depends on !SMP
1063         help
1064           Write Back Policy:
1065             Cached data will be written back to SDRAM only when needed.
1066             This can give a nice increase in performance, but beware of
1067             broken drivers that do not properly invalidate/flush their
1068             cache.
1069
1070           Write Through Policy:
1071             Cached data will always be written back to SDRAM when the
1072             cache is updated.  This is a completely safe setting, but
1073             performance is worse than Write Back.
1074
1075           If you are unsure of the options and you want to be safe,
1076           then go with Write Through.
1077
1078 config BFIN_EXTMEM_WRITETHROUGH
1079         bool "Write through"
1080         help
1081           Write Back Policy:
1082             Cached data will be written back to SDRAM only when needed.
1083             This can give a nice increase in performance, but beware of
1084             broken drivers that do not properly invalidate/flush their
1085             cache.
1086
1087           Write Through Policy:
1088             Cached data will always be written back to SDRAM when the
1089             cache is updated.  This is a completely safe setting, but
1090             performance is worse than Write Back.
1091
1092           If you are unsure of the options and you want to be safe,
1093           then go with Write Through.
1094
1095 endchoice
1096
1097 config BFIN_L2_DCACHEABLE
1098         bool "Enable DCACHE for L2 SRAM"
1099         depends on BFIN_DCACHE
1100         depends on (BF54x || BF561 || BF60x) && !SMP
1101         default n
1102 choice
1103         prompt "L2 SRAM DCACHE policy"
1104         depends on BFIN_L2_DCACHEABLE
1105         default BFIN_L2_WRITEBACK
1106 config BFIN_L2_WRITEBACK
1107         bool "Write back"
1108
1109 config BFIN_L2_WRITETHROUGH
1110         bool "Write through"
1111 endchoice
1112
1113
1114 comment "Memory Protection Unit"
1115 config MPU
1116         bool "Enable the memory protection unit (EXPERIMENTAL)"
1117         default n
1118         help
1119           Use the processor's MPU to protect applications from accessing
1120           memory they do not own.  This comes at a performance penalty
1121           and is recommended only for debugging.
1122
1123 comment "Asynchronous Memory Configuration"
1124
1125 menu "EBIU_AMGCTL Global Control"
1126         depends on !BF60x
1127 config C_AMCKEN
1128         bool "Enable CLKOUT"
1129         default y
1130
1131 config C_CDPRIO
1132         bool "DMA has priority over core for ext. accesses"
1133         default n
1134
1135 config C_B0PEN
1136         depends on BF561
1137         bool "Bank 0 16 bit packing enable"
1138         default y
1139
1140 config C_B1PEN
1141         depends on BF561
1142         bool "Bank 1 16 bit packing enable"
1143         default y
1144
1145 config C_B2PEN
1146         depends on BF561
1147         bool "Bank 2 16 bit packing enable"
1148         default y
1149
1150 config C_B3PEN
1151         depends on BF561
1152         bool "Bank 3 16 bit packing enable"
1153         default n
1154
1155 choice
1156         prompt "Enable Asynchronous Memory Banks"
1157         default C_AMBEN_ALL
1158
1159 config C_AMBEN
1160         bool "Disable All Banks"
1161
1162 config C_AMBEN_B0
1163         bool "Enable Bank 0"
1164
1165 config C_AMBEN_B0_B1
1166         bool "Enable Bank 0 & 1"
1167
1168 config C_AMBEN_B0_B1_B2
1169         bool "Enable Bank 0 & 1 & 2"
1170
1171 config C_AMBEN_ALL
1172         bool "Enable All Banks"
1173 endchoice
1174 endmenu
1175
1176 menu "EBIU_AMBCTL Control"
1177         depends on !BF60x
1178 config BANK_0
1179         hex "Bank 0 (AMBCTL0.L)"
1180         default 0x7BB0
1181         help
1182           These are the low 16 bits of the EBIU_AMBCTL0 MMR which are
1183           used to control the Asynchronous Memory Bank 0 settings.
1184
1185 config BANK_1
1186         hex "Bank 1 (AMBCTL0.H)"
1187         default 0x7BB0
1188         default 0x5558 if BF54x
1189         help
1190           These are the high 16 bits of the EBIU_AMBCTL0 MMR which are
1191           used to control the Asynchronous Memory Bank 1 settings.
1192
1193 config BANK_2
1194         hex "Bank 2 (AMBCTL1.L)"
1195         default 0x7BB0
1196         help
1197           These are the low 16 bits of the EBIU_AMBCTL1 MMR which are
1198           used to control the Asynchronous Memory Bank 2 settings.
1199
1200 config BANK_3
1201         hex "Bank 3 (AMBCTL1.H)"
1202         default 0x99B3
1203         help
1204           These are the high 16 bits of the EBIU_AMBCTL1 MMR which are
1205           used to control the Asynchronous Memory Bank 3 settings.
1206
1207 endmenu
1208
1209 config EBIU_MBSCTLVAL
1210         hex "EBIU Bank Select Control Register"
1211         depends on BF54x
1212         default 0
1213
1214 config EBIU_MODEVAL
1215         hex "Flash Memory Mode Control Register"
1216         depends on BF54x
1217         default 1
1218
1219 config EBIU_FCTLVAL
1220         hex "Flash Memory Bank Control Register"
1221         depends on BF54x
1222         default 6
1223 endmenu
1224
1225 #############################################################################
1226 menu "Bus options (PCI, PCMCIA, EISA, MCA, ISA)"
1227
1228 config PCI
1229         bool "PCI support"
1230         depends on BROKEN
1231         help
1232           Support for PCI bus.
1233
1234 source "drivers/pci/Kconfig"
1235
1236 source "drivers/pcmcia/Kconfig"
1237
1238 source "drivers/pci/hotplug/Kconfig"
1239
1240 endmenu
1241
1242 menu "Executable file formats"
1243
1244 source "fs/Kconfig.binfmt"
1245
1246 endmenu
1247
1248 menu "Power management options"
1249
1250 source "kernel/power/Kconfig"
1251
1252 config ARCH_SUSPEND_POSSIBLE
1253         def_bool y
1254
1255 choice
1256         prompt "Standby Power Saving Mode"
1257         depends on PM && !BF60x
1258         default PM_BFIN_SLEEP_DEEPER
1259 config  PM_BFIN_SLEEP_DEEPER
1260         bool "Sleep Deeper"
1261         help
1262           Sleep "Deeper" Mode (High Power Savings) - This mode reduces dynamic
1263           power dissipation by disabling the clock to the processor core (CCLK).
1264           Furthermore, Standby sets the internal power supply voltage (VDDINT)
1265           to 0.85 V to provide the greatest power savings, while preserving the
1266           processor state.
1267           The PLL and system clock (SCLK) continue to operate at a very low
1268           frequency of about 3.3 MHz. To preserve data integrity in the SDRAM,
1269           the SDRAM is put into Self Refresh Mode. Typically an external event
1270           such as GPIO interrupt or RTC activity wakes up the processor.
1271           Various Peripherals such as UART, SPORT, PPI may not function as
1272           normal during Sleep Deeper, due to the reduced SCLK frequency.
1273           When in the sleep mode, system DMA access to L1 memory is not supported.
1274
1275           If unsure, select "Sleep Deeper".
1276
1277 config  PM_BFIN_SLEEP
1278         bool "Sleep"
1279         help
1280           Sleep Mode (High Power Savings) - The sleep mode reduces power
1281           dissipation by disabling the clock to the processor core (CCLK).
1282           The PLL and system clock (SCLK), however, continue to operate in
1283           this mode. Typically an external event or RTC activity will wake
1284           up the processor. When in the sleep mode, system DMA access to L1
1285           memory is not supported.
1286
1287           If unsure, select "Sleep Deeper".
1288 endchoice
1289
1290 comment "Possible Suspend Mem / Hibernate Wake-Up Sources"
1291         depends on PM
1292
1293 config PM_BFIN_WAKE_PH6
1294         bool "Allow Wake-Up from on-chip PHY or PH6 GP"
1295         depends on PM && (BF51x || BF52x || BF534 || BF536 || BF537)
1296         default n
1297         help
1298           Enable PHY and PH6 GP Wake-Up (Voltage Regulator Power-Up)
1299
1300 config PM_BFIN_WAKE_GP
1301         bool "Allow Wake-Up from GPIOs"
1302         depends on PM && BF54x
1303         default n
1304         help
1305           Enable General-Purpose Wake-Up (Voltage Regulator Power-Up)
1306           (all processors, except ADSP-BF549). This option sets
1307           the general-purpose wake-up enable (GPWE) control bit to enable
1308           wake-up upon detection of an active low signal on the /GPW (PH7) pin.
1309           On ADSP-BF549 this option enables the same functionality on the
1310           /MRXON pin also PH7.
1311
1312 config PM_BFIN_WAKE_PA15
1313         bool "Allow Wake-Up from PA15"
1314         depends on PM && BF60x
1315         default n
1316         help
1317           Enable PA15 Wake-Up
1318
1319 config PM_BFIN_WAKE_PA15_POL
1320         int "Wake-up priority"
1321         depends on PM_BFIN_WAKE_PA15
1322         default 0
1323         help
1324           Wake-Up priority 0(low) 1(high)
1325
1326 config PM_BFIN_WAKE_PB15
1327         bool "Allow Wake-Up from PB15"
1328         depends on PM && BF60x
1329         default n
1330         help
1331           Enable PB15 Wake-Up
1332
1333 config PM_BFIN_WAKE_PB15_POL
1334         int "Wake-up priority"
1335         depends on PM_BFIN_WAKE_PB15
1336         default 0
1337         help
1338           Wake-Up priority 0(low) 1(high)
1339
1340 config PM_BFIN_WAKE_PC15
1341         bool "Allow Wake-Up from PC15"
1342         depends on PM && BF60x
1343         default n
1344         help
1345           Enable PC15 Wake-Up
1346
1347 config PM_BFIN_WAKE_PC15_POL
1348         int "Wake-up priority"
1349         depends on PM_BFIN_WAKE_PC15
1350         default 0
1351         help
1352           Wake-Up priority 0(low) 1(high)
1353
1354 config PM_BFIN_WAKE_PD06
1355         bool "Allow Wake-Up from PD06(ETH0_PHYINT)"
1356         depends on PM && BF60x
1357         default n
1358         help
1359           Enable PD06(ETH0_PHYINT) Wake-up
1360
1361 config PM_BFIN_WAKE_PD06_POL
1362         int "Wake-up priority"
1363         depends on PM_BFIN_WAKE_PD06
1364         default 0
1365         help
1366           Wake-Up priority 0(low) 1(high)
1367
1368 config PM_BFIN_WAKE_PE12
1369         bool "Allow Wake-Up from PE12(ETH1_PHYINT, PUSH BUTTON)"
1370         depends on PM && BF60x
1371         default n
1372         help
1373           Enable PE12(ETH1_PHYINT, PUSH BUTTON) Wake-up
1374
1375 config PM_BFIN_WAKE_PE12_POL
1376         int "Wake-up priority"
1377         depends on PM_BFIN_WAKE_PE12
1378         default 0
1379         help
1380           Wake-Up priority 0(low) 1(high)
1381
1382 config PM_BFIN_WAKE_PG04
1383         bool "Allow Wake-Up from PG04(CAN0_RX)"
1384         depends on PM && BF60x
1385         default n
1386         help
1387           Enable PG04(CAN0_RX) Wake-up
1388
1389 config PM_BFIN_WAKE_PG04_POL
1390         int "Wake-up priority"
1391         depends on PM_BFIN_WAKE_PG04
1392         default 0
1393         help
1394           Wake-Up priority 0(low) 1(high)
1395
1396 config PM_BFIN_WAKE_PG13
1397         bool "Allow Wake-Up from PG13"
1398         depends on PM && BF60x
1399         default n
1400         help
1401           Enable PG13 Wake-Up
1402
1403 config PM_BFIN_WAKE_PG13_POL
1404         int "Wake-up priority"
1405         depends on PM_BFIN_WAKE_PG13
1406         default 0
1407         help
1408           Wake-Up priority 0(low) 1(high)
1409
1410 config PM_BFIN_WAKE_USB
1411         bool "Allow Wake-Up from (USB)"
1412         depends on PM && BF60x
1413         default n
1414         help
1415           Enable (USB) Wake-up
1416
1417 config PM_BFIN_WAKE_USB_POL
1418         int "Wake-up priority"
1419         depends on PM_BFIN_WAKE_USB
1420         default 0
1421         help
1422           Wake-Up priority 0(low) 1(high)
1423
1424 endmenu
1425
1426 menu "CPU Frequency scaling"
1427
1428 source "drivers/cpufreq/Kconfig"
1429
1430 config BFIN_CPU_FREQ
1431         bool
1432         depends on CPU_FREQ
1433         select CPU_FREQ_TABLE
1434         default y
1435
1436 config CPU_VOLTAGE
1437         bool "CPU Voltage scaling"
1438         depends on EXPERIMENTAL
1439         depends on CPU_FREQ
1440         default n
1441         help
1442           Say Y here if you want CPU voltage scaling according to the CPU frequency.
1443           This option violates the PLL BYPASS recommendation in the Blackfin Processor
1444           manuals. There is a theoretical risk that during VDDINT transitions
1445           the PLL may unlock.
1446
1447 endmenu
1448
1449 source "net/Kconfig"
1450
1451 source "drivers/Kconfig"
1452
1453 source "drivers/firmware/Kconfig"
1454
1455 source "fs/Kconfig"
1456
1457 source "arch/blackfin/Kconfig.debug"
1458
1459 source "security/Kconfig"
1460
1461 source "crypto/Kconfig"
1462
1463 source "lib/Kconfig"