arch/blackfin/include/asm/cplb.h

   1 /*
   2  * File:         include/asm-blackfin/cplb.h
   3  * Based on:     include/asm-blackfin/mach-bf537/bf537.h
   4  * Author:       Robin Getz <rgetz@blackfin.uclinux.org>
   5  *
   6  * Created:      2000
   7  * Description:  Common CPLB definitions for CPLB init
   8  *
   9  * Modified:
  10  *               Copyright 2004-2007 Analog Devices Inc.
  11  *
  12  * Bugs:         Enter bugs at http://blackfin.uclinux.org/
  13  *
  14  * This program is free software; you can redistribute it and/or modify
  15  * it under the terms of the GNU General Public License as published by
  16  * the Free Software Foundation; either version 2 of the License, or
  17  * (at your option) any later version.
  18  *
  19  * This program is distributed in the hope that it will be useful,
  20  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  21  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  22  * GNU General Public License for more details.
  23  *
  24  * You should have received a copy of the GNU General Public License
  25  * along with this program; if not, see the file COPYING, or write
  26  * to the Free Software Foundation, Inc.,
  27  * 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  28  */
  29
  30 #ifndef _CPLB_H
  31 #define _CPLB_H
  32
  33 #include <mach/anomaly.h>
  34
  35 #define SDRAM_IGENERIC    (CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_PORTPRIO)
  36 #define SDRAM_IKERNEL     (SDRAM_IGENERIC | CPLB_LOCK)
  37 #define L1_IMEMORY        (               CPLB_USER_RD | CPLB_VALID | CPLB_LOCK)
  38 #define SDRAM_INON_CHBL   (               CPLB_USER_RD | CPLB_VALID)
  39
  40 #if ANOMALY_05000158
  41 #define ANOMALY_05000158_WORKAROUND             0x200
  42 #else
  43 #define ANOMALY_05000158_WORKAROUND             0x0
  44 #endif
  45
  46 #define CPLB_COMMON     (CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND)
  47
  48 #ifdef CONFIG_BFIN_EXTMEM_WRITEBACK
  49 #define SDRAM_DGENERIC   (CPLB_L1_CHBL | CPLB_COMMON)
  50 #elif defined(CONFIG_BFIN_EXTMEM_WRITETHROUGH)
  51 #define SDRAM_DGENERIC   (CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW  | CPLB_COMMON)
  52 #else
  53 #define SDRAM_DGENERIC   (CPLB_COMMON)
  54 #endif
  55
  56 #define SDRAM_DNON_CHBL  (CPLB_COMMON)
  57 #define SDRAM_EBIU       (CPLB_COMMON)
  58 #define SDRAM_OOPS       (CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_LOCK | CPLB_DIRTY)
  59
  60 #define L1_DMEMORY       (CPLB_LOCK | CPLB_COMMON)
  61
  62 #ifdef CONFIG_SMP
  63 #define L2_ATTR          (INITIAL_T | I_CPLB | D_CPLB)
  64 #define L2_IMEMORY       (CPLB_COMMON | PAGE_SIZE_1MB)
  65 #define L2_DMEMORY       (CPLB_LOCK | CPLB_COMMON | PAGE_SIZE_1MB)
  66
  67 #else
  68 #define L2_ATTR          (INITIAL_T | SWITCH_T | I_CPLB | D_CPLB)
  69 # if defined(CONFIG_BFIN_L2_ICACHEABLE)
  70 # define L2_IMEMORY      (CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | PAGE_SIZE_1MB)
  71 # else
  72 # define L2_IMEMORY      (               CPLB_USER_RD | CPLB_VALID | PAGE_SIZE_1MB)
  73 # endif
  74
  75 # if defined(CONFIG_BFIN_L2_WRITEBACK)
  76 # define L2_DMEMORY      (CPLB_L1_CHBL | CPLB_COMMON | PAGE_SIZE_1MB)
  77 # elif defined(CONFIG_BFIN_L2_WRITETHROUGH)
  78 # define L2_DMEMORY      (CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_COMMON | PAGE_SIZE_1MB)
  79 # else
  80 # define L2_DMEMORY      (CPLB_COMMON | PAGE_SIZE_1MB)
  81 # endif
  82 #endif /* CONFIG_SMP */
  83
  84 #define SIZE_1K 0x00000400      /* 1K */
  85 #define SIZE_4K 0x00001000      /* 4K */
  86 #define SIZE_1M 0x00100000      /* 1M */
  87 #define SIZE_4M 0x00400000      /* 4M */
  88
  89 #define MAX_CPLBS 16
  90
  91 #define CPLB_ENABLE_ICACHE_P    0
  92 #define CPLB_ENABLE_DCACHE_P    1
  93 #define CPLB_ENABLE_DCACHE2_P   2
  94 #define CPLB_ENABLE_CPLBS_P     3       /* Deprecated! */
  95 #define CPLB_ENABLE_ICPLBS_P    4
  96 #define CPLB_ENABLE_DCPLBS_P    5
  97
  98 #define CPLB_ENABLE_ICACHE      (1<<CPLB_ENABLE_ICACHE_P)
  99 #define CPLB_ENABLE_DCACHE      (1<<CPLB_ENABLE_DCACHE_P)
 100 #define CPLB_ENABLE_DCACHE2     (1<<CPLB_ENABLE_DCACHE2_P)
 101 #define CPLB_ENABLE_CPLBS       (1<<CPLB_ENABLE_CPLBS_P)
 102 #define CPLB_ENABLE_ICPLBS      (1<<CPLB_ENABLE_ICPLBS_P)
 103 #define CPLB_ENABLE_DCPLBS      (1<<CPLB_ENABLE_DCPLBS_P)
 104 #define CPLB_ENABLE_ANY_CPLBS   CPLB_ENABLE_CPLBS | \
 105                                 CPLB_ENABLE_ICPLBS | \
 106                                 CPLB_ENABLE_DCPLBS
 107
 108 #define CPLB_RELOADED           0x0000
 109 #define CPLB_NO_UNLOCKED        0x0001
 110 #define CPLB_NO_ADDR_MATCH      0x0002
 111 #define CPLB_PROT_VIOL          0x0003
 112 #define CPLB_UNKNOWN_ERR        0x0004
 113
 114 #define CPLB_DEF_CACHE          CPLB_L1_CHBL | CPLB_WT
 115 #define CPLB_CACHE_ENABLED      CPLB_L1_CHBL | CPLB_DIRTY
 116
 117 #define CPLB_I_PAGE_MGMT        CPLB_LOCK | CPLB_VALID
 118 #define CPLB_D_PAGE_MGMT        CPLB_LOCK | CPLB_ALL_ACCESS | CPLB_VALID
 119 #define CPLB_DNOCACHE           CPLB_ALL_ACCESS | CPLB_VALID
 120 #define CPLB_DDOCACHE           CPLB_DNOCACHE | CPLB_DEF_CACHE
 121 #define CPLB_INOCACHE           CPLB_USER_RD | CPLB_VALID
 122 #define CPLB_IDOCACHE           CPLB_INOCACHE | CPLB_L1_CHBL
 123
 124 #define FAULT_RW        (1 << 16)
 125 #define FAULT_USERSUPV  (1 << 17)
 126 #define FAULT_CPLBBITS  0x0000ffff
 127
 128 #ifndef __ASSEMBLY__
 129
 130 static inline void _disable_cplb(u32 mmr, u32 mask)
 131 {
 132         u32 ctrl = bfin_read32(mmr) & ~mask;
 133         /* CSYNC to ensure load store ordering */
 134         __builtin_bfin_csync();
 135         bfin_write32(mmr, ctrl);
 136         __builtin_bfin_ssync();
 137 }
 138 static inline void disable_cplb(u32 mmr, u32 mask)
 139 {
 140         u32 ctrl = bfin_read32(mmr) & ~mask;
 141         CSYNC();
 142         bfin_write32(mmr, ctrl);
 143         SSYNC();
 144 }
 145 #define _disable_dcplb() _disable_cplb(DMEM_CONTROL, ENDCPLB)
 146 #define  disable_dcplb()  disable_cplb(DMEM_CONTROL, ENDCPLB)
 147 #define _disable_icplb() _disable_cplb(IMEM_CONTROL, ENICPLB)
 148 #define  disable_icplb()  disable_cplb(IMEM_CONTROL, ENICPLB)
 149
 150 static inline void _enable_cplb(u32 mmr, u32 mask)
 151 {
 152         u32 ctrl = bfin_read32(mmr) | mask;
 153         /* CSYNC to ensure load store ordering */
 154         __builtin_bfin_csync();
 155         bfin_write32(mmr, ctrl);
 156         __builtin_bfin_ssync();
 157 }
 158 static inline void enable_cplb(u32 mmr, u32 mask)
 159 {
 160         u32 ctrl = bfin_read32(mmr) | mask;
 161         CSYNC();
 162         bfin_write32(mmr, ctrl);
 163         SSYNC();
 164 }
 165 #define _enable_dcplb()  _enable_cplb(DMEM_CONTROL, ENDCPLB)
 166 #define  enable_dcplb()   enable_cplb(DMEM_CONTROL, ENDCPLB)
 167 #define _enable_icplb()  _enable_cplb(IMEM_CONTROL, ENICPLB)
 168 #define  enable_icplb()   enable_cplb(IMEM_CONTROL, ENICPLB)
 169
 170 #endif          /* __ASSEMBLY__ */
 171
 172 #endif          /* _CPLB_H */