arch/blackfin/include/asm/ipipe.h

   1 /*   -*- linux-c -*-
   2  *   include/asm-blackfin/ipipe.h
   3  *
   4  *   Copyright (C) 2002-2007 Philippe Gerum.
   5  *
   6  *   This program is free software; you can redistribute it and/or modify
   7  *   it under the terms of the GNU General Public License as published by
   8  *   the Free Software Foundation, Inc., 675 Mass Ave, Cambridge MA 02139,
   9  *   USA; either version 2 of the License, or (at your option) any later
  10  *   version.
  11  *
  12  *   This program is distributed in the hope that it will be useful,
  13  *   but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  *   GNU General Public License for more details.
  16  *
  17  *   You should have received a copy of the GNU General Public License
  18  *   along with this program; if not, write to the Free Software
  19  *   Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  20  */
  21
  22 #ifndef __ASM_BLACKFIN_IPIPE_H
  23 #define __ASM_BLACKFIN_IPIPE_H
  24
  25 #ifdef CONFIG_IPIPE
  26
  27 #include <linux/cpumask.h>
  28 #include <linux/list.h>
  29 #include <linux/threads.h>
  30 #include <linux/irq.h>
  31 #include <linux/ipipe_percpu.h>
  32 #include <asm/ptrace.h>
  33 #include <asm/irq.h>
  34 #include <asm/bitops.h>
  35 #include <asm/atomic.h>
  36 #include <asm/traps.h>
  37
  38 #define IPIPE_ARCH_STRING     "1.10-00"
  39 #define IPIPE_MAJOR_NUMBER    1
  40 #define IPIPE_MINOR_NUMBER    10
  41 #define IPIPE_PATCH_NUMBER    0
  42
  43 #ifdef CONFIG_SMP
  44 #error "I-pipe/blackfin: SMP not implemented"
  45 #else /* !CONFIG_SMP */
  46 #define ipipe_processor_id()    0
  47 #endif  /* CONFIG_SMP */
  48
  49 #define prepare_arch_switch(next)               \
  50 do {                                            \
  51         ipipe_schedule_notify(current, next);   \
  52         local_irq_disable_hw();                 \
  53 } while (0)
  54
  55 #define task_hijacked(p)                                                \
  56         ({                                                              \
  57                 int __x__ = __ipipe_root_domain_p;                      \
  58                 __clear_bit(IPIPE_SYNC_FLAG, &ipipe_root_cpudom_var(status)); \
  59                 if (__x__)                                              \
  60                         local_irq_enable_hw();                          \
  61                 !__x__;                                                 \
  62         })
  63
  64 struct ipipe_domain;
  65
  66 struct ipipe_sysinfo {
  67
  68         int ncpus;              /* Number of CPUs on board */
  69         u64 cpufreq;            /* CPU frequency (in Hz) */
  70
  71         /* Arch-dependent block */
  72
  73         struct {
  74                 unsigned tmirq; /* Timer tick IRQ */
  75                 u64 tmfreq;     /* Timer frequency */
  76         } archdep;
  77 };
  78
  79 #define ipipe_read_tsc(t)                                       \
  80         ({                                                      \
  81         unsigned long __cy2;                                    \
  82         __asm__ __volatile__ ("1: %0 = CYCLES2\n"               \
  83                                 "%1 = CYCLES\n"                 \
  84                                 "%2 = CYCLES2\n"                \
  85                                 "CC = %2 == %0\n"               \
  86                                 "if ! CC jump 1b\n"             \
  87                                 : "=d,a" (((unsigned long *)&t)[1]),    \
  88                                   "=d,a" (((unsigned long *)&t)[0]),    \
  89                                   "=d,a" (__cy2)                                \
  90                                 : /*no input*/ : "CC");                 \
  91         t;                                                              \
  92         })
  93
  94 #define ipipe_cpu_freq()        __ipipe_core_clock
  95 #define ipipe_tsc2ns(_t)        (((unsigned long)(_t)) * __ipipe_freq_scale)
  96 #define ipipe_tsc2us(_t)        (ipipe_tsc2ns(_t) / 1000 + 1)
  97
  98 /* Private interface -- Internal use only */
  99
 100 #define __ipipe_check_platform()        do { } while (0)
 101
 102 #define __ipipe_init_platform()         do { } while (0)
 103
 104 extern atomic_t __ipipe_irq_lvdepth[IVG15 + 1];
 105
 106 extern unsigned long __ipipe_irq_lvmask;
 107
 108 extern struct ipipe_domain ipipe_root;
 109
 110 /* enable/disable_irqdesc _must_ be used in pairs. */
 111
 112 void __ipipe_enable_irqdesc(struct ipipe_domain *ipd,
 113                             unsigned irq);
 114
 115 void __ipipe_disable_irqdesc(struct ipipe_domain *ipd,
 116                              unsigned irq);
 117
 118 #define __ipipe_enable_irq(irq)         (irq_desc[irq].chip->unmask(irq))
 119
 120 #define __ipipe_disable_irq(irq)        (irq_desc[irq].chip->mask(irq))
 121
 122 static inline int __ipipe_check_tickdev(const char *devname)
 123 {
 124         return 1;
 125 }
 126
 127 static inline void __ipipe_lock_root(void)
 128 {
 129         set_bit(IPIPE_SYNCDEFER_FLAG, &ipipe_root_cpudom_var(status));
 130 }
 131
 132 static inline void __ipipe_unlock_root(void)
 133 {
 134         clear_bit(IPIPE_SYNCDEFER_FLAG, &ipipe_root_cpudom_var(status));
 135 }
 136
 137 void __ipipe_enable_pipeline(void);
 138
 139 #define __ipipe_hook_critical_ipi(ipd) do { } while (0)
 140
 141 #define __ipipe_sync_pipeline  ___ipipe_sync_pipeline
 142 void ___ipipe_sync_pipeline(unsigned long syncmask);
 143
 144 void __ipipe_handle_irq(unsigned irq, struct pt_regs *regs);
 145
 146 int __ipipe_get_irq_priority(unsigned irq);
 147
 148 void __ipipe_stall_root_raw(void);
 149
 150 void __ipipe_unstall_root_raw(void);
 151
 152 void __ipipe_serial_debug(const char *fmt, ...);
 153
 154 asmlinkage void __ipipe_call_irqtail(unsigned long addr);
 155
 156 DECLARE_PER_CPU(struct pt_regs, __ipipe_tick_regs);
 157
 158 extern unsigned long __ipipe_core_clock;
 159
 160 extern unsigned long __ipipe_freq_scale;
 161
 162 extern unsigned long __ipipe_irq_tail_hook;
 163
 164 static inline unsigned long __ipipe_ffnz(unsigned long ul)
 165 {
 166         return ffs(ul) - 1;
 167 }
 168
 169 #define __ipipe_run_irqtail()  /* Must be a macro */                    \
 170         do {                                                            \
 171                 unsigned long __pending;                                \
 172                 CSYNC();                                                \
 173                 __pending = bfin_read_IPEND();                          \
 174                 if (__pending & 0x8000) {                               \
 175                         __pending &= ~0x8010;                           \
 176                         if (__pending && (__pending & (__pending - 1)) == 0) \
 177                                 __ipipe_call_irqtail(__ipipe_irq_tail_hook); \
 178                 }                                                       \
 179         } while (0)
 180
 181 #define __ipipe_run_isr(ipd, irq)                                       \
 182         do {                                                            \
 183                 if (!__ipipe_pipeline_head_p(ipd))                      \
 184                         local_irq_enable_hw();                          \
 185                 if (ipd == ipipe_root_domain) {                         \
 186                         if (unlikely(ipipe_virtual_irq_p(irq))) {       \
 187                                 irq_enter();                            \
 188                                 ipd->irqs[irq].handler(irq, ipd->irqs[irq].cookie); \
 189                                 irq_exit();                             \
 190                         } else                                          \
 191                                 ipd->irqs[irq].handler(irq, &__raw_get_cpu_var(__ipipe_tick_regs)); \
 192                 } else {                                                \
 193                         __clear_bit(IPIPE_SYNC_FLAG, &ipipe_cpudom_var(ipd, status)); \
 194                         ipd->irqs[irq].handler(irq, ipd->irqs[irq].cookie); \
 195                         /* Attempt to exit the outer interrupt level before \
 196                          * starting the deferred IRQ processing. */     \
 197                         __ipipe_run_irqtail();                          \
 198                         __set_bit(IPIPE_SYNC_FLAG, &ipipe_cpudom_var(ipd, status)); \
 199                 }                                                       \
 200                 local_irq_disable_hw();                                 \
 201         } while (0)
 202
 203 #define __ipipe_syscall_watched_p(p, sc)        \
 204         (((p)->flags & PF_EVNOTIFY) || (unsigned long)sc >= NR_syscalls)
 205
 206 void ipipe_init_irq_threads(void);
 207
 208 int ipipe_start_irq_thread(unsigned irq, struct irq_desc *desc);
 209
 210 #ifdef CONFIG_TICKSOURCE_CORETMR
 211 #define IRQ_SYSTMR              IRQ_CORETMR
 212 #define IRQ_PRIOTMR             IRQ_CORETMR
 213 #else
 214 #define IRQ_SYSTMR              IRQ_TIMER0
 215 #define IRQ_PRIOTMR             CONFIG_IRQ_TIMER0
 216 #endif
 217
 218 #ifdef CONFIG_BF561
 219 #define bfin_write_TIMER_DISABLE(val)   bfin_write_TMRS8_DISABLE(val)
 220 #define bfin_write_TIMER_ENABLE(val)    bfin_write_TMRS8_ENABLE(val)
 221 #define bfin_write_TIMER_STATUS(val)    bfin_write_TMRS8_STATUS(val)
 222 #define bfin_read_TIMER_STATUS()        bfin_read_TMRS8_STATUS()
 223 #elif defined(CONFIG_BF54x)
 224 #define bfin_write_TIMER_DISABLE(val)   bfin_write_TIMER_DISABLE0(val)
 225 #define bfin_write_TIMER_ENABLE(val)    bfin_write_TIMER_ENABLE0(val)
 226 #define bfin_write_TIMER_STATUS(val)    bfin_write_TIMER_STATUS0(val)
 227 #define bfin_read_TIMER_STATUS(val)     bfin_read_TIMER_STATUS0(val)
 228 #endif
 229
 230 #define __ipipe_root_tick_p(regs)       ((regs->ipend & 0x10) != 0)
 231
 232 #else /* !CONFIG_IPIPE */
 233
 234 #define task_hijacked(p)                0
 235 #define ipipe_trap_notify(t, r)         0
 236
 237 #define __ipipe_stall_root_raw()        do { } while (0)
 238 #define __ipipe_unstall_root_raw()      do { } while (0)
 239
 240 #define ipipe_init_irq_threads()                do { } while (0)
 241 #define ipipe_start_irq_thread(irq, desc)       0
 242
 243 #ifndef CONFIG_TICKSOURCE_GPTMR0
 244 #define IRQ_SYSTMR              IRQ_CORETMR
 245 #define IRQ_PRIOTMR             IRQ_CORETMR
 246 #else
 247 #define IRQ_SYSTMR              IRQ_TIMER0
 248 #define IRQ_PRIOTMR             CONFIG_IRQ_TIMER0
 249 #endif
 250
 251 #define __ipipe_root_tick_p(regs)       1
 252
 253 #endif /* !CONFIG_IPIPE */
 254
 255 #define ipipe_update_tick_evtdev(evtdev)        do { } while (0)
 256
 257 #endif  /* !__ASM_BLACKFIN_IPIPE_H */