2 * Blackfin CPLB initialization
4 * Copyright 2004-2007 Analog Devices Inc.
6 * Bugs: Enter bugs at http://blackfin.uclinux.org/
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, see the file COPYING, or write
20 * to the Free Software Foundation, Inc.,
21 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
23 #include <linux/module.h>
25 #include <asm/blackfin.h>
26 #include <asm/cacheflush.h>
28 #include <asm/cplbinit.h>
30 #define CPLB_MEM CONFIG_MAX_MEM_SIZE
33 * Number of required data CPLB switchtable entries
34 * MEMSIZE / 4 (we mostly install 4M page size CPLBs
35 * approx 16 for smaller 1MB page size CPLBs for allignment purposes
36 * 1 for L1 Data Memory
37 * possibly 1 for L2 Data Memory
38 * 1 for CONFIG_DEBUG_HUNT_FOR_ZERO
41 #define MAX_SWITCH_D_CPLBS (((CPLB_MEM / 4) + 16 + 1 + 1 + 1 \
42 + ASYNC_MEMORY_CPLB_COVERAGE) * 2)
45 * Number of required instruction CPLB switchtable entries
46 * MEMSIZE / 4 (we mostly install 4M page size CPLBs
47 * approx 12 for smaller 1MB page size CPLBs for allignment purposes
48 * 1 for L1 Instruction Memory
49 * possibly 1 for L2 Instruction Memory
50 * 1 for CONFIG_DEBUG_HUNT_FOR_ZERO
52 #define MAX_SWITCH_I_CPLBS (((CPLB_MEM / 4) + 12 + 1 + 1 + 1) * 2)
55 u_long icplb_table
[MAX_CPLBS
+ 1];
56 u_long dcplb_table
[MAX_CPLBS
+ 1];
58 #ifdef CONFIG_CPLB_SWITCH_TAB_L1
59 # define PDT_ATTR __attribute__((l1_data))
64 u_long ipdt_table
[MAX_SWITCH_I_CPLBS
+ 1] PDT_ATTR
;
65 u_long dpdt_table
[MAX_SWITCH_D_CPLBS
+ 1] PDT_ATTR
;
67 #ifdef CONFIG_CPLB_INFO
68 u_long ipdt_swapcount_table
[MAX_SWITCH_I_CPLBS
] PDT_ATTR
;
69 u_long dpdt_swapcount_table
[MAX_SWITCH_D_CPLBS
] PDT_ATTR
;
73 struct cplb_tab init_i
;
74 struct cplb_tab init_d
;
75 struct cplb_tab switch_i
;
76 struct cplb_tab switch_d
;
79 #if defined(CONFIG_BFIN_DCACHE) || defined(CONFIG_BFIN_ICACHE)
80 static struct cplb_desc cplb_data
[] = {
85 .attr
= INITIAL_T
| SWITCH_T
| I_CPLB
| D_CPLB
,
88 #if defined(CONFIG_DEBUG_HUNT_FOR_ZERO)
93 .name
= "Zero Pointer Guard Page",
96 .start
= L1_CODE_START
,
97 .end
= L1_CODE_START
+ L1_CODE_LENGTH
,
99 .attr
= INITIAL_T
| SWITCH_T
| I_CPLB
,
100 .i_conf
= L1_IMEMORY
,
103 .name
= "L1 I-Memory",
106 .start
= L1_DATA_A_START
,
107 .end
= L1_DATA_B_START
+ L1_DATA_B_LENGTH
,
109 .attr
= INITIAL_T
| SWITCH_T
| D_CPLB
,
111 .d_conf
= L1_DMEMORY
,
112 #if ((L1_DATA_A_LENGTH > 0) || (L1_DATA_B_LENGTH > 0))
117 .name
= "L1 D-Memory",
121 .end
= 0, /* dynamic */
123 .attr
= INITIAL_T
| SWITCH_T
| I_CPLB
| D_CPLB
,
124 .i_conf
= SDRAM_IGENERIC
,
125 .d_conf
= SDRAM_DGENERIC
,
127 .name
= "Kernel Memory",
130 .start
= 0, /* dynamic */
131 .end
= 0, /* dynamic */
133 .attr
= INITIAL_T
| SWITCH_T
| D_CPLB
,
134 .i_conf
= SDRAM_IGENERIC
,
135 .d_conf
= SDRAM_DNON_CHBL
,
137 .name
= "uClinux MTD Memory",
140 .start
= 0, /* dynamic */
141 .end
= 0, /* dynamic */
143 .attr
= INITIAL_T
| SWITCH_T
| D_CPLB
,
144 .d_conf
= SDRAM_DNON_CHBL
,
146 .name
= "Uncached DMA Zone",
149 .start
= 0, /* dynamic */
150 .end
= 0, /* dynamic */
152 .attr
= SWITCH_T
| D_CPLB
,
153 .i_conf
= 0, /* dynamic */
154 .d_conf
= 0, /* dynamic */
156 .name
= "Reserved Memory",
159 .start
= ASYNC_BANK0_BASE
,
160 .end
= ASYNC_BANK3_BASE
+ ASYNC_BANK3_SIZE
,
162 .attr
= SWITCH_T
| D_CPLB
,
163 .d_conf
= SDRAM_EBIU
,
165 .name
= "Asynchronous Memory Banks",
169 .end
= L2_START
+ L2_LENGTH
,
171 .attr
= SWITCH_T
| I_CPLB
| D_CPLB
,
172 .i_conf
= L2_IMEMORY
,
173 .d_conf
= L2_DMEMORY
,
174 .valid
= (L2_LENGTH
> 0),
178 .start
= BOOT_ROM_START
,
179 .end
= BOOT_ROM_START
+ BOOT_ROM_LENGTH
,
181 .attr
= SWITCH_T
| I_CPLB
| D_CPLB
,
182 .i_conf
= SDRAM_IGENERIC
,
183 .d_conf
= SDRAM_DGENERIC
,
185 .name
= "On-Chip BootROM",
189 static u16 __init
lock_kernel_check(u32 start
, u32 end
)
191 if (start
>= (u32
)_end
|| end
<= (u32
)_stext
)
194 /* This cplb block overlapped with kernel area. */
198 static unsigned short __init
199 fill_cplbtab(struct cplb_tab
*table
,
200 unsigned long start
, unsigned long end
,
201 unsigned long block_size
, unsigned long cplb_data
)
205 switch (block_size
) {
221 cplb_data
= (cplb_data
& ~(3 << 16)) | (i
<< 16);
223 while ((start
< end
) && (table
->pos
< table
->size
)) {
225 table
->tab
[table
->pos
++] = start
;
227 if (lock_kernel_check(start
, start
+ block_size
) == IN_KERNEL
)
228 table
->tab
[table
->pos
++] =
229 cplb_data
| CPLB_LOCK
| CPLB_DIRTY
;
231 table
->tab
[table
->pos
++] = cplb_data
;
238 static unsigned short __init
239 close_cplbtab(struct cplb_tab
*table
)
242 while (table
->pos
< table
->size
) {
244 table
->tab
[table
->pos
++] = 0;
245 table
->tab
[table
->pos
++] = 0; /* !CPLB_VALID */
250 /* helper function */
252 __fill_code_cplbtab(struct cplb_tab
*t
, int i
, u32 a_start
, u32 a_end
)
254 if (cplb_data
[i
].psize
) {
259 cplb_data
[i
].i_conf
);
261 #if defined(CONFIG_BFIN_ICACHE)
262 if (ANOMALY_05000263
&& i
== SDRAM_KERN
) {
267 cplb_data
[i
].i_conf
);
275 cplb_data
[i
].i_conf
);
280 cplb_data
[i
].i_conf
);
281 fill_cplbtab(t
, a_end
,
284 cplb_data
[i
].i_conf
);
290 __fill_data_cplbtab(struct cplb_tab
*t
, int i
, u32 a_start
, u32 a_end
)
292 if (cplb_data
[i
].psize
) {
297 cplb_data
[i
].d_conf
);
302 cplb_data
[i
].d_conf
);
303 fill_cplbtab(t
, a_start
,
305 cplb_data
[i
].d_conf
);
306 fill_cplbtab(t
, a_end
,
309 cplb_data
[i
].d_conf
);
313 void __init
generate_cplb_tables(void)
317 u32 a_start
, a_end
, as
, ae
, as_1m
;
319 struct cplb_tab
*t_i
= NULL
;
320 struct cplb_tab
*t_d
= NULL
;
323 printk(KERN_INFO
"NOMPU: setting up cplb tables for global access\n");
325 cplb
.init_i
.size
= MAX_CPLBS
;
326 cplb
.init_d
.size
= MAX_CPLBS
;
327 cplb
.switch_i
.size
= MAX_SWITCH_I_CPLBS
;
328 cplb
.switch_d
.size
= MAX_SWITCH_D_CPLBS
;
332 cplb
.switch_i
.pos
= 0;
333 cplb
.switch_d
.pos
= 0;
335 cplb
.init_i
.tab
= icplb_table
;
336 cplb
.init_d
.tab
= dcplb_table
;
337 cplb
.switch_i
.tab
= ipdt_table
;
338 cplb
.switch_d
.tab
= dpdt_table
;
340 cplb_data
[SDRAM_KERN
].end
= memory_end
;
342 #ifdef CONFIG_MTD_UCLINUX
343 cplb_data
[SDRAM_RAM_MTD
].start
= memory_mtd_start
;
344 cplb_data
[SDRAM_RAM_MTD
].end
= memory_mtd_start
+ mtd_size
;
345 cplb_data
[SDRAM_RAM_MTD
].valid
= mtd_size
> 0;
346 # if defined(CONFIG_ROMFS_FS)
347 cplb_data
[SDRAM_RAM_MTD
].attr
|= I_CPLB
;
350 * The ROMFS_FS size is often not multiple of 1MB.
351 * This can cause multiple CPLB sets covering the same memory area.
352 * This will then cause multiple CPLB hit exceptions.
353 * Workaround: We ensure a contiguous memory area by extending the kernel
354 * memory section over the mtd section.
355 * For ROMFS_FS memory must be covered with ICPLBs anyways.
356 * So there is no difference between kernel and mtd memory setup.
359 cplb_data
[SDRAM_KERN
].end
= memory_mtd_start
+ mtd_size
;;
360 cplb_data
[SDRAM_RAM_MTD
].valid
= 0;
364 cplb_data
[SDRAM_RAM_MTD
].valid
= 0;
367 cplb_data
[SDRAM_DMAZ
].start
= _ramend
- DMA_UNCACHED_REGION
;
368 cplb_data
[SDRAM_DMAZ
].end
= _ramend
;
370 cplb_data
[RES_MEM
].start
= _ramend
;
371 cplb_data
[RES_MEM
].end
= physical_mem_end
;
373 if (reserved_mem_dcache_on
)
374 cplb_data
[RES_MEM
].d_conf
= SDRAM_DGENERIC
;
376 cplb_data
[RES_MEM
].d_conf
= SDRAM_DNON_CHBL
;
378 if (reserved_mem_icache_on
)
379 cplb_data
[RES_MEM
].i_conf
= SDRAM_IGENERIC
;
381 cplb_data
[RES_MEM
].i_conf
= SDRAM_INON_CHBL
;
383 for (i
= ZERO_P
; i
< ARRAY_SIZE(cplb_data
); ++i
) {
384 if (!cplb_data
[i
].valid
)
387 as_1m
= cplb_data
[i
].start
% SIZE_1M
;
389 /* We need to make sure all sections are properly 1M aligned
390 * However between Kernel Memory and the Kernel mtd section, depending on the
391 * rootfs size, there can be overlapping memory areas.
394 if (as_1m
&& i
!= L1I_MEM
&& i
!= L1D_MEM
) {
395 #ifdef CONFIG_MTD_UCLINUX
396 if (i
== SDRAM_RAM_MTD
) {
397 if ((cplb_data
[SDRAM_KERN
].end
+ 1) > cplb_data
[SDRAM_RAM_MTD
].start
)
398 cplb_data
[SDRAM_RAM_MTD
].start
= (cplb_data
[i
].start
& (-2*SIZE_1M
)) + SIZE_1M
;
400 cplb_data
[SDRAM_RAM_MTD
].start
= (cplb_data
[i
].start
& (-2*SIZE_1M
));
403 printk(KERN_WARNING
"Unaligned Start of %s at 0x%X\n",
404 cplb_data
[i
].name
, cplb_data
[i
].start
);
407 as
= cplb_data
[i
].start
% SIZE_4M
;
408 ae
= cplb_data
[i
].end
% SIZE_4M
;
411 a_start
= cplb_data
[i
].start
+ (SIZE_4M
- (as
));
413 a_start
= cplb_data
[i
].start
;
415 a_end
= cplb_data
[i
].end
- ae
;
417 for (j
= INITIAL_T
; j
<= SWITCH_T
; j
++) {
421 if (cplb_data
[i
].attr
& INITIAL_T
) {
429 if (cplb_data
[i
].attr
& SWITCH_T
) {
430 t_i
= &cplb
.switch_i
;
431 t_d
= &cplb
.switch_d
;
443 if (cplb_data
[i
].attr
& I_CPLB
)
444 __fill_code_cplbtab(t_i
, i
, a_start
, a_end
);
446 if (cplb_data
[i
].attr
& D_CPLB
)
447 __fill_data_cplbtab(t_d
, i
, a_start
, a_end
);
453 close_cplbtab(&cplb
.init_i
);
454 close_cplbtab(&cplb
.init_d
);
456 cplb
.init_i
.tab
[cplb
.init_i
.pos
] = -1;
457 cplb
.init_d
.tab
[cplb
.init_d
.pos
] = -1;
458 cplb
.switch_i
.tab
[cplb
.switch_i
.pos
] = -1;
459 cplb
.switch_d
.tab
[cplb
.switch_d
.pos
] = -1;