2 * Blackfin CPLB initialization
4 * Copyright 2004-2007 Analog Devices Inc.
6 * Bugs: Enter bugs at http://blackfin.uclinux.org/
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, see the file COPYING, or write
20 * to the Free Software Foundation, Inc.,
21 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
24 #include <linux/module.h>
26 #include <asm/blackfin.h>
27 #include <asm/cacheflush.h>
29 #include <asm/cplbinit.h>
30 #include <asm/mem_map.h>
32 struct cplb_entry icplb_tbl
[NR_CPUS
][MAX_CPLBS
] PDT_ATTR
;
33 struct cplb_entry dcplb_tbl
[NR_CPUS
][MAX_CPLBS
] PDT_ATTR
;
35 int first_switched_icplb PDT_ATTR
;
36 int first_switched_dcplb PDT_ATTR
;
38 struct cplb_boundary dcplb_bounds
[9] PDT_ATTR
;
39 struct cplb_boundary icplb_bounds
[7] PDT_ATTR
;
41 int icplb_nr_bounds PDT_ATTR
;
42 int dcplb_nr_bounds PDT_ATTR
;
44 void __init
generate_cplb_tables_cpu(unsigned int cpu
)
49 struct cplb_entry
*d_tbl
= dcplb_tbl
[cpu
];
50 struct cplb_entry
*i_tbl
= icplb_tbl
[cpu
];
52 printk(KERN_INFO
"NOMPU: setting up cplb tables\n");
56 /* Set up the zero page. */
58 d_tbl
[i_d
++].data
= SDRAM_OOPS
| PAGE_SIZE_1KB
;
60 /* Cover kernel memory with 4M pages. */
63 for (; addr
< memory_start
; addr
+= 4 * 1024 * 1024) {
64 d_tbl
[i_d
].addr
= addr
;
65 d_tbl
[i_d
++].data
= SDRAM_DGENERIC
| PAGE_SIZE_4MB
;
66 i_tbl
[i_i
].addr
= addr
;
67 i_tbl
[i_i
++].data
= SDRAM_IGENERIC
| PAGE_SIZE_4MB
;
70 /* Cover L1 memory. One 4M area for code and data each is enough. */
71 if (L1_DATA_A_LENGTH
|| L1_DATA_B_LENGTH
) {
72 d_tbl
[i_d
].addr
= L1_DATA_A_START
;
73 d_tbl
[i_d
++].data
= L1_DMEMORY
| PAGE_SIZE_4MB
;
75 i_tbl
[i_i
].addr
= L1_CODE_START
;
76 i_tbl
[i_i
++].data
= L1_IMEMORY
| PAGE_SIZE_4MB
;
78 first_switched_dcplb
= i_d
;
79 first_switched_icplb
= i_i
;
81 BUG_ON(first_switched_dcplb
> MAX_CPLBS
);
82 BUG_ON(first_switched_icplb
> MAX_CPLBS
);
84 while (i_d
< MAX_CPLBS
)
85 d_tbl
[i_d
++].data
= 0;
86 while (i_i
< MAX_CPLBS
)
87 i_tbl
[i_i
++].data
= 0;
90 void __init
generate_cplb_tables_all(void)
95 /* Normal RAM, including MTD FS. */
96 #ifdef CONFIG_MTD_UCLINUX
97 dcplb_bounds
[i_d
].eaddr
= memory_mtd_start
+ mtd_size
;
99 dcplb_bounds
[i_d
].eaddr
= memory_end
;
101 dcplb_bounds
[i_d
++].data
= SDRAM_DGENERIC
;
102 /* DMA uncached region. */
103 if (DMA_UNCACHED_REGION
) {
104 dcplb_bounds
[i_d
].eaddr
= _ramend
;
105 dcplb_bounds
[i_d
++].data
= SDRAM_DNON_CHBL
;
107 if (_ramend
!= physical_mem_end
) {
108 /* Reserved memory. */
109 dcplb_bounds
[i_d
].eaddr
= physical_mem_end
;
110 dcplb_bounds
[i_d
++].data
= (reserved_mem_dcache_on
?
111 SDRAM_DGENERIC
: SDRAM_DNON_CHBL
);
113 /* Addressing hole up to the async bank. */
114 dcplb_bounds
[i_d
].eaddr
= ASYNC_BANK0_BASE
;
115 dcplb_bounds
[i_d
++].data
= 0;
117 dcplb_bounds
[i_d
].eaddr
= ASYNC_BANK3_BASE
+ ASYNC_BANK3_SIZE
;
118 dcplb_bounds
[i_d
++].data
= SDRAM_EBIU
;
119 /* Addressing hole up to BootROM. */
120 dcplb_bounds
[i_d
].eaddr
= BOOT_ROM_START
;
121 dcplb_bounds
[i_d
++].data
= 0;
122 /* BootROM -- largest one should be less than 1 meg. */
123 dcplb_bounds
[i_d
].eaddr
= BOOT_ROM_START
+ (1 * 1024 * 1024);
124 dcplb_bounds
[i_d
++].data
= SDRAM_DGENERIC
;
126 /* Addressing hole up to L2 SRAM. */
127 dcplb_bounds
[i_d
].eaddr
= L2_START
;
128 dcplb_bounds
[i_d
++].data
= 0;
130 dcplb_bounds
[i_d
].eaddr
= L2_START
+ L2_LENGTH
;
131 dcplb_bounds
[i_d
++].data
= L2_DMEMORY
;
133 dcplb_nr_bounds
= i_d
;
134 BUG_ON(dcplb_nr_bounds
> ARRAY_SIZE(dcplb_bounds
));
137 /* Normal RAM, including MTD FS. */
138 #ifdef CONFIG_MTD_UCLINUX
139 icplb_bounds
[i_i
].eaddr
= memory_mtd_start
+ mtd_size
;
141 icplb_bounds
[i_i
].eaddr
= memory_end
;
143 icplb_bounds
[i_i
++].data
= SDRAM_IGENERIC
;
144 /* DMA uncached region. */
145 if (DMA_UNCACHED_REGION
) {
146 icplb_bounds
[i_i
].eaddr
= _ramend
;
147 icplb_bounds
[i_i
++].data
= 0;
149 if (_ramend
!= physical_mem_end
) {
150 /* Reserved memory. */
151 icplb_bounds
[i_i
].eaddr
= physical_mem_end
;
152 icplb_bounds
[i_i
++].data
= (reserved_mem_icache_on
?
153 SDRAM_IGENERIC
: SDRAM_INON_CHBL
);
155 /* Addressing hole up to BootROM. */
156 icplb_bounds
[i_i
].eaddr
= BOOT_ROM_START
;
157 icplb_bounds
[i_i
++].data
= 0;
158 /* BootROM -- largest one should be less than 1 meg. */
159 icplb_bounds
[i_i
].eaddr
= BOOT_ROM_START
+ (1 * 1024 * 1024);
160 icplb_bounds
[i_i
++].data
= SDRAM_IGENERIC
;
162 /* Addressing hole up to L2 SRAM, including the async bank. */
163 icplb_bounds
[i_i
].eaddr
= L2_START
;
164 icplb_bounds
[i_i
++].data
= 0;
166 icplb_bounds
[i_i
].eaddr
= L2_START
+ L2_LENGTH
;
167 icplb_bounds
[i_i
++].data
= L2_IMEMORY
;
169 icplb_nr_bounds
= i_i
;
170 BUG_ON(icplb_nr_bounds
> ARRAY_SIZE(icplb_bounds
));