2 * debugfs interface to core/system MMRs
4 * Copyright 2007-2011 Analog Devices Inc.
6 * Licensed under the GPL-2 or later
9 #include <linux/debugfs.h>
11 #include <linux/kernel.h>
12 #include <linux/module.h>
14 #include <asm/blackfin.h>
16 #include <asm/gptimers.h>
17 #include <asm/bfin_can.h>
18 #include <asm/bfin_dma.h>
19 #include <asm/bfin_ppi.h>
20 #include <asm/bfin_serial.h>
21 #include <asm/bfin5xx_spi.h>
22 #include <asm/bfin_twi.h>
24 /* Common code defines PORT_MUX on us, so redirect the MMR back locally */
27 #define PORT_MUX BFIN_PORT_MUX
30 #define _d(name, bits, addr, perms) debugfs_create_x##bits(name, perms, parent, (u##bits *)(addr))
31 #define d(name, bits, addr) _d(name, bits, addr, S_IRUSR|S_IWUSR)
32 #define d_RO(name, bits, addr) _d(name, bits, addr, S_IRUSR)
33 #define d_WO(name, bits, addr) _d(name, bits, addr, S_IWUSR)
35 #define D_RO(name, bits) d_RO(#name, bits, name)
36 #define D_WO(name, bits) d_WO(#name, bits, name)
37 #define D32(name) d(#name, 32, name)
38 #define D16(name) d(#name, 16, name)
40 #define REGS_OFF(peri, mmr) offsetof(struct bfin_##peri##_regs, mmr)
41 #define __REGS(peri, sname, rname) \
43 struct bfin_##peri##_regs r; \
44 void *addr = (void *)(base + REGS_OFF(peri, rname)); \
45 strcpy(_buf, sname); \
46 if (sizeof(r.rname) == 2) \
47 debugfs_create_x16(buf, S_IRUSR|S_IWUSR, parent, addr); \
49 debugfs_create_x32(buf, S_IRUSR|S_IWUSR, parent, addr); \
51 #define REGS_STR_PFX(buf, pfx, num) \
54 sprintf(buf, #pfx "%i_", num) : \
55 sprintf(buf, #pfx "_")); \
57 #define REGS_STR_PFX_C(buf, pfx, num) \
60 sprintf(buf, #pfx "%c_", 'A' + num) : \
61 sprintf(buf, #pfx "_")); \
65 * Core registers (not memory mapped)
67 extern u32 last_seqstat
;
69 static int debug_cclk_get(void *data
, u64
*val
)
74 DEFINE_SIMPLE_ATTRIBUTE(fops_debug_cclk
, debug_cclk_get
, NULL
, "0x%08llx\n");
76 static int debug_sclk_get(void *data
, u64
*val
)
81 DEFINE_SIMPLE_ATTRIBUTE(fops_debug_sclk
, debug_sclk_get
, NULL
, "0x%08llx\n");
83 #define DEFINE_SYSREG(sr, pre, post) \
84 static int sysreg_##sr##_get(void *data, u64 *val) \
88 __asm__ __volatile__("%0 = " #sr ";" : "=d"(tmp)); \
92 static int sysreg_##sr##_set(void *data, u64 val) \
94 unsigned long tmp = val; \
95 __asm__ __volatile__(#sr " = %0;" : : "d"(tmp)); \
99 DEFINE_SIMPLE_ATTRIBUTE(fops_sysreg_##sr, sysreg_##sr##_get, sysreg_##sr##_set, "0x%08llx\n")
101 DEFINE_SYSREG(cycles
, , );
102 DEFINE_SYSREG(cycles2
, __asm__
__volatile__("%0 = cycles;" : "=d"(tmp
)), );
103 DEFINE_SYSREG(emudat
, , );
104 DEFINE_SYSREG(seqstat
, , );
105 DEFINE_SYSREG(syscfg
, , CSYNC());
106 #define D_SYSREG(sr) debugfs_create_file(#sr, S_IRUSR|S_IWUSR, parent, NULL, &fops_sysreg_##sr)
111 #define CAN_OFF(mmr) REGS_OFF(can, mmr)
112 #define __CAN(uname, lname) __REGS(can, #uname, lname)
113 static void __init __maybe_unused
114 bfin_debug_mmrs_can(struct dentry
*parent
, unsigned long base
, int num
)
116 static struct dentry
*am
, *mb
;
118 char buf
[32], *_buf
= REGS_STR_PFX(buf
, CAN
, num
);
121 am
= debugfs_create_dir("am", parent
);
122 mb
= debugfs_create_dir("mb", parent
);
133 __CAN(MBTIF1
, mbtif1
);
134 __CAN(MBRIF1
, mbrif1
);
147 __CAN(MBTIF2
, mbtif2
);
148 __CAN(MBRIF2
, mbrif2
);
154 __CAN(TIMING
, timing
);
156 __CAN(STATUS
, status
);
161 __CAN(CONTROL
, control
);
163 __CAN(VERSION
, version
);
167 /*__CAN(UCREG, ucreg); no longer exists */
171 __CAN(VERSION2
, version2
);
173 for (i
= 0; i
< 32; ++i
) {
174 sprintf(_buf
, "AM%02iL", i
);
175 debugfs_create_x16(buf
, S_IRUSR
|S_IWUSR
, am
,
176 (u16
*)(base
+ CAN_OFF(msk
[i
].aml
)));
177 sprintf(_buf
, "AM%02iH", i
);
178 debugfs_create_x16(buf
, S_IRUSR
|S_IWUSR
, am
,
179 (u16
*)(base
+ CAN_OFF(msk
[i
].amh
)));
181 for (j
= 0; j
< 3; ++j
) {
182 sprintf(_buf
, "MB%02i_DATA%i", i
, j
);
183 debugfs_create_x16(buf
, S_IRUSR
|S_IWUSR
, mb
,
184 (u16
*)(base
+ CAN_OFF(chl
[i
].data
[j
*2])));
186 sprintf(_buf
, "MB%02i_LENGTH", i
);
187 debugfs_create_x16(buf
, S_IRUSR
|S_IWUSR
, mb
,
188 (u16
*)(base
+ CAN_OFF(chl
[i
].dlc
)));
189 sprintf(_buf
, "MB%02i_TIMESTAMP", i
);
190 debugfs_create_x16(buf
, S_IRUSR
|S_IWUSR
, mb
,
191 (u16
*)(base
+ CAN_OFF(chl
[i
].tsv
)));
192 sprintf(_buf
, "MB%02i_ID0", i
);
193 debugfs_create_x16(buf
, S_IRUSR
|S_IWUSR
, mb
,
194 (u16
*)(base
+ CAN_OFF(chl
[i
].id0
)));
195 sprintf(_buf
, "MB%02i_ID1", i
);
196 debugfs_create_x16(buf
, S_IRUSR
|S_IWUSR
, mb
,
197 (u16
*)(base
+ CAN_OFF(chl
[i
].id1
)));
200 #define CAN(num) bfin_debug_mmrs_can(parent, CAN##num##_MC1, num)
205 #define __DMA(uname, lname) __REGS(dma, #uname, lname)
206 static void __init __maybe_unused
207 bfin_debug_mmrs_dma(struct dentry
*parent
, unsigned long base
, int num
, char mdma
, const char *pfx
)
212 _buf
= buf
+ sprintf(buf
, "%s_%c%i_", pfx
, mdma
, num
);
214 _buf
= buf
+ sprintf(buf
, "%s%i_", pfx
, num
);
216 __DMA(NEXT_DESC_PTR
, next_desc_ptr
);
217 __DMA(START_ADDR
, start_addr
);
218 __DMA(CONFIG
, config
);
219 __DMA(X_COUNT
, x_count
);
220 __DMA(X_MODIFY
, x_modify
);
221 __DMA(Y_COUNT
, y_count
);
222 __DMA(Y_MODIFY
, y_modify
);
223 __DMA(CURR_DESC_PTR
, curr_desc_ptr
);
224 __DMA(CURR_ADDR
, curr_addr
);
225 __DMA(IRQ_STATUS
, irq_status
);
226 if (strcmp(pfx
, "IMDMA") != 0)
227 __DMA(PERIPHERAL_MAP
, peripheral_map
);
228 __DMA(CURR_X_COUNT
, curr_x_count
);
229 __DMA(CURR_Y_COUNT
, curr_y_count
);
231 #define _DMA(num, base, mdma, pfx) bfin_debug_mmrs_dma(parent, base, num, mdma, pfx "DMA")
232 #define DMA(num) _DMA(num, DMA##num##_NEXT_DESC_PTR, 0, "")
233 #define _MDMA(num, x) \
235 _DMA(num, x##DMA_D##num##_NEXT_DESC_PTR, 'D', #x); \
236 _DMA(num, x##DMA_S##num##_NEXT_DESC_PTR, 'S', #x); \
238 #define MDMA(num) _MDMA(num, M)
239 #define IMDMA(num) _MDMA(num, IM)
244 #define __EPPI(uname, lname) __REGS(eppi, #uname, lname)
245 static void __init __maybe_unused
246 bfin_debug_mmrs_eppi(struct dentry
*parent
, unsigned long base
, int num
)
248 char buf
[32], *_buf
= REGS_STR_PFX(buf
, EPPI
, num
);
249 __EPPI(STATUS
, status
);
250 __EPPI(HCOUNT
, hcount
);
251 __EPPI(HDELAY
, hdelay
);
252 __EPPI(VCOUNT
, vcount
);
253 __EPPI(VDELAY
, vdelay
);
254 __EPPI(FRAME
, frame
);
256 __EPPI(CLKDIV
, clkdiv
);
257 __EPPI(CONTROL
, control
);
258 __EPPI(FS1W_HBL
, fs1w_hbl
);
259 __EPPI(FS1P_AVPL
, fs1p_avpl
);
260 __EPPI(FS2W_LVB
, fs2w_lvb
);
261 __EPPI(FS2P_LAVF
, fs2p_lavf
);
264 #define EPPI(num) bfin_debug_mmrs_eppi(parent, EPPI##num##_STATUS, num)
267 * General Purpose Timers
269 #define __GPTIMER(uname, lname) __REGS(gptimer, #uname, lname)
270 static void __init __maybe_unused
271 bfin_debug_mmrs_gptimer(struct dentry
*parent
, unsigned long base
, int num
)
273 char buf
[32], *_buf
= REGS_STR_PFX(buf
, TIMER
, num
);
274 __GPTIMER(CONFIG
, config
);
275 __GPTIMER(COUNTER
, counter
);
276 __GPTIMER(PERIOD
, period
);
277 __GPTIMER(WIDTH
, width
);
279 #define GPTIMER(num) bfin_debug_mmrs_gptimer(parent, TIMER##num##_CONFIG, num)
281 #define GPTIMER_GROUP_OFF(mmr) REGS_OFF(gptimer_group, mmr)
282 #define __GPTIMER_GROUP(uname, lname) __REGS(gptimer_group, #uname, lname)
283 static void __init __maybe_unused
284 bfin_debug_mmrs_gptimer_group(struct dentry
*parent
, unsigned long base
, int num
)
289 _buf
= buf
+ sprintf(buf
, "TIMER_");
290 __GPTIMER_GROUP(ENABLE
, enable
);
291 __GPTIMER_GROUP(DISABLE
, disable
);
292 __GPTIMER_GROUP(STATUS
, status
);
294 /* These MMRs are a bit odd as the group # is a suffix */
295 _buf
= buf
+ sprintf(buf
, "TIMER_ENABLE%i", num
);
296 d(buf
, 16, base
+ GPTIMER_GROUP_OFF(enable
));
298 _buf
= buf
+ sprintf(buf
, "TIMER_DISABLE%i", num
);
299 d(buf
, 16, base
+ GPTIMER_GROUP_OFF(disable
));
301 _buf
= buf
+ sprintf(buf
, "TIMER_STATUS%i", num
);
302 d(buf
, 32, base
+ GPTIMER_GROUP_OFF(status
));
305 #define GPTIMER_GROUP(mmr, num) bfin_debug_mmrs_gptimer_group(parent, mmr, num)
310 #define __HMDMA(uname, lname) __REGS(hmdma, #uname, lname)
311 static void __init __maybe_unused
312 bfin_debug_mmrs_hmdma(struct dentry
*parent
, unsigned long base
, int num
)
314 char buf
[32], *_buf
= REGS_STR_PFX(buf
, HMDMA
, num
);
315 __HMDMA(CONTROL
, control
);
316 __HMDMA(ECINIT
, ecinit
);
317 __HMDMA(BCINIT
, bcinit
);
318 __HMDMA(ECURGENT
, ecurgent
);
319 __HMDMA(ECOVERFLOW
, ecoverflow
);
320 __HMDMA(ECOUNT
, ecount
);
321 __HMDMA(BCOUNT
, bcount
);
323 #define HMDMA(num) bfin_debug_mmrs_hmdma(parent, HMDMA##num##_CONTROL, num)
328 #define bfin_gpio_regs gpio_port_t
329 #define __PORT(uname, lname) __REGS(gpio, #uname, lname)
330 static void __init __maybe_unused
331 bfin_debug_mmrs_port(struct dentry
*parent
, unsigned long base
, int num
)
335 _buf
= REGS_STR_PFX_C(buf
, PORT
, num
);
336 __PORT(FER
, port_fer
);
337 __PORT(SET
, data_set
);
338 __PORT(CLEAR
, data_clear
);
339 __PORT(DIR_SET
, dir_set
);
340 __PORT(DIR_CLEAR
, dir_clear
);
342 __PORT(MUX
, port_mux
);
344 _buf
= buf
+ sprintf(buf
, "PORT%cIO_", num
);
345 __PORT(CLEAR
, data_clear
);
346 __PORT(SET
, data_set
);
347 __PORT(TOGGLE
, toggle
);
348 __PORT(MASKA
, maska
);
349 __PORT(MASKA_CLEAR
, maska_clear
);
350 __PORT(MASKA_SET
, maska_set
);
351 __PORT(MASKA_TOGGLE
, maska_toggle
);
352 __PORT(MASKB
, maskb
);
353 __PORT(MASKB_CLEAR
, maskb_clear
);
354 __PORT(MASKB_SET
, maskb_set
);
355 __PORT(MASKB_TOGGLE
, maskb_toggle
);
357 __PORT(POLAR
, polar
);
363 d(buf
, 16, base
+ REGS_OFF(gpio
, data
));
365 #define PORT(base, num) bfin_debug_mmrs_port(parent, base, num)
370 #define __PPI(uname, lname) __REGS(ppi, #uname, lname)
371 static void __init __maybe_unused
372 bfin_debug_mmrs_ppi(struct dentry
*parent
, unsigned long base
, int num
)
374 char buf
[32], *_buf
= REGS_STR_PFX(buf
, PPI
, num
);
375 __PPI(CONTROL
, control
);
376 __PPI(STATUS
, status
);
381 #define PPI(num) bfin_debug_mmrs_ppi(parent, PPI##num##_CONTROL, num)
386 #define __SPI(uname, lname) __REGS(spi, #uname, lname)
387 static void __init __maybe_unused
388 bfin_debug_mmrs_spi(struct dentry
*parent
, unsigned long base
, int num
)
390 char buf
[32], *_buf
= REGS_STR_PFX(buf
, SPI
, num
);
397 __SPI(SHADOW
, shadow
);
399 #define SPI(num) bfin_debug_mmrs_spi(parent, SPI##num##_REGBASE, num)
404 static inline int sport_width(void *mmr
)
406 unsigned long lmmr
= (unsigned long)mmr
;
407 if ((lmmr
& 0xff) == 0x10)
408 /* SPORT#_TX has 0x10 offset -> SPORT#_TCR2 has 0x04 offset */
411 /* SPORT#_RX has 0x18 offset -> SPORT#_RCR2 has 0x24 offset */
413 /* extract SLEN field from control register 2 and add 1 */
414 return (bfin_read16(lmmr
) & 0x1f) + 1;
416 static int sport_set(void *mmr
, u64 val
)
419 local_irq_save(flags
);
420 if (sport_width(mmr
) <= 16)
421 bfin_write16(mmr
, val
);
423 bfin_write32(mmr
, val
);
424 local_irq_restore(flags
);
427 static int sport_get(void *mmr
, u64
*val
)
430 local_irq_save(flags
);
431 if (sport_width(mmr
) <= 16)
432 *val
= bfin_read16(mmr
);
434 *val
= bfin_read32(mmr
);
435 local_irq_restore(flags
);
438 DEFINE_SIMPLE_ATTRIBUTE(fops_sport
, sport_get
, sport_set
, "0x%08llx\n");
439 /*DEFINE_SIMPLE_ATTRIBUTE(fops_sport_ro, sport_get, NULL, "0x%08llx\n");*/
440 DEFINE_SIMPLE_ATTRIBUTE(fops_sport_wo
, NULL
, sport_set
, "0x%08llx\n");
441 #define SPORT_OFF(mmr) (SPORT0_##mmr - SPORT0_TCR1)
442 #define _D_SPORT(name, perms, fops) \
444 strcpy(_buf, #name); \
445 debugfs_create_file(buf, perms, parent, (void *)(base + SPORT_OFF(name)), fops); \
447 #define __SPORT_RW(name) _D_SPORT(name, S_IRUSR|S_IWUSR, &fops_sport)
448 #define __SPORT_RO(name) _D_SPORT(name, S_IRUSR, &fops_sport_ro)
449 #define __SPORT_WO(name) _D_SPORT(name, S_IWUSR, &fops_sport_wo)
450 #define __SPORT(name, bits) \
452 strcpy(_buf, #name); \
453 debugfs_create_x##bits(buf, S_IRUSR|S_IWUSR, parent, (u##bits *)(base + SPORT_OFF(name))); \
455 static void __init __maybe_unused
456 bfin_debug_mmrs_sport(struct dentry
*parent
, unsigned long base
, int num
)
458 char buf
[32], *_buf
= REGS_STR_PFX(buf
, SPORT
, num
);
470 __SPORT(RCLKDIV
, 16);
476 __SPORT(TCLKDIV
, 16);
482 #define SPORT(num) bfin_debug_mmrs_sport(parent, SPORT##num##_TCR1, num)
487 #define __TWI(uname, lname) __REGS(twi, #uname, lname)
488 static void __init __maybe_unused
489 bfin_debug_mmrs_twi(struct dentry
*parent
, unsigned long base
, int num
)
491 char buf
[32], *_buf
= REGS_STR_PFX(buf
, TWI
, num
);
492 __TWI(CLKDIV
, clkdiv
);
493 __TWI(CONTROL
, control
);
494 __TWI(SLAVE_CTL
, slave_ctl
);
495 __TWI(SLAVE_STAT
, slave_stat
);
496 __TWI(SLAVE_ADDR
, slave_addr
);
497 __TWI(MASTER_CTL
, master_ctl
);
498 __TWI(MASTER_STAT
, master_stat
);
499 __TWI(MASTER_ADDR
, master_addr
);
500 __TWI(INT_STAT
, int_stat
);
501 __TWI(INT_MASK
, int_mask
);
502 __TWI(FIFO_CTL
, fifo_ctl
);
503 __TWI(FIFO_STAT
, fifo_stat
);
504 __TWI(XMT_DATA8
, xmt_data8
);
505 __TWI(XMT_DATA16
, xmt_data16
);
506 __TWI(RCV_DATA8
, rcv_data8
);
507 __TWI(RCV_DATA16
, rcv_data16
);
509 #define TWI(num) bfin_debug_mmrs_twi(parent, TWI##num##_CLKDIV, num)
514 #define __UART(uname, lname) __REGS(uart, #uname, lname)
515 static void __init __maybe_unused
516 bfin_debug_mmrs_uart(struct dentry
*parent
, unsigned long base
, int num
)
518 char buf
[32], *_buf
= REGS_STR_PFX(buf
, UART
, num
);
519 #ifdef BFIN_UART_BF54X_STYLE
528 __UART(IER_SET
, ier_set
);
529 __UART(IER_CLEAR
, ier_clear
);
547 #define UART(num) bfin_debug_mmrs_uart(parent, UART##num##_DLL, num)
550 * The actual debugfs generation
552 static struct dentry
*debug_mmrs_dentry
;
554 static int __init
bfin_debug_mmrs_init(void)
556 struct dentry
*top
, *parent
;
558 pr_info("debug-mmrs: setting up Blackfin MMR debugfs\n");
560 top
= debugfs_create_dir("blackfin", NULL
);
564 parent
= debugfs_create_dir("core_regs", top
);
565 debugfs_create_file("cclk", S_IRUSR
, parent
, NULL
, &fops_debug_cclk
);
566 debugfs_create_file("sclk", S_IRUSR
, parent
, NULL
, &fops_debug_sclk
);
567 debugfs_create_x32("last_seqstat", S_IRUSR
, parent
, &last_seqstat
);
575 parent
= debugfs_create_dir("ctimer", top
);
581 parent
= debugfs_create_dir("cec", top
);
604 parent
= debugfs_create_dir("debug", top
);
608 parent
= debugfs_create_dir("mmu", top
);
609 D32(SRAM_BASE_ADDRESS
);
642 D32(DCPLB_FAULT_ADDR
);
681 D32(ICPLB_FAULT_ADDR
);
684 if (!ANOMALY_05000481
) {
690 parent
= debugfs_create_dir("perf", top
);
695 parent
= debugfs_create_dir("trace", top
);
700 parent
= debugfs_create_dir("watchpoint", top
);
723 parent
= debugfs_create_dir("atapi", top
);
726 D16(ATAPI_DEV_RXBUF
);
727 D16(ATAPI_DEV_TXBUF
);
728 D16(ATAPI_DMA_TFRCNT
);
730 D16(ATAPI_INT_STATUS
);
731 D16(ATAPI_LINE_STATUS
);
732 D16(ATAPI_MULTI_TIM_0
);
733 D16(ATAPI_MULTI_TIM_1
);
734 D16(ATAPI_MULTI_TIM_2
);
735 D16(ATAPI_PIO_TFRCNT
);
736 D16(ATAPI_PIO_TIM_0
);
737 D16(ATAPI_PIO_TIM_1
);
738 D16(ATAPI_REG_TIM_0
);
741 D16(ATAPI_TERMINATE
);
742 D16(ATAPI_UDMAOUT_TFRCNT
);
743 D16(ATAPI_ULTRA_TIM_0
);
744 D16(ATAPI_ULTRA_TIM_1
);
745 D16(ATAPI_ULTRA_TIM_2
);
746 D16(ATAPI_ULTRA_TIM_3
);
747 D16(ATAPI_UMAIN_TFRCNT
);
751 #if defined(CAN_MC1) || defined(CAN0_MC1) || defined(CAN1_MC1)
752 parent
= debugfs_create_dir("can", top
);
754 bfin_debug_mmrs_can(parent
, CAN_MC1
, -1);
765 parent
= debugfs_create_dir("counter", top
);
776 parent
= debugfs_create_dir("dmac", top
);
794 /* XXX: should rewrite the MMR map */
795 # define DMA0_NEXT_DESC_PTR DMA2_0_NEXT_DESC_PTR
796 # define DMA1_NEXT_DESC_PTR DMA2_1_NEXT_DESC_PTR
797 # define DMA2_NEXT_DESC_PTR DMA2_2_NEXT_DESC_PTR
798 # define DMA3_NEXT_DESC_PTR DMA2_3_NEXT_DESC_PTR
799 # define DMA4_NEXT_DESC_PTR DMA2_4_NEXT_DESC_PTR
800 # define DMA5_NEXT_DESC_PTR DMA2_5_NEXT_DESC_PTR
801 # define DMA6_NEXT_DESC_PTR DMA2_6_NEXT_DESC_PTR
802 # define DMA7_NEXT_DESC_PTR DMA2_7_NEXT_DESC_PTR
803 # define DMA8_NEXT_DESC_PTR DMA2_8_NEXT_DESC_PTR
804 # define DMA9_NEXT_DESC_PTR DMA2_9_NEXT_DESC_PTR
805 # define DMA10_NEXT_DESC_PTR DMA2_10_NEXT_DESC_PTR
806 # define DMA11_NEXT_DESC_PTR DMA2_11_NEXT_DESC_PTR
807 # define DMA12_NEXT_DESC_PTR DMA1_0_NEXT_DESC_PTR
808 # define DMA13_NEXT_DESC_PTR DMA1_1_NEXT_DESC_PTR
809 # define DMA14_NEXT_DESC_PTR DMA1_2_NEXT_DESC_PTR
810 # define DMA15_NEXT_DESC_PTR DMA1_3_NEXT_DESC_PTR
811 # define DMA16_NEXT_DESC_PTR DMA1_4_NEXT_DESC_PTR
812 # define DMA17_NEXT_DESC_PTR DMA1_5_NEXT_DESC_PTR
813 # define DMA18_NEXT_DESC_PTR DMA1_6_NEXT_DESC_PTR
814 # define DMA19_NEXT_DESC_PTR DMA1_7_NEXT_DESC_PTR
815 # define DMA20_NEXT_DESC_PTR DMA1_8_NEXT_DESC_PTR
816 # define DMA21_NEXT_DESC_PTR DMA1_9_NEXT_DESC_PTR
817 # define DMA22_NEXT_DESC_PTR DMA1_10_NEXT_DESC_PTR
818 # define DMA23_NEXT_DESC_PTR DMA1_11_NEXT_DESC_PTR
820 parent
= debugfs_create_dir("dma", top
);
830 #ifdef DMA8_NEXT_DESC_PTR
836 #ifdef DMA12_NEXT_DESC_PTR
846 #ifdef DMA20_NEXT_DESC_PTR
853 parent
= debugfs_create_dir("ebiu_amc", top
);
865 parent
= debugfs_create_dir("ebiu_sdram", top
);
866 # ifdef __ADSPBF561__
877 parent
= debugfs_create_dir("ebiu_ddr", top
);
914 parent
= debugfs_create_dir("emac", top
);
927 D32(EMAC_RXC_ALLFRM
);
928 D32(EMAC_RXC_ALLOCT
);
930 D32(EMAC_RXC_DMAOVF
);
933 D32(EMAC_RXC_GE1024
);
934 D32(EMAC_RXC_LNERRI
);
935 D32(EMAC_RXC_LNERRO
);
937 D32(EMAC_RXC_LT1024
);
941 D32(EMAC_RXC_MACCTL
);
945 D32(EMAC_RXC_OPCODE
);
949 D32(EMAC_RXC_UNICST
);
959 D32(EMAC_TXC_ALLFRM
);
960 D32(EMAC_TXC_ALLOCT
);
962 D32(EMAC_TXC_CRSERR
);
964 D32(EMAC_TXC_DMAUND
);
966 D32(EMAC_TXC_GE1024
);
967 D32(EMAC_TXC_GT1COL
);
968 D32(EMAC_TXC_LATECL
);
969 D32(EMAC_TXC_LT1024
);
973 D32(EMAC_TXC_MACCTL
);
977 D32(EMAC_TXC_UNICST
);
978 D32(EMAC_TXC_XS_COL
);
979 D32(EMAC_TXC_XS_DFR
);
986 D32(EMAC_WKUP_FFCMD
);
987 D32(EMAC_WKUP_FFCRC0
);
988 D32(EMAC_WKUP_FFCRC1
);
989 D32(EMAC_WKUP_FFMSK0
);
990 D32(EMAC_WKUP_FFMSK1
);
991 D32(EMAC_WKUP_FFMSK2
);
992 D32(EMAC_WKUP_FFMSK3
);
993 D32(EMAC_WKUP_FFOFF
);
994 # ifdef EMAC_PTP_ACCR
996 D32(EMAC_PTP_ADDEND
);
997 D32(EMAC_PTP_ALARMHI
);
998 D32(EMAC_PTP_ALARMLO
);
1004 D16(EMAC_PTP_ID_OFF
);
1005 D32(EMAC_PTP_ID_SNAP
);
1007 D16(EMAC_PTP_ISTAT
);
1008 D32(EMAC_PTP_OFFSET
);
1009 D32(EMAC_PTP_PPS_PERIOD
);
1010 D32(EMAC_PTP_PPS_STARTHI
);
1011 D32(EMAC_PTP_PPS_STARTLO
);
1012 D32(EMAC_PTP_RXSNAPHI
);
1013 D32(EMAC_PTP_RXSNAPLO
);
1014 D32(EMAC_PTP_TIMEHI
);
1015 D32(EMAC_PTP_TIMELO
);
1016 D32(EMAC_PTP_TXSNAPHI
);
1017 D32(EMAC_PTP_TXSNAPLO
);
1021 #if defined(EPPI0_STATUS) || defined(EPPI1_STATUS) || defined(EPPI2_STATUS)
1022 parent
= debugfs_create_dir("eppi", top
);
1023 # ifdef EPPI0_STATUS
1026 # ifdef EPPI1_STATUS
1029 # ifdef EPPI2_STATUS
1034 parent
= debugfs_create_dir("gptimer", top
);
1036 GPTIMER_GROUP(TIMER_ENABLE
, -1);
1038 #ifdef TIMER_ENABLE0
1039 GPTIMER_GROUP(TIMER_ENABLE0
, 0);
1041 #ifdef TIMER_ENABLE1
1042 GPTIMER_GROUP(TIMER_ENABLE1
, 1);
1044 /* XXX: Should convert BF561 MMR names */
1045 #ifdef TMRS4_DISABLE
1046 GPTIMER_GROUP(TMRS4_ENABLE
, 0);
1047 GPTIMER_GROUP(TMRS8_ENABLE
, 1);
1052 #ifdef TIMER3_CONFIG
1059 #ifdef TIMER8_CONFIG
1064 #ifdef TIMER11_CONFIG
1068 #ifdef HMDMA0_CONTROL
1069 parent
= debugfs_create_dir("hmdma", top
);
1075 parent
= debugfs_create_dir("hostdp", top
);
1081 #ifdef IMDMA_S0_CONFIG
1082 parent
= debugfs_create_dir("imdma", top
);
1088 parent
= debugfs_create_dir("keypad", top
);
1097 parent
= debugfs_create_dir("mdma", top
);
1100 #ifdef MDMA_D2_CONFIG
1106 parent
= debugfs_create_dir("mxvr", top
);
1108 # ifdef MXVR_PLL_CTL_0
1109 D32(MXVR_PLL_CTL_0
);
1113 D32(MXVR_INT_STAT_0
);
1114 D32(MXVR_INT_STAT_1
);
1118 D16(MXVR_MAX_POSITION
);
1120 D16(MXVR_MAX_DELAY
);
1139 D32(MXVR_SYNC_LCHAN_0
);
1140 D32(MXVR_SYNC_LCHAN_1
);
1141 D32(MXVR_SYNC_LCHAN_2
);
1142 D32(MXVR_SYNC_LCHAN_3
);
1143 D32(MXVR_SYNC_LCHAN_4
);
1144 D32(MXVR_SYNC_LCHAN_5
);
1145 D32(MXVR_SYNC_LCHAN_6
);
1146 D32(MXVR_SYNC_LCHAN_7
);
1147 D32(MXVR_DMA0_CONFIG
);
1148 D32(MXVR_DMA0_START_ADDR
);
1149 D16(MXVR_DMA0_COUNT
);
1150 D32(MXVR_DMA0_CURR_ADDR
);
1151 D16(MXVR_DMA0_CURR_COUNT
);
1152 D32(MXVR_DMA1_CONFIG
);
1153 D32(MXVR_DMA1_START_ADDR
);
1154 D16(MXVR_DMA1_COUNT
);
1155 D32(MXVR_DMA1_CURR_ADDR
);
1156 D16(MXVR_DMA1_CURR_COUNT
);
1157 D32(MXVR_DMA2_CONFIG
);
1158 D32(MXVR_DMA2_START_ADDR
);
1159 D16(MXVR_DMA2_COUNT
);
1160 D32(MXVR_DMA2_CURR_ADDR
);
1161 D16(MXVR_DMA2_CURR_COUNT
);
1162 D32(MXVR_DMA3_CONFIG
);
1163 D32(MXVR_DMA3_START_ADDR
);
1164 D16(MXVR_DMA3_COUNT
);
1165 D32(MXVR_DMA3_CURR_ADDR
);
1166 D16(MXVR_DMA3_CURR_COUNT
);
1167 D32(MXVR_DMA4_CONFIG
);
1168 D32(MXVR_DMA4_START_ADDR
);
1169 D16(MXVR_DMA4_COUNT
);
1170 D32(MXVR_DMA4_CURR_ADDR
);
1171 D16(MXVR_DMA4_CURR_COUNT
);
1172 D32(MXVR_DMA5_CONFIG
);
1173 D32(MXVR_DMA5_START_ADDR
);
1174 D16(MXVR_DMA5_COUNT
);
1175 D32(MXVR_DMA5_CURR_ADDR
);
1176 D16(MXVR_DMA5_CURR_COUNT
);
1177 D32(MXVR_DMA6_CONFIG
);
1178 D32(MXVR_DMA6_START_ADDR
);
1179 D16(MXVR_DMA6_COUNT
);
1180 D32(MXVR_DMA6_CURR_ADDR
);
1181 D16(MXVR_DMA6_CURR_COUNT
);
1182 D32(MXVR_DMA7_CONFIG
);
1183 D32(MXVR_DMA7_START_ADDR
);
1184 D16(MXVR_DMA7_COUNT
);
1185 D32(MXVR_DMA7_CURR_ADDR
);
1186 D16(MXVR_DMA7_CURR_COUNT
);
1188 D32(MXVR_APRB_START_ADDR
);
1189 D32(MXVR_APRB_CURR_ADDR
);
1190 D32(MXVR_APTB_START_ADDR
);
1191 D32(MXVR_APTB_CURR_ADDR
);
1193 D32(MXVR_CMRB_START_ADDR
);
1194 D32(MXVR_CMRB_CURR_ADDR
);
1195 D32(MXVR_CMTB_START_ADDR
);
1196 D32(MXVR_CMTB_CURR_ADDR
);
1197 D32(MXVR_RRDB_START_ADDR
);
1198 D32(MXVR_RRDB_CURR_ADDR
);
1199 D32(MXVR_PAT_DATA_0
);
1201 D32(MXVR_PAT_DATA_1
);
1203 D16(MXVR_FRAME_CNT_0
);
1204 D16(MXVR_FRAME_CNT_1
);
1205 D32(MXVR_ROUTING_0
);
1206 D32(MXVR_ROUTING_1
);
1207 D32(MXVR_ROUTING_2
);
1208 D32(MXVR_ROUTING_3
);
1209 D32(MXVR_ROUTING_4
);
1210 D32(MXVR_ROUTING_5
);
1211 D32(MXVR_ROUTING_6
);
1212 D32(MXVR_ROUTING_7
);
1213 D32(MXVR_ROUTING_8
);
1214 D32(MXVR_ROUTING_9
);
1215 D32(MXVR_ROUTING_10
);
1216 D32(MXVR_ROUTING_11
);
1217 D32(MXVR_ROUTING_12
);
1218 D32(MXVR_ROUTING_13
);
1219 D32(MXVR_ROUTING_14
);
1220 # ifdef MXVR_PLL_CTL_1
1221 D32(MXVR_PLL_CTL_1
);
1223 D16(MXVR_BLOCK_CNT
);
1224 # ifdef MXVR_CLK_CTL
1227 # ifdef MXVR_CDRPLL_CTL
1228 D32(MXVR_CDRPLL_CTL
);
1230 # ifdef MXVR_FMPLL_CTL
1231 D32(MXVR_FMPLL_CTL
);
1233 # ifdef MXVR_PIN_CTL
1236 # ifdef MXVR_SCLK_CNT
1242 parent
= debugfs_create_dir("nfc", top
);
1245 D_RO(NFC_COUNT
, 16);
1247 D_WO(NFC_DATA_RD
, 16);
1248 D_WO(NFC_DATA_WR
, 16);
1255 D_WO(NFC_PGCTL
, 16);
1262 parent
= debugfs_create_dir("otp", top
);
1274 parent
= debugfs_create_dir("pixc", top
);
1296 parent
= debugfs_create_dir("pll", top
);
1302 D32(CHIPID
); /* it's part of this hardware block */
1304 #if defined(PPI_CONTROL) || defined(PPI0_CONTROL) || defined(PPI1_CONTROL)
1305 parent
= debugfs_create_dir("ppi", top
);
1307 bfin_debug_mmrs_ppi(parent
, PPI_CONTROL
, -1);
1309 # ifdef PPI0_CONTROL
1312 # ifdef PPI1_CONTROL
1318 parent
= debugfs_create_dir("pwm", top
);
1337 parent
= debugfs_create_dir("rsi", top
);
1339 D16(RSI_CEATA_CONTROL
);
1340 D16(RSI_CLK_CONTROL
);
1344 D16(RSI_DATA_CONTROL
);
1346 D32(RSI_DATA_TIMER
);
1361 D16(RSI_PWR_CONTROL
);
1362 D16(RSI_RD_WAIT_EN
);
1369 D_WO(RSI_STATUSCL
, 16);
1373 parent
= debugfs_create_dir("rtc", top
);
1383 parent
= debugfs_create_dir("sdh", top
);
1388 D_RO(SDH_DATA_CNT
, 16);
1391 D32(SDH_DATA_TIMER
);
1395 D_RO(SDH_FIFO_CNT
, 16);
1407 D16(SDH_RD_WAIT_EN
);
1408 D_RO(SDH_RESPONSE0
, 32);
1409 D_RO(SDH_RESPONSE1
, 32);
1410 D_RO(SDH_RESPONSE2
, 32);
1411 D_RO(SDH_RESPONSE3
, 32);
1412 D_RO(SDH_RESP_CMD
, 16);
1413 D_RO(SDH_STATUS
, 32);
1414 D_WO(SDH_STATUS_CLR
, 16);
1417 #ifdef SECURE_CONTROL
1418 parent
= debugfs_create_dir("security", top
);
1419 D16(SECURE_CONTROL
);
1424 parent
= debugfs_create_dir("sic", top
);
1486 parent
= debugfs_create_dir("spi", top
);
1497 parent
= debugfs_create_dir("sport", top
);
1511 #if defined(TWI_CLKDIV) || defined(TWI0_CLKDIV) || defined(TWI1_CLKDIV)
1512 parent
= debugfs_create_dir("twi", top
);
1514 bfin_debug_mmrs_twi(parent
, TWI_CLKDIV
, -1);
1524 parent
= debugfs_create_dir("uart", top
);
1525 #ifdef BFIN_UART_DLL
1526 bfin_debug_mmrs_uart(parent
, BFIN_UART_DLL
, -1);
1542 parent
= debugfs_create_dir("usb", top
);
1555 D16(USB_GLOBAL_CTL
);
1556 D16(USB_TX_MAX_PACKET
);
1559 D16(USB_RX_MAX_PACKET
);
1565 D16(USB_TXINTERVAL
);
1567 D16(USB_RXINTERVAL
);
1577 D16(USB_OTG_DEV_CTL
);
1578 D16(USB_OTG_VBUS_IRQ
);
1579 D16(USB_OTG_VBUS_MASK
);
1585 D16(USB_APHY_CNTRL
);
1586 D16(USB_APHY_CALIB
);
1587 D16(USB_APHY_CNTRL2
);
1589 D16(USB_PLLOSC_CTRL
);
1590 D16(USB_SRP_CLKDIV
);
1591 D16(USB_EP_NI0_TXMAXP
);
1592 D16(USB_EP_NI0_TXCSR
);
1593 D16(USB_EP_NI0_RXMAXP
);
1594 D16(USB_EP_NI0_RXCSR
);
1595 D16(USB_EP_NI0_RXCOUNT
);
1596 D16(USB_EP_NI0_TXTYPE
);
1597 D16(USB_EP_NI0_TXINTERVAL
);
1598 D16(USB_EP_NI0_RXTYPE
);
1599 D16(USB_EP_NI0_RXINTERVAL
);
1600 D16(USB_EP_NI0_TXCOUNT
);
1601 D16(USB_EP_NI1_TXMAXP
);
1602 D16(USB_EP_NI1_TXCSR
);
1603 D16(USB_EP_NI1_RXMAXP
);
1604 D16(USB_EP_NI1_RXCSR
);
1605 D16(USB_EP_NI1_RXCOUNT
);
1606 D16(USB_EP_NI1_TXTYPE
);
1607 D16(USB_EP_NI1_TXINTERVAL
);
1608 D16(USB_EP_NI1_RXTYPE
);
1609 D16(USB_EP_NI1_RXINTERVAL
);
1610 D16(USB_EP_NI1_TXCOUNT
);
1611 D16(USB_EP_NI2_TXMAXP
);
1612 D16(USB_EP_NI2_TXCSR
);
1613 D16(USB_EP_NI2_RXMAXP
);
1614 D16(USB_EP_NI2_RXCSR
);
1615 D16(USB_EP_NI2_RXCOUNT
);
1616 D16(USB_EP_NI2_TXTYPE
);
1617 D16(USB_EP_NI2_TXINTERVAL
);
1618 D16(USB_EP_NI2_RXTYPE
);
1619 D16(USB_EP_NI2_RXINTERVAL
);
1620 D16(USB_EP_NI2_TXCOUNT
);
1621 D16(USB_EP_NI3_TXMAXP
);
1622 D16(USB_EP_NI3_TXCSR
);
1623 D16(USB_EP_NI3_RXMAXP
);
1624 D16(USB_EP_NI3_RXCSR
);
1625 D16(USB_EP_NI3_RXCOUNT
);
1626 D16(USB_EP_NI3_TXTYPE
);
1627 D16(USB_EP_NI3_TXINTERVAL
);
1628 D16(USB_EP_NI3_RXTYPE
);
1629 D16(USB_EP_NI3_RXINTERVAL
);
1630 D16(USB_EP_NI3_TXCOUNT
);
1631 D16(USB_EP_NI4_TXMAXP
);
1632 D16(USB_EP_NI4_TXCSR
);
1633 D16(USB_EP_NI4_RXMAXP
);
1634 D16(USB_EP_NI4_RXCSR
);
1635 D16(USB_EP_NI4_RXCOUNT
);
1636 D16(USB_EP_NI4_TXTYPE
);
1637 D16(USB_EP_NI4_TXINTERVAL
);
1638 D16(USB_EP_NI4_RXTYPE
);
1639 D16(USB_EP_NI4_RXINTERVAL
);
1640 D16(USB_EP_NI4_TXCOUNT
);
1641 D16(USB_EP_NI5_TXMAXP
);
1642 D16(USB_EP_NI5_TXCSR
);
1643 D16(USB_EP_NI5_RXMAXP
);
1644 D16(USB_EP_NI5_RXCSR
);
1645 D16(USB_EP_NI5_RXCOUNT
);
1646 D16(USB_EP_NI5_TXTYPE
);
1647 D16(USB_EP_NI5_TXINTERVAL
);
1648 D16(USB_EP_NI5_RXTYPE
);
1649 D16(USB_EP_NI5_RXINTERVAL
);
1650 D16(USB_EP_NI5_TXCOUNT
);
1651 D16(USB_EP_NI6_TXMAXP
);
1652 D16(USB_EP_NI6_TXCSR
);
1653 D16(USB_EP_NI6_RXMAXP
);
1654 D16(USB_EP_NI6_RXCSR
);
1655 D16(USB_EP_NI6_RXCOUNT
);
1656 D16(USB_EP_NI6_TXTYPE
);
1657 D16(USB_EP_NI6_TXINTERVAL
);
1658 D16(USB_EP_NI6_RXTYPE
);
1659 D16(USB_EP_NI6_RXINTERVAL
);
1660 D16(USB_EP_NI6_TXCOUNT
);
1661 D16(USB_EP_NI7_TXMAXP
);
1662 D16(USB_EP_NI7_TXCSR
);
1663 D16(USB_EP_NI7_RXMAXP
);
1664 D16(USB_EP_NI7_RXCSR
);
1665 D16(USB_EP_NI7_RXCOUNT
);
1666 D16(USB_EP_NI7_TXTYPE
);
1667 D16(USB_EP_NI7_TXINTERVAL
);
1668 D16(USB_EP_NI7_RXTYPE
);
1669 D16(USB_EP_NI7_RXINTERVAL
);
1670 D16(USB_EP_NI7_TXCOUNT
);
1671 D16(USB_DMA_INTERRUPT
);
1672 D16(USB_DMA0CONTROL
);
1673 D16(USB_DMA0ADDRLOW
);
1674 D16(USB_DMA0ADDRHIGH
);
1675 D16(USB_DMA0COUNTLOW
);
1676 D16(USB_DMA0COUNTHIGH
);
1677 D16(USB_DMA1CONTROL
);
1678 D16(USB_DMA1ADDRLOW
);
1679 D16(USB_DMA1ADDRHIGH
);
1680 D16(USB_DMA1COUNTLOW
);
1681 D16(USB_DMA1COUNTHIGH
);
1682 D16(USB_DMA2CONTROL
);
1683 D16(USB_DMA2ADDRLOW
);
1684 D16(USB_DMA2ADDRHIGH
);
1685 D16(USB_DMA2COUNTLOW
);
1686 D16(USB_DMA2COUNTHIGH
);
1687 D16(USB_DMA3CONTROL
);
1688 D16(USB_DMA3ADDRLOW
);
1689 D16(USB_DMA3ADDRHIGH
);
1690 D16(USB_DMA3COUNTLOW
);
1691 D16(USB_DMA3COUNTHIGH
);
1692 D16(USB_DMA4CONTROL
);
1693 D16(USB_DMA4ADDRLOW
);
1694 D16(USB_DMA4ADDRHIGH
);
1695 D16(USB_DMA4COUNTLOW
);
1696 D16(USB_DMA4COUNTHIGH
);
1697 D16(USB_DMA5CONTROL
);
1698 D16(USB_DMA5ADDRLOW
);
1699 D16(USB_DMA5ADDRHIGH
);
1700 D16(USB_DMA5COUNTLOW
);
1701 D16(USB_DMA5COUNTHIGH
);
1702 D16(USB_DMA6CONTROL
);
1703 D16(USB_DMA6ADDRLOW
);
1704 D16(USB_DMA6ADDRHIGH
);
1705 D16(USB_DMA6COUNTLOW
);
1706 D16(USB_DMA6COUNTHIGH
);
1707 D16(USB_DMA7CONTROL
);
1708 D16(USB_DMA7ADDRLOW
);
1709 D16(USB_DMA7ADDRHIGH
);
1710 D16(USB_DMA7COUNTLOW
);
1711 D16(USB_DMA7COUNTHIGH
);
1715 parent
= debugfs_create_dir("watchdog", top
);
1721 parent
= debugfs_create_dir("watchdog", top
);
1732 #define PORTFIO FIO_FLAG_D
1736 #define PORTFIO FIO0_FLAG_D
1739 #define PORTGIO FIO1_FLAG_D
1742 #define PORTHIO FIO2_FLAG_D
1744 parent
= debugfs_create_dir("port", top
);
1755 #ifdef __ADSPBF51x__
1758 D16(PORTF_HYSTERESIS
);
1763 D16(PORTG_HYSTERESIS
);
1768 D16(PORTH_HYSTERESIS
);
1771 D16(MISCPORT_DRIVE
);
1772 D16(MISCPORT_HYSTERESIS
);
1775 #ifdef __ADSPBF52x__
1778 D16(PORTF_HYSTERESIS
);
1784 D16(PORTG_HYSTERESIS
);
1790 D16(PORTH_HYSTERESIS
);
1794 D16(MISCPORT_DRIVE
);
1795 D16(MISCPORT_HYSTERESIS
);
1804 #endif /* BF534 BF536 BF537 */
1811 D16(PORTCIO_TOGGLE
);
1821 D16(PORTDIO_TOGGLE
);
1829 D16(PORTEIO_TOGGLE
);
1830 #endif /* BF538 BF539 */
1832 #ifdef __ADSPBF54x__
1836 char *_buf
, buf
[32];
1839 for (num
= 0; num
< 10; ++num
) {
1841 base
+= sizeof(struct bfin_gpio_regs
);
1844 #define __PINT(uname, lname) __REGS(pint, #uname, lname)
1845 parent
= debugfs_create_dir("pint", top
);
1846 base
= PINT0_MASK_SET
;
1847 for (num
= 0; num
< 4; ++num
) {
1848 _buf
= REGS_STR_PFX(buf
, PINT
, num
);
1849 __PINT(MASK_SET
, mask_set
);
1850 __PINT(MASK_CLEAR
, mask_clear
);
1851 __PINT(REQUEST
, request
);
1852 __PINT(ASSIGN
, assign
);
1853 __PINT(EDGE_SET
, edge_set
);
1854 __PINT(EDGE_CLEAR
, edge_clear
);
1855 __PINT(INVERT_SET
, invert_set
);
1856 __PINT(INVERT_CLEAR
, invert_clear
);
1857 __PINT(PINSTATE
, pinstate
);
1858 __PINT(LATCH
, latch
);
1859 base
+= sizeof(struct bfin_pint_regs
);
1865 debug_mmrs_dentry
= top
;
1869 module_init(bfin_debug_mmrs_init
);
1871 static void __exit
bfin_debug_mmrs_exit(void)
1873 debugfs_remove_recursive(debug_mmrs_dentry
);
1875 module_exit(bfin_debug_mmrs_exit
);
1877 MODULE_LICENSE("GPL");
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