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Merge branch 'for_linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jack/linux...
[deliverable/linux.git] / arch / blackfin / kernel / setup.c
1 /*
2 * arch/blackfin/kernel/setup.c
3 *
4 * Copyright 2004-2006 Analog Devices Inc.
5 *
6 * Enter bugs at http://blackfin.uclinux.org/
7 *
8 * Licensed under the GPL-2 or later.
9 */
10
11 #include <linux/delay.h>
12 #include <linux/console.h>
13 #include <linux/bootmem.h>
14 #include <linux/seq_file.h>
15 #include <linux/cpu.h>
16 #include <linux/mm.h>
17 #include <linux/module.h>
18 #include <linux/tty.h>
19 #include <linux/pfn.h>
20
21 #ifdef CONFIG_MTD_UCLINUX
22 #include <linux/mtd/map.h>
23 #include <linux/ext2_fs.h>
24 #include <linux/cramfs_fs.h>
25 #include <linux/romfs_fs.h>
26 #endif
27
28 #include <asm/cplb.h>
29 #include <asm/cacheflush.h>
30 #include <asm/blackfin.h>
31 #include <asm/cplbinit.h>
32 #include <asm/div64.h>
33 #include <asm/cpu.h>
34 #include <asm/fixed_code.h>
35 #include <asm/early_printk.h>
36
37 u16 _bfin_swrst;
38 EXPORT_SYMBOL(_bfin_swrst);
39
40 unsigned long memory_start, memory_end, physical_mem_end;
41 unsigned long _rambase, _ramstart, _ramend;
42 unsigned long reserved_mem_dcache_on;
43 unsigned long reserved_mem_icache_on;
44 EXPORT_SYMBOL(memory_start);
45 EXPORT_SYMBOL(memory_end);
46 EXPORT_SYMBOL(physical_mem_end);
47 EXPORT_SYMBOL(_ramend);
48 EXPORT_SYMBOL(reserved_mem_dcache_on);
49
50 #ifdef CONFIG_MTD_UCLINUX
51 extern struct map_info uclinux_ram_map;
52 unsigned long memory_mtd_end, memory_mtd_start, mtd_size;
53 unsigned long _ebss;
54 EXPORT_SYMBOL(memory_mtd_end);
55 EXPORT_SYMBOL(memory_mtd_start);
56 EXPORT_SYMBOL(mtd_size);
57 #endif
58
59 char __initdata command_line[COMMAND_LINE_SIZE];
60 void __initdata *init_retx, *init_saved_retx, *init_saved_seqstat,
61 *init_saved_icplb_fault_addr, *init_saved_dcplb_fault_addr;
62
63 /* boot memmap, for parsing "memmap=" */
64 #define BFIN_MEMMAP_MAX 128 /* number of entries in bfin_memmap */
65 #define BFIN_MEMMAP_RAM 1
66 #define BFIN_MEMMAP_RESERVED 2
67 static struct bfin_memmap {
68 int nr_map;
69 struct bfin_memmap_entry {
70 unsigned long long addr; /* start of memory segment */
71 unsigned long long size;
72 unsigned long type;
73 } map[BFIN_MEMMAP_MAX];
74 } bfin_memmap __initdata;
75
76 /* for memmap sanitization */
77 struct change_member {
78 struct bfin_memmap_entry *pentry; /* pointer to original entry */
79 unsigned long long addr; /* address for this change point */
80 };
81 static struct change_member change_point_list[2*BFIN_MEMMAP_MAX] __initdata;
82 static struct change_member *change_point[2*BFIN_MEMMAP_MAX] __initdata;
83 static struct bfin_memmap_entry *overlap_list[BFIN_MEMMAP_MAX] __initdata;
84 static struct bfin_memmap_entry new_map[BFIN_MEMMAP_MAX] __initdata;
85
86 DEFINE_PER_CPU(struct blackfin_cpudata, cpu_data);
87
88 static int early_init_clkin_hz(char *buf);
89
90 #if defined(CONFIG_BFIN_DCACHE) || defined(CONFIG_BFIN_ICACHE)
91 void __init generate_cplb_tables(void)
92 {
93 unsigned int cpu;
94
95 generate_cplb_tables_all();
96 /* Generate per-CPU I&D CPLB tables */
97 for (cpu = 0; cpu < num_possible_cpus(); ++cpu)
98 generate_cplb_tables_cpu(cpu);
99 }
100 #endif
101
102 void __cpuinit bfin_setup_caches(unsigned int cpu)
103 {
104 #ifdef CONFIG_BFIN_ICACHE
105 bfin_icache_init(icplb_tbl[cpu]);
106 #endif
107
108 #ifdef CONFIG_BFIN_DCACHE
109 bfin_dcache_init(dcplb_tbl[cpu]);
110 #endif
111
112 /*
113 * In cache coherence emulation mode, we need to have the
114 * D-cache enabled before running any atomic operation which
115 * might involve cache invalidation (i.e. spinlock, rwlock).
116 * So printk's are deferred until then.
117 */
118 #ifdef CONFIG_BFIN_ICACHE
119 printk(KERN_INFO "Instruction Cache Enabled for CPU%u\n", cpu);
120 printk(KERN_INFO " External memory:"
121 # ifdef CONFIG_BFIN_EXTMEM_ICACHEABLE
122 " cacheable"
123 # else
124 " uncacheable"
125 # endif
126 " in instruction cache\n");
127 if (L2_LENGTH)
128 printk(KERN_INFO " L2 SRAM :"
129 # ifdef CONFIG_BFIN_L2_ICACHEABLE
130 " cacheable"
131 # else
132 " uncacheable"
133 # endif
134 " in instruction cache\n");
135
136 #else
137 printk(KERN_INFO "Instruction Cache Disabled for CPU%u\n", cpu);
138 #endif
139
140 #ifdef CONFIG_BFIN_DCACHE
141 printk(KERN_INFO "Data Cache Enabled for CPU%u\n", cpu);
142 printk(KERN_INFO " External memory:"
143 # if defined CONFIG_BFIN_EXTMEM_WRITEBACK
144 " cacheable (write-back)"
145 # elif defined CONFIG_BFIN_EXTMEM_WRITETHROUGH
146 " cacheable (write-through)"
147 # else
148 " uncacheable"
149 # endif
150 " in data cache\n");
151 if (L2_LENGTH)
152 printk(KERN_INFO " L2 SRAM :"
153 # if defined CONFIG_BFIN_L2_WRITEBACK
154 " cacheable (write-back)"
155 # elif defined CONFIG_BFIN_L2_WRITETHROUGH
156 " cacheable (write-through)"
157 # else
158 " uncacheable"
159 # endif
160 " in data cache\n");
161 #else
162 printk(KERN_INFO "Data Cache Disabled for CPU%u\n", cpu);
163 #endif
164 }
165
166 void __cpuinit bfin_setup_cpudata(unsigned int cpu)
167 {
168 struct blackfin_cpudata *cpudata = &per_cpu(cpu_data, cpu);
169
170 cpudata->idle = current;
171 cpudata->imemctl = bfin_read_IMEM_CONTROL();
172 cpudata->dmemctl = bfin_read_DMEM_CONTROL();
173 }
174
175 void __init bfin_cache_init(void)
176 {
177 #if defined(CONFIG_BFIN_DCACHE) || defined(CONFIG_BFIN_ICACHE)
178 generate_cplb_tables();
179 #endif
180 bfin_setup_caches(0);
181 }
182
183 void __init bfin_relocate_l1_mem(void)
184 {
185 unsigned long l1_code_length;
186 unsigned long l1_data_a_length;
187 unsigned long l1_data_b_length;
188 unsigned long l2_length;
189
190 early_shadow_stamp();
191
192 /*
193 * due to the ALIGN(4) in the arch/blackfin/kernel/vmlinux.lds.S
194 * we know that everything about l1 text/data is nice and aligned,
195 * so copy by 4 byte chunks, and don't worry about overlapping
196 * src/dest.
197 *
198 * We can't use the dma_memcpy functions, since they can call
199 * scheduler functions which might be in L1 :( and core writes
200 * into L1 instruction cause bad access errors, so we are stuck,
201 * we are required to use DMA, but can't use the common dma
202 * functions. We can't use memcpy either - since that might be
203 * going to be in the relocated L1
204 */
205
206 blackfin_dma_early_init();
207
208 /* if necessary, copy _stext_l1 to _etext_l1 to L1 instruction SRAM */
209 l1_code_length = _etext_l1 - _stext_l1;
210 if (l1_code_length)
211 early_dma_memcpy(_stext_l1, _l1_lma_start, l1_code_length);
212
213 /* if necessary, copy _sdata_l1 to _sbss_l1 to L1 data bank A SRAM */
214 l1_data_a_length = _sbss_l1 - _sdata_l1;
215 if (l1_data_a_length)
216 early_dma_memcpy(_sdata_l1, _l1_lma_start + l1_code_length, l1_data_a_length);
217
218 /* if necessary, copy _sdata_b_l1 to _sbss_b_l1 to L1 data bank B SRAM */
219 l1_data_b_length = _sbss_b_l1 - _sdata_b_l1;
220 if (l1_data_b_length)
221 early_dma_memcpy(_sdata_b_l1, _l1_lma_start + l1_code_length +
222 l1_data_a_length, l1_data_b_length);
223
224 early_dma_memcpy_done();
225
226 /* if necessary, copy _stext_l2 to _edata_l2 to L2 SRAM */
227 if (L2_LENGTH != 0) {
228 l2_length = _sbss_l2 - _stext_l2;
229 if (l2_length)
230 memcpy(_stext_l2, _l2_lma_start, l2_length);
231 }
232 }
233
234 /* add_memory_region to memmap */
235 static void __init add_memory_region(unsigned long long start,
236 unsigned long long size, int type)
237 {
238 int i;
239
240 i = bfin_memmap.nr_map;
241
242 if (i == BFIN_MEMMAP_MAX) {
243 printk(KERN_ERR "Ooops! Too many entries in the memory map!\n");
244 return;
245 }
246
247 bfin_memmap.map[i].addr = start;
248 bfin_memmap.map[i].size = size;
249 bfin_memmap.map[i].type = type;
250 bfin_memmap.nr_map++;
251 }
252
253 /*
254 * Sanitize the boot memmap, removing overlaps.
255 */
256 static int __init sanitize_memmap(struct bfin_memmap_entry *map, int *pnr_map)
257 {
258 struct change_member *change_tmp;
259 unsigned long current_type, last_type;
260 unsigned long long last_addr;
261 int chgidx, still_changing;
262 int overlap_entries;
263 int new_entry;
264 int old_nr, new_nr, chg_nr;
265 int i;
266
267 /*
268 Visually we're performing the following (1,2,3,4 = memory types)
269
270 Sample memory map (w/overlaps):
271 ____22__________________
272 ______________________4_
273 ____1111________________
274 _44_____________________
275 11111111________________
276 ____________________33__
277 ___________44___________
278 __________33333_________
279 ______________22________
280 ___________________2222_
281 _________111111111______
282 _____________________11_
283 _________________4______
284
285 Sanitized equivalent (no overlap):
286 1_______________________
287 _44_____________________
288 ___1____________________
289 ____22__________________
290 ______11________________
291 _________1______________
292 __________3_____________
293 ___________44___________
294 _____________33_________
295 _______________2________
296 ________________1_______
297 _________________4______
298 ___________________2____
299 ____________________33__
300 ______________________4_
301 */
302 /* if there's only one memory region, don't bother */
303 if (*pnr_map < 2)
304 return -1;
305
306 old_nr = *pnr_map;
307
308 /* bail out if we find any unreasonable addresses in memmap */
309 for (i = 0; i < old_nr; i++)
310 if (map[i].addr + map[i].size < map[i].addr)
311 return -1;
312
313 /* create pointers for initial change-point information (for sorting) */
314 for (i = 0; i < 2*old_nr; i++)
315 change_point[i] = &change_point_list[i];
316
317 /* record all known change-points (starting and ending addresses),
318 omitting those that are for empty memory regions */
319 chgidx = 0;
320 for (i = 0; i < old_nr; i++) {
321 if (map[i].size != 0) {
322 change_point[chgidx]->addr = map[i].addr;
323 change_point[chgidx++]->pentry = &map[i];
324 change_point[chgidx]->addr = map[i].addr + map[i].size;
325 change_point[chgidx++]->pentry = &map[i];
326 }
327 }
328 chg_nr = chgidx; /* true number of change-points */
329
330 /* sort change-point list by memory addresses (low -> high) */
331 still_changing = 1;
332 while (still_changing) {
333 still_changing = 0;
334 for (i = 1; i < chg_nr; i++) {
335 /* if <current_addr> > <last_addr>, swap */
336 /* or, if current=<start_addr> & last=<end_addr>, swap */
337 if ((change_point[i]->addr < change_point[i-1]->addr) ||
338 ((change_point[i]->addr == change_point[i-1]->addr) &&
339 (change_point[i]->addr == change_point[i]->pentry->addr) &&
340 (change_point[i-1]->addr != change_point[i-1]->pentry->addr))
341 ) {
342 change_tmp = change_point[i];
343 change_point[i] = change_point[i-1];
344 change_point[i-1] = change_tmp;
345 still_changing = 1;
346 }
347 }
348 }
349
350 /* create a new memmap, removing overlaps */
351 overlap_entries = 0; /* number of entries in the overlap table */
352 new_entry = 0; /* index for creating new memmap entries */
353 last_type = 0; /* start with undefined memory type */
354 last_addr = 0; /* start with 0 as last starting address */
355 /* loop through change-points, determining affect on the new memmap */
356 for (chgidx = 0; chgidx < chg_nr; chgidx++) {
357 /* keep track of all overlapping memmap entries */
358 if (change_point[chgidx]->addr == change_point[chgidx]->pentry->addr) {
359 /* add map entry to overlap list (> 1 entry implies an overlap) */
360 overlap_list[overlap_entries++] = change_point[chgidx]->pentry;
361 } else {
362 /* remove entry from list (order independent, so swap with last) */
363 for (i = 0; i < overlap_entries; i++) {
364 if (overlap_list[i] == change_point[chgidx]->pentry)
365 overlap_list[i] = overlap_list[overlap_entries-1];
366 }
367 overlap_entries--;
368 }
369 /* if there are overlapping entries, decide which "type" to use */
370 /* (larger value takes precedence -- 1=usable, 2,3,4,4+=unusable) */
371 current_type = 0;
372 for (i = 0; i < overlap_entries; i++)
373 if (overlap_list[i]->type > current_type)
374 current_type = overlap_list[i]->type;
375 /* continue building up new memmap based on this information */
376 if (current_type != last_type) {
377 if (last_type != 0) {
378 new_map[new_entry].size =
379 change_point[chgidx]->addr - last_addr;
380 /* move forward only if the new size was non-zero */
381 if (new_map[new_entry].size != 0)
382 if (++new_entry >= BFIN_MEMMAP_MAX)
383 break; /* no more space left for new entries */
384 }
385 if (current_type != 0) {
386 new_map[new_entry].addr = change_point[chgidx]->addr;
387 new_map[new_entry].type = current_type;
388 last_addr = change_point[chgidx]->addr;
389 }
390 last_type = current_type;
391 }
392 }
393 new_nr = new_entry; /* retain count for new entries */
394
395 /* copy new mapping into original location */
396 memcpy(map, new_map, new_nr*sizeof(struct bfin_memmap_entry));
397 *pnr_map = new_nr;
398
399 return 0;
400 }
401
402 static void __init print_memory_map(char *who)
403 {
404 int i;
405
406 for (i = 0; i < bfin_memmap.nr_map; i++) {
407 printk(KERN_DEBUG " %s: %016Lx - %016Lx ", who,
408 bfin_memmap.map[i].addr,
409 bfin_memmap.map[i].addr + bfin_memmap.map[i].size);
410 switch (bfin_memmap.map[i].type) {
411 case BFIN_MEMMAP_RAM:
412 printk(KERN_CONT "(usable)\n");
413 break;
414 case BFIN_MEMMAP_RESERVED:
415 printk(KERN_CONT "(reserved)\n");
416 break;
417 default:
418 printk(KERN_CONT "type %lu\n", bfin_memmap.map[i].type);
419 break;
420 }
421 }
422 }
423
424 static __init int parse_memmap(char *arg)
425 {
426 unsigned long long start_at, mem_size;
427
428 if (!arg)
429 return -EINVAL;
430
431 mem_size = memparse(arg, &arg);
432 if (*arg == '@') {
433 start_at = memparse(arg+1, &arg);
434 add_memory_region(start_at, mem_size, BFIN_MEMMAP_RAM);
435 } else if (*arg == '$') {
436 start_at = memparse(arg+1, &arg);
437 add_memory_region(start_at, mem_size, BFIN_MEMMAP_RESERVED);
438 }
439
440 return 0;
441 }
442
443 /*
444 * Initial parsing of the command line. Currently, we support:
445 * - Controlling the linux memory size: mem=xxx[KMG]
446 * - Controlling the physical memory size: max_mem=xxx[KMG][$][#]
447 * $ -> reserved memory is dcacheable
448 * # -> reserved memory is icacheable
449 * - "memmap=XXX[KkmM][@][$]XXX[KkmM]" defines a memory region
450 * @ from <start> to <start>+<mem>, type RAM
451 * $ from <start> to <start>+<mem>, type RESERVED
452 */
453 static __init void parse_cmdline_early(char *cmdline_p)
454 {
455 char c = ' ', *to = cmdline_p;
456 unsigned int memsize;
457 for (;;) {
458 if (c == ' ') {
459 if (!memcmp(to, "mem=", 4)) {
460 to += 4;
461 memsize = memparse(to, &to);
462 if (memsize)
463 _ramend = memsize;
464
465 } else if (!memcmp(to, "max_mem=", 8)) {
466 to += 8;
467 memsize = memparse(to, &to);
468 if (memsize) {
469 physical_mem_end = memsize;
470 if (*to != ' ') {
471 if (*to == '$'
472 || *(to + 1) == '$')
473 reserved_mem_dcache_on = 1;
474 if (*to == '#'
475 || *(to + 1) == '#')
476 reserved_mem_icache_on = 1;
477 }
478 }
479 } else if (!memcmp(to, "clkin_hz=", 9)) {
480 to += 9;
481 early_init_clkin_hz(to);
482 #ifdef CONFIG_EARLY_PRINTK
483 } else if (!memcmp(to, "earlyprintk=", 12)) {
484 to += 12;
485 setup_early_printk(to);
486 #endif
487 } else if (!memcmp(to, "memmap=", 7)) {
488 to += 7;
489 parse_memmap(to);
490 }
491 }
492 c = *(to++);
493 if (!c)
494 break;
495 }
496 }
497
498 /*
499 * Setup memory defaults from user config.
500 * The physical memory layout looks like:
501 *
502 * [_rambase, _ramstart]: kernel image
503 * [memory_start, memory_end]: dynamic memory managed by kernel
504 * [memory_end, _ramend]: reserved memory
505 * [memory_mtd_start(memory_end),
506 * memory_mtd_start + mtd_size]: rootfs (if any)
507 * [_ramend - DMA_UNCACHED_REGION,
508 * _ramend]: uncached DMA region
509 * [_ramend, physical_mem_end]: memory not managed by kernel
510 */
511 static __init void memory_setup(void)
512 {
513 #ifdef CONFIG_MTD_UCLINUX
514 unsigned long mtd_phys = 0;
515 #endif
516 unsigned long max_mem;
517
518 _rambase = (unsigned long)_stext;
519 _ramstart = (unsigned long)_end;
520
521 if (DMA_UNCACHED_REGION > (_ramend - _ramstart)) {
522 console_init();
523 panic("DMA region exceeds memory limit: %lu.",
524 _ramend - _ramstart);
525 }
526 max_mem = memory_end = _ramend - DMA_UNCACHED_REGION;
527
528 #if (defined(CONFIG_BFIN_EXTMEM_ICACHEABLE) && ANOMALY_05000263)
529 /* Due to a Hardware Anomaly we need to limit the size of usable
530 * instruction memory to max 60MB, 56 if HUNT_FOR_ZERO is on
531 * 05000263 - Hardware loop corrupted when taking an ICPLB exception
532 */
533 # if (defined(CONFIG_DEBUG_HUNT_FOR_ZERO))
534 if (max_mem >= 56 * 1024 * 1024)
535 max_mem = 56 * 1024 * 1024;
536 # else
537 if (max_mem >= 60 * 1024 * 1024)
538 max_mem = 60 * 1024 * 1024;
539 # endif /* CONFIG_DEBUG_HUNT_FOR_ZERO */
540 #endif /* ANOMALY_05000263 */
541
542
543 #ifdef CONFIG_MPU
544 /* Round up to multiple of 4MB */
545 memory_start = (_ramstart + 0x3fffff) & ~0x3fffff;
546 #else
547 memory_start = PAGE_ALIGN(_ramstart);
548 #endif
549
550 #if defined(CONFIG_MTD_UCLINUX)
551 /* generic memory mapped MTD driver */
552 memory_mtd_end = memory_end;
553
554 mtd_phys = _ramstart;
555 mtd_size = PAGE_ALIGN(*((unsigned long *)(mtd_phys + 8)));
556
557 # if defined(CONFIG_EXT2_FS) || defined(CONFIG_EXT3_FS)
558 if (*((unsigned short *)(mtd_phys + 0x438)) == EXT2_SUPER_MAGIC)
559 mtd_size =
560 PAGE_ALIGN(*((unsigned long *)(mtd_phys + 0x404)) << 10);
561 # endif
562
563 # if defined(CONFIG_CRAMFS)
564 if (*((unsigned long *)(mtd_phys)) == CRAMFS_MAGIC)
565 mtd_size = PAGE_ALIGN(*((unsigned long *)(mtd_phys + 0x4)));
566 # endif
567
568 # if defined(CONFIG_ROMFS_FS)
569 if (((unsigned long *)mtd_phys)[0] == ROMSB_WORD0
570 && ((unsigned long *)mtd_phys)[1] == ROMSB_WORD1) {
571 mtd_size =
572 PAGE_ALIGN(be32_to_cpu(((unsigned long *)mtd_phys)[2]));
573
574 /* ROM_FS is XIP, so if we found it, we need to limit memory */
575 if (memory_end > max_mem) {
576 pr_info("Limiting kernel memory to %liMB due to anomaly 05000263\n", max_mem >> 20);
577 memory_end = max_mem;
578 }
579 }
580 # endif /* CONFIG_ROMFS_FS */
581
582 /* Since the default MTD_UCLINUX has no magic number, we just blindly
583 * read 8 past the end of the kernel's image, and look at it.
584 * When no image is attached, mtd_size is set to a random number
585 * Do some basic sanity checks before operating on things
586 */
587 if (mtd_size == 0 || memory_end <= mtd_size) {
588 pr_emerg("Could not find valid ram mtd attached.\n");
589 } else {
590 memory_end -= mtd_size;
591
592 /* Relocate MTD image to the top of memory after the uncached memory area */
593 uclinux_ram_map.phys = memory_mtd_start = memory_end;
594 uclinux_ram_map.size = mtd_size;
595 pr_info("Found mtd parition at 0x%p, (len=0x%lx), moving to 0x%p\n",
596 _end, mtd_size, (void *)memory_mtd_start);
597 dma_memcpy((void *)uclinux_ram_map.phys, _end, uclinux_ram_map.size);
598 }
599 #endif /* CONFIG_MTD_UCLINUX */
600
601 /* We need lo limit memory, since everything could have a text section
602 * of userspace in it, and expose anomaly 05000263. If the anomaly
603 * doesn't exist, or we don't need to - then dont.
604 */
605 if (memory_end > max_mem) {
606 pr_info("Limiting kernel memory to %liMB due to anomaly 05000263\n", max_mem >> 20);
607 memory_end = max_mem;
608 }
609
610 #ifdef CONFIG_MPU
611 page_mask_nelts = ((_ramend >> PAGE_SHIFT) + 31) / 32;
612 page_mask_order = get_order(3 * page_mask_nelts * sizeof(long));
613 #endif
614
615 #if !defined(CONFIG_MTD_UCLINUX)
616 /*In case there is no valid CPLB behind memory_end make sure we don't get to close*/
617 memory_end -= SIZE_4K;
618 #endif
619
620 init_mm.start_code = (unsigned long)_stext;
621 init_mm.end_code = (unsigned long)_etext;
622 init_mm.end_data = (unsigned long)_edata;
623 init_mm.brk = (unsigned long)0;
624
625 printk(KERN_INFO "Board Memory: %ldMB\n", physical_mem_end >> 20);
626 printk(KERN_INFO "Kernel Managed Memory: %ldMB\n", _ramend >> 20);
627
628 printk(KERN_INFO "Memory map:\n"
629 " fixedcode = 0x%p-0x%p\n"
630 " text = 0x%p-0x%p\n"
631 " rodata = 0x%p-0x%p\n"
632 " bss = 0x%p-0x%p\n"
633 " data = 0x%p-0x%p\n"
634 " stack = 0x%p-0x%p\n"
635 " init = 0x%p-0x%p\n"
636 " available = 0x%p-0x%p\n"
637 #ifdef CONFIG_MTD_UCLINUX
638 " rootfs = 0x%p-0x%p\n"
639 #endif
640 #if DMA_UNCACHED_REGION > 0
641 " DMA Zone = 0x%p-0x%p\n"
642 #endif
643 , (void *)FIXED_CODE_START, (void *)FIXED_CODE_END,
644 _stext, _etext,
645 __start_rodata, __end_rodata,
646 __bss_start, __bss_stop,
647 _sdata, _edata,
648 (void *)&init_thread_union,
649 (void *)((int)(&init_thread_union) + 0x2000),
650 __init_begin, __init_end,
651 (void *)_ramstart, (void *)memory_end
652 #ifdef CONFIG_MTD_UCLINUX
653 , (void *)memory_mtd_start, (void *)(memory_mtd_start + mtd_size)
654 #endif
655 #if DMA_UNCACHED_REGION > 0
656 , (void *)(_ramend - DMA_UNCACHED_REGION), (void *)(_ramend)
657 #endif
658 );
659 }
660
661 /*
662 * Find the lowest, highest page frame number we have available
663 */
664 void __init find_min_max_pfn(void)
665 {
666 int i;
667
668 max_pfn = 0;
669 min_low_pfn = memory_end;
670
671 for (i = 0; i < bfin_memmap.nr_map; i++) {
672 unsigned long start, end;
673 /* RAM? */
674 if (bfin_memmap.map[i].type != BFIN_MEMMAP_RAM)
675 continue;
676 start = PFN_UP(bfin_memmap.map[i].addr);
677 end = PFN_DOWN(bfin_memmap.map[i].addr +
678 bfin_memmap.map[i].size);
679 if (start >= end)
680 continue;
681 if (end > max_pfn)
682 max_pfn = end;
683 if (start < min_low_pfn)
684 min_low_pfn = start;
685 }
686 }
687
688 static __init void setup_bootmem_allocator(void)
689 {
690 int bootmap_size;
691 int i;
692 unsigned long start_pfn, end_pfn;
693 unsigned long curr_pfn, last_pfn, size;
694
695 /* mark memory between memory_start and memory_end usable */
696 add_memory_region(memory_start,
697 memory_end - memory_start, BFIN_MEMMAP_RAM);
698 /* sanity check for overlap */
699 sanitize_memmap(bfin_memmap.map, &bfin_memmap.nr_map);
700 print_memory_map("boot memmap");
701
702 /* initialize globals in linux/bootmem.h */
703 find_min_max_pfn();
704 /* pfn of the last usable page frame */
705 if (max_pfn > memory_end >> PAGE_SHIFT)
706 max_pfn = memory_end >> PAGE_SHIFT;
707 /* pfn of last page frame directly mapped by kernel */
708 max_low_pfn = max_pfn;
709 /* pfn of the first usable page frame after kernel image*/
710 if (min_low_pfn < memory_start >> PAGE_SHIFT)
711 min_low_pfn = memory_start >> PAGE_SHIFT;
712
713 start_pfn = PAGE_OFFSET >> PAGE_SHIFT;
714 end_pfn = memory_end >> PAGE_SHIFT;
715
716 /*
717 * give all the memory to the bootmap allocator, tell it to put the
718 * boot mem_map at the start of memory.
719 */
720 bootmap_size = init_bootmem_node(NODE_DATA(0),
721 memory_start >> PAGE_SHIFT, /* map goes here */
722 start_pfn, end_pfn);
723
724 /* register the memmap regions with the bootmem allocator */
725 for (i = 0; i < bfin_memmap.nr_map; i++) {
726 /*
727 * Reserve usable memory
728 */
729 if (bfin_memmap.map[i].type != BFIN_MEMMAP_RAM)
730 continue;
731 /*
732 * We are rounding up the start address of usable memory:
733 */
734 curr_pfn = PFN_UP(bfin_memmap.map[i].addr);
735 if (curr_pfn >= end_pfn)
736 continue;
737 /*
738 * ... and at the end of the usable range downwards:
739 */
740 last_pfn = PFN_DOWN(bfin_memmap.map[i].addr +
741 bfin_memmap.map[i].size);
742
743 if (last_pfn > end_pfn)
744 last_pfn = end_pfn;
745
746 /*
747 * .. finally, did all the rounding and playing
748 * around just make the area go away?
749 */
750 if (last_pfn <= curr_pfn)
751 continue;
752
753 size = last_pfn - curr_pfn;
754 free_bootmem(PFN_PHYS(curr_pfn), PFN_PHYS(size));
755 }
756
757 /* reserve memory before memory_start, including bootmap */
758 reserve_bootmem(PAGE_OFFSET,
759 memory_start + bootmap_size + PAGE_SIZE - 1 - PAGE_OFFSET,
760 BOOTMEM_DEFAULT);
761 }
762
763 #define EBSZ_TO_MEG(ebsz) \
764 ({ \
765 int meg = 0; \
766 switch (ebsz & 0xf) { \
767 case 0x1: meg = 16; break; \
768 case 0x3: meg = 32; break; \
769 case 0x5: meg = 64; break; \
770 case 0x7: meg = 128; break; \
771 case 0x9: meg = 256; break; \
772 case 0xb: meg = 512; break; \
773 } \
774 meg; \
775 })
776 static inline int __init get_mem_size(void)
777 {
778 #if defined(EBIU_SDBCTL)
779 # if defined(BF561_FAMILY)
780 int ret = 0;
781 u32 sdbctl = bfin_read_EBIU_SDBCTL();
782 ret += EBSZ_TO_MEG(sdbctl >> 0);
783 ret += EBSZ_TO_MEG(sdbctl >> 8);
784 ret += EBSZ_TO_MEG(sdbctl >> 16);
785 ret += EBSZ_TO_MEG(sdbctl >> 24);
786 return ret;
787 # else
788 return EBSZ_TO_MEG(bfin_read_EBIU_SDBCTL());
789 # endif
790 #elif defined(EBIU_DDRCTL1)
791 u32 ddrctl = bfin_read_EBIU_DDRCTL1();
792 int ret = 0;
793 switch (ddrctl & 0xc0000) {
794 case DEVSZ_64: ret = 64 / 8;
795 case DEVSZ_128: ret = 128 / 8;
796 case DEVSZ_256: ret = 256 / 8;
797 case DEVSZ_512: ret = 512 / 8;
798 }
799 switch (ddrctl & 0x30000) {
800 case DEVWD_4: ret *= 2;
801 case DEVWD_8: ret *= 2;
802 case DEVWD_16: break;
803 }
804 if ((ddrctl & 0xc000) == 0x4000)
805 ret *= 2;
806 return ret;
807 #endif
808 BUG();
809 }
810
811 void __init setup_arch(char **cmdline_p)
812 {
813 unsigned long sclk, cclk;
814
815 enable_shadow_console();
816
817 /* Check to make sure we are running on the right processor */
818 if (unlikely(CPUID != bfin_cpuid()))
819 printk(KERN_ERR "ERROR: Not running on ADSP-%s: unknown CPUID 0x%04x Rev 0.%d\n",
820 CPU, bfin_cpuid(), bfin_revid());
821
822 #ifdef CONFIG_DUMMY_CONSOLE
823 conswitchp = &dummy_con;
824 #endif
825
826 #if defined(CONFIG_CMDLINE_BOOL)
827 strncpy(&command_line[0], CONFIG_CMDLINE, sizeof(command_line));
828 command_line[sizeof(command_line) - 1] = 0;
829 #endif
830
831 /* Keep a copy of command line */
832 *cmdline_p = &command_line[0];
833 memcpy(boot_command_line, command_line, COMMAND_LINE_SIZE);
834 boot_command_line[COMMAND_LINE_SIZE - 1] = '\0';
835
836 memset(&bfin_memmap, 0, sizeof(bfin_memmap));
837
838 /* If the user does not specify things on the command line, use
839 * what the bootloader set things up as
840 */
841 physical_mem_end = 0;
842 parse_cmdline_early(&command_line[0]);
843
844 if (_ramend == 0)
845 _ramend = get_mem_size() * 1024 * 1024;
846
847 if (physical_mem_end == 0)
848 physical_mem_end = _ramend;
849
850 memory_setup();
851
852 /* Initialize Async memory banks */
853 bfin_write_EBIU_AMBCTL0(AMBCTL0VAL);
854 bfin_write_EBIU_AMBCTL1(AMBCTL1VAL);
855 bfin_write_EBIU_AMGCTL(AMGCTLVAL);
856 #ifdef CONFIG_EBIU_MBSCTLVAL
857 bfin_write_EBIU_MBSCTL(CONFIG_EBIU_MBSCTLVAL);
858 bfin_write_EBIU_MODE(CONFIG_EBIU_MODEVAL);
859 bfin_write_EBIU_FCTL(CONFIG_EBIU_FCTLVAL);
860 #endif
861
862 cclk = get_cclk();
863 sclk = get_sclk();
864
865 if ((ANOMALY_05000273 || ANOMALY_05000274) && (cclk >> 1) < sclk)
866 panic("ANOMALY 05000273 or 05000274: CCLK must be >= 2*SCLK");
867
868 #ifdef BF561_FAMILY
869 if (ANOMALY_05000266) {
870 bfin_read_IMDMA_D0_IRQ_STATUS();
871 bfin_read_IMDMA_D1_IRQ_STATUS();
872 }
873 #endif
874 printk(KERN_INFO "Hardware Trace ");
875 if (bfin_read_TBUFCTL() & 0x1)
876 printk(KERN_CONT "Active ");
877 else
878 printk(KERN_CONT "Off ");
879 if (bfin_read_TBUFCTL() & 0x2)
880 printk(KERN_CONT "and Enabled\n");
881 else
882 printk(KERN_CONT "and Disabled\n");
883
884 printk(KERN_INFO "Boot Mode: %i\n", bfin_read_SYSCR() & 0xF);
885
886 /* Newer parts mirror SWRST bits in SYSCR */
887 #if defined(CONFIG_BF53x) || defined(CONFIG_BF561) || \
888 defined(CONFIG_BF538) || defined(CONFIG_BF539)
889 _bfin_swrst = bfin_read_SWRST();
890 #else
891 /* Clear boot mode field */
892 _bfin_swrst = bfin_read_SYSCR() & ~0xf;
893 #endif
894
895 #ifdef CONFIG_DEBUG_DOUBLEFAULT_PRINT
896 bfin_write_SWRST(_bfin_swrst & ~DOUBLE_FAULT);
897 #endif
898 #ifdef CONFIG_DEBUG_DOUBLEFAULT_RESET
899 bfin_write_SWRST(_bfin_swrst | DOUBLE_FAULT);
900 #endif
901
902 #ifdef CONFIG_SMP
903 if (_bfin_swrst & SWRST_DBL_FAULT_A) {
904 #else
905 if (_bfin_swrst & RESET_DOUBLE) {
906 #endif
907 printk(KERN_EMERG "Recovering from DOUBLE FAULT event\n");
908 #ifdef CONFIG_DEBUG_DOUBLEFAULT
909 /* We assume the crashing kernel, and the current symbol table match */
910 printk(KERN_EMERG " While handling exception (EXCAUSE = 0x%x) at %pF\n",
911 (int)init_saved_seqstat & SEQSTAT_EXCAUSE, init_saved_retx);
912 printk(KERN_NOTICE " DCPLB_FAULT_ADDR: %pF\n", init_saved_dcplb_fault_addr);
913 printk(KERN_NOTICE " ICPLB_FAULT_ADDR: %pF\n", init_saved_icplb_fault_addr);
914 #endif
915 printk(KERN_NOTICE " The instruction at %pF caused a double exception\n",
916 init_retx);
917 } else if (_bfin_swrst & RESET_WDOG)
918 printk(KERN_INFO "Recovering from Watchdog event\n");
919 else if (_bfin_swrst & RESET_SOFTWARE)
920 printk(KERN_NOTICE "Reset caused by Software reset\n");
921
922 printk(KERN_INFO "Blackfin support (C) 2004-2009 Analog Devices, Inc.\n");
923 if (bfin_compiled_revid() == 0xffff)
924 printk(KERN_INFO "Compiled for ADSP-%s Rev any\n", CPU);
925 else if (bfin_compiled_revid() == -1)
926 printk(KERN_INFO "Compiled for ADSP-%s Rev none\n", CPU);
927 else
928 printk(KERN_INFO "Compiled for ADSP-%s Rev 0.%d\n", CPU, bfin_compiled_revid());
929
930 if (likely(CPUID == bfin_cpuid())) {
931 if (bfin_revid() != bfin_compiled_revid()) {
932 if (bfin_compiled_revid() == -1)
933 printk(KERN_ERR "Warning: Compiled for Rev none, but running on Rev %d\n",
934 bfin_revid());
935 else if (bfin_compiled_revid() != 0xffff) {
936 printk(KERN_ERR "Warning: Compiled for Rev %d, but running on Rev %d\n",
937 bfin_compiled_revid(), bfin_revid());
938 if (bfin_compiled_revid() > bfin_revid())
939 panic("Error: you are missing anomaly workarounds for this rev");
940 }
941 }
942 if (bfin_revid() < CONFIG_BF_REV_MIN || bfin_revid() > CONFIG_BF_REV_MAX)
943 printk(KERN_ERR "Warning: Unsupported Chip Revision ADSP-%s Rev 0.%d detected\n",
944 CPU, bfin_revid());
945 }
946
947 printk(KERN_INFO "Blackfin Linux support by http://blackfin.uclinux.org/\n");
948
949 printk(KERN_INFO "Processor Speed: %lu MHz core clock and %lu MHz System Clock\n",
950 cclk / 1000000, sclk / 1000000);
951
952 setup_bootmem_allocator();
953
954 paging_init();
955
956 /* Copy atomic sequences to their fixed location, and sanity check that
957 these locations are the ones that we advertise to userspace. */
958 memcpy((void *)FIXED_CODE_START, &fixed_code_start,
959 FIXED_CODE_END - FIXED_CODE_START);
960 BUG_ON((char *)&sigreturn_stub - (char *)&fixed_code_start
961 != SIGRETURN_STUB - FIXED_CODE_START);
962 BUG_ON((char *)&atomic_xchg32 - (char *)&fixed_code_start
963 != ATOMIC_XCHG32 - FIXED_CODE_START);
964 BUG_ON((char *)&atomic_cas32 - (char *)&fixed_code_start
965 != ATOMIC_CAS32 - FIXED_CODE_START);
966 BUG_ON((char *)&atomic_add32 - (char *)&fixed_code_start
967 != ATOMIC_ADD32 - FIXED_CODE_START);
968 BUG_ON((char *)&atomic_sub32 - (char *)&fixed_code_start
969 != ATOMIC_SUB32 - FIXED_CODE_START);
970 BUG_ON((char *)&atomic_ior32 - (char *)&fixed_code_start
971 != ATOMIC_IOR32 - FIXED_CODE_START);
972 BUG_ON((char *)&atomic_and32 - (char *)&fixed_code_start
973 != ATOMIC_AND32 - FIXED_CODE_START);
974 BUG_ON((char *)&atomic_xor32 - (char *)&fixed_code_start
975 != ATOMIC_XOR32 - FIXED_CODE_START);
976 BUG_ON((char *)&safe_user_instruction - (char *)&fixed_code_start
977 != SAFE_USER_INSTRUCTION - FIXED_CODE_START);
978
979 #ifdef CONFIG_SMP
980 platform_init_cpus();
981 #endif
982 init_exception_vectors();
983 bfin_cache_init(); /* Initialize caches for the boot CPU */
984 }
985
986 static int __init topology_init(void)
987 {
988 unsigned int cpu;
989 /* Record CPU-private information for the boot processor. */
990 bfin_setup_cpudata(0);
991
992 for_each_possible_cpu(cpu) {
993 register_cpu(&per_cpu(cpu_data, cpu).cpu, cpu);
994 }
995
996 return 0;
997 }
998
999 subsys_initcall(topology_init);
1000
1001 /* Get the input clock frequency */
1002 static u_long cached_clkin_hz = CONFIG_CLKIN_HZ;
1003 static u_long get_clkin_hz(void)
1004 {
1005 return cached_clkin_hz;
1006 }
1007 static int __init early_init_clkin_hz(char *buf)
1008 {
1009 cached_clkin_hz = simple_strtoul(buf, NULL, 0);
1010 #ifdef BFIN_KERNEL_CLOCK
1011 if (cached_clkin_hz != CONFIG_CLKIN_HZ)
1012 panic("cannot change clkin_hz when reprogramming clocks");
1013 #endif
1014 return 1;
1015 }
1016 early_param("clkin_hz=", early_init_clkin_hz);
1017
1018 /* Get the voltage input multiplier */
1019 static u_long get_vco(void)
1020 {
1021 static u_long cached_vco;
1022 u_long msel, pll_ctl;
1023
1024 /* The assumption here is that VCO never changes at runtime.
1025 * If, someday, we support that, then we'll have to change this.
1026 */
1027 if (cached_vco)
1028 return cached_vco;
1029
1030 pll_ctl = bfin_read_PLL_CTL();
1031 msel = (pll_ctl >> 9) & 0x3F;
1032 if (0 == msel)
1033 msel = 64;
1034
1035 cached_vco = get_clkin_hz();
1036 cached_vco >>= (1 & pll_ctl); /* DF bit */
1037 cached_vco *= msel;
1038 return cached_vco;
1039 }
1040
1041 /* Get the Core clock */
1042 u_long get_cclk(void)
1043 {
1044 static u_long cached_cclk_pll_div, cached_cclk;
1045 u_long csel, ssel;
1046
1047 if (bfin_read_PLL_STAT() & 0x1)
1048 return get_clkin_hz();
1049
1050 ssel = bfin_read_PLL_DIV();
1051 if (ssel == cached_cclk_pll_div)
1052 return cached_cclk;
1053 else
1054 cached_cclk_pll_div = ssel;
1055
1056 csel = ((ssel >> 4) & 0x03);
1057 ssel &= 0xf;
1058 if (ssel && ssel < (1 << csel)) /* SCLK > CCLK */
1059 cached_cclk = get_vco() / ssel;
1060 else
1061 cached_cclk = get_vco() >> csel;
1062 return cached_cclk;
1063 }
1064 EXPORT_SYMBOL(get_cclk);
1065
1066 /* Get the System clock */
1067 u_long get_sclk(void)
1068 {
1069 static u_long cached_sclk;
1070 u_long ssel;
1071
1072 /* The assumption here is that SCLK never changes at runtime.
1073 * If, someday, we support that, then we'll have to change this.
1074 */
1075 if (cached_sclk)
1076 return cached_sclk;
1077
1078 if (bfin_read_PLL_STAT() & 0x1)
1079 return get_clkin_hz();
1080
1081 ssel = bfin_read_PLL_DIV() & 0xf;
1082 if (0 == ssel) {
1083 printk(KERN_WARNING "Invalid System Clock\n");
1084 ssel = 1;
1085 }
1086
1087 cached_sclk = get_vco() / ssel;
1088 return cached_sclk;
1089 }
1090 EXPORT_SYMBOL(get_sclk);
1091
1092 unsigned long sclk_to_usecs(unsigned long sclk)
1093 {
1094 u64 tmp = USEC_PER_SEC * (u64)sclk;
1095 do_div(tmp, get_sclk());
1096 return tmp;
1097 }
1098 EXPORT_SYMBOL(sclk_to_usecs);
1099
1100 unsigned long usecs_to_sclk(unsigned long usecs)
1101 {
1102 u64 tmp = get_sclk() * (u64)usecs;
1103 do_div(tmp, USEC_PER_SEC);
1104 return tmp;
1105 }
1106 EXPORT_SYMBOL(usecs_to_sclk);
1107
1108 /*
1109 * Get CPU information for use by the procfs.
1110 */
1111 static int show_cpuinfo(struct seq_file *m, void *v)
1112 {
1113 char *cpu, *mmu, *fpu, *vendor, *cache;
1114 uint32_t revid;
1115 int cpu_num = *(unsigned int *)v;
1116 u_long sclk, cclk;
1117 u_int icache_size = BFIN_ICACHESIZE / 1024, dcache_size = 0, dsup_banks = 0;
1118 struct blackfin_cpudata *cpudata = &per_cpu(cpu_data, cpu_num);
1119
1120 cpu = CPU;
1121 mmu = "none";
1122 fpu = "none";
1123 revid = bfin_revid();
1124
1125 sclk = get_sclk();
1126 cclk = get_cclk();
1127
1128 switch (bfin_read_CHIPID() & CHIPID_MANUFACTURE) {
1129 case 0xca:
1130 vendor = "Analog Devices";
1131 break;
1132 default:
1133 vendor = "unknown";
1134 break;
1135 }
1136
1137 seq_printf(m, "processor\t: %d\n" "vendor_id\t: %s\n", cpu_num, vendor);
1138
1139 if (CPUID == bfin_cpuid())
1140 seq_printf(m, "cpu family\t: 0x%04x\n", CPUID);
1141 else
1142 seq_printf(m, "cpu family\t: Compiled for:0x%04x, running on:0x%04x\n",
1143 CPUID, bfin_cpuid());
1144
1145 seq_printf(m, "model name\t: ADSP-%s %lu(MHz CCLK) %lu(MHz SCLK) (%s)\n"
1146 "stepping\t: %d ",
1147 cpu, cclk/1000000, sclk/1000000,
1148 #ifdef CONFIG_MPU
1149 "mpu on",
1150 #else
1151 "mpu off",
1152 #endif
1153 revid);
1154
1155 if (bfin_revid() != bfin_compiled_revid()) {
1156 if (bfin_compiled_revid() == -1)
1157 seq_printf(m, "(Compiled for Rev none)");
1158 else if (bfin_compiled_revid() == 0xffff)
1159 seq_printf(m, "(Compiled for Rev any)");
1160 else
1161 seq_printf(m, "(Compiled for Rev %d)", bfin_compiled_revid());
1162 }
1163
1164 seq_printf(m, "\ncpu MHz\t\t: %lu.%03lu/%lu.%03lu\n",
1165 cclk/1000000, cclk%1000000,
1166 sclk/1000000, sclk%1000000);
1167 seq_printf(m, "bogomips\t: %lu.%02lu\n"
1168 "Calibration\t: %lu loops\n",
1169 (loops_per_jiffy * HZ) / 500000,
1170 ((loops_per_jiffy * HZ) / 5000) % 100,
1171 (loops_per_jiffy * HZ));
1172
1173 /* Check Cache configutation */
1174 switch (cpudata->dmemctl & (1 << DMC0_P | 1 << DMC1_P)) {
1175 case ACACHE_BSRAM:
1176 cache = "dbank-A/B\t: cache/sram";
1177 dcache_size = 16;
1178 dsup_banks = 1;
1179 break;
1180 case ACACHE_BCACHE:
1181 cache = "dbank-A/B\t: cache/cache";
1182 dcache_size = 32;
1183 dsup_banks = 2;
1184 break;
1185 case ASRAM_BSRAM:
1186 cache = "dbank-A/B\t: sram/sram";
1187 dcache_size = 0;
1188 dsup_banks = 0;
1189 break;
1190 default:
1191 cache = "unknown";
1192 dcache_size = 0;
1193 dsup_banks = 0;
1194 break;
1195 }
1196
1197 /* Is it turned on? */
1198 if ((cpudata->dmemctl & (ENDCPLB | DMC_ENABLE)) != (ENDCPLB | DMC_ENABLE))
1199 dcache_size = 0;
1200
1201 if ((cpudata->imemctl & (IMC | ENICPLB)) != (IMC | ENICPLB))
1202 icache_size = 0;
1203
1204 seq_printf(m, "cache size\t: %d KB(L1 icache) "
1205 "%d KB(L1 dcache) %d KB(L2 cache)\n",
1206 icache_size, dcache_size, 0);
1207 seq_printf(m, "%s\n", cache);
1208 seq_printf(m, "external memory\t: "
1209 #if defined(CONFIG_BFIN_EXTMEM_ICACHEABLE)
1210 "cacheable"
1211 #else
1212 "uncacheable"
1213 #endif
1214 " in instruction cache\n");
1215 seq_printf(m, "external memory\t: "
1216 #if defined(CONFIG_BFIN_EXTMEM_WRITEBACK)
1217 "cacheable (write-back)"
1218 #elif defined(CONFIG_BFIN_EXTMEM_WRITETHROUGH)
1219 "cacheable (write-through)"
1220 #else
1221 "uncacheable"
1222 #endif
1223 " in data cache\n");
1224
1225 if (icache_size)
1226 seq_printf(m, "icache setup\t: %d Sub-banks/%d Ways, %d Lines/Way\n",
1227 BFIN_ISUBBANKS, BFIN_IWAYS, BFIN_ILINES);
1228 else
1229 seq_printf(m, "icache setup\t: off\n");
1230
1231 seq_printf(m,
1232 "dcache setup\t: %d Super-banks/%d Sub-banks/%d Ways, %d Lines/Way\n",
1233 dsup_banks, BFIN_DSUBBANKS, BFIN_DWAYS,
1234 BFIN_DLINES);
1235 #ifdef __ARCH_SYNC_CORE_DCACHE
1236 seq_printf(m, "SMP Dcache Flushes\t: %lu\n\n", cpudata->dcache_invld_count);
1237 #endif
1238 #ifdef __ARCH_SYNC_CORE_ICACHE
1239 seq_printf(m, "SMP Icache Flushes\t: %lu\n\n", cpudata->icache_invld_count);
1240 #endif
1241
1242 if (cpu_num != num_possible_cpus() - 1)
1243 return 0;
1244
1245 if (L2_LENGTH) {
1246 seq_printf(m, "L2 SRAM\t\t: %dKB\n", L2_LENGTH/0x400);
1247 seq_printf(m, "L2 SRAM\t\t: "
1248 #if defined(CONFIG_BFIN_L2_ICACHEABLE)
1249 "cacheable"
1250 #else
1251 "uncacheable"
1252 #endif
1253 " in instruction cache\n");
1254 seq_printf(m, "L2 SRAM\t\t: "
1255 #if defined(CONFIG_BFIN_L2_WRITEBACK)
1256 "cacheable (write-back)"
1257 #elif defined(CONFIG_BFIN_L2_WRITETHROUGH)
1258 "cacheable (write-through)"
1259 #else
1260 "uncacheable"
1261 #endif
1262 " in data cache\n");
1263 }
1264 seq_printf(m, "board name\t: %s\n", bfin_board_name);
1265 seq_printf(m, "board memory\t: %ld kB (0x%p -> 0x%p)\n",
1266 physical_mem_end >> 10, (void *)0, (void *)physical_mem_end);
1267 seq_printf(m, "kernel memory\t: %d kB (0x%p -> 0x%p)\n",
1268 ((int)memory_end - (int)_stext) >> 10,
1269 _stext,
1270 (void *)memory_end);
1271 seq_printf(m, "\n");
1272
1273 return 0;
1274 }
1275
1276 static void *c_start(struct seq_file *m, loff_t *pos)
1277 {
1278 if (*pos == 0)
1279 *pos = first_cpu(cpu_online_map);
1280 if (*pos >= num_online_cpus())
1281 return NULL;
1282
1283 return pos;
1284 }
1285
1286 static void *c_next(struct seq_file *m, void *v, loff_t *pos)
1287 {
1288 *pos = next_cpu(*pos, cpu_online_map);
1289
1290 return c_start(m, pos);
1291 }
1292
1293 static void c_stop(struct seq_file *m, void *v)
1294 {
1295 }
1296
1297 const struct seq_operations cpuinfo_op = {
1298 .start = c_start,
1299 .next = c_next,
1300 .stop = c_stop,
1301 .show = show_cpuinfo,
1302 };
1303
1304 void __init cmdline_init(const char *r0)
1305 {
1306 early_shadow_stamp();
1307 if (r0)
1308 strncpy(command_line, r0, COMMAND_LINE_SIZE);
1309 }
Linux kernel - Deliverables
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