projects / deliverable / linux.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
Merge branch 'wm8974-upstream' into for-2.6.32
[deliverable/linux.git] / arch / blackfin / kernel / setup.c
1 /*
2 * arch/blackfin/kernel/setup.c
3 *
4 * Copyright 2004-2006 Analog Devices Inc.
5 *
6 * Enter bugs at http://blackfin.uclinux.org/
7 *
8 * Licensed under the GPL-2 or later.
9 */
10
11 #include <linux/delay.h>
12 #include <linux/console.h>
13 #include <linux/bootmem.h>
14 #include <linux/seq_file.h>
15 #include <linux/cpu.h>
16 #include <linux/mm.h>
17 #include <linux/module.h>
18 #include <linux/tty.h>
19 #include <linux/pfn.h>
20
21 #ifdef CONFIG_MTD_UCLINUX
22 #include <linux/mtd/map.h>
23 #include <linux/ext2_fs.h>
24 #include <linux/cramfs_fs.h>
25 #include <linux/romfs_fs.h>
26 #endif
27
28 #include <asm/cplb.h>
29 #include <asm/cacheflush.h>
30 #include <asm/blackfin.h>
31 #include <asm/cplbinit.h>
32 #include <asm/div64.h>
33 #include <asm/cpu.h>
34 #include <asm/fixed_code.h>
35 #include <asm/early_printk.h>
36
37 u16 _bfin_swrst;
38 EXPORT_SYMBOL(_bfin_swrst);
39
40 unsigned long memory_start, memory_end, physical_mem_end;
41 unsigned long _rambase, _ramstart, _ramend;
42 unsigned long reserved_mem_dcache_on;
43 unsigned long reserved_mem_icache_on;
44 EXPORT_SYMBOL(memory_start);
45 EXPORT_SYMBOL(memory_end);
46 EXPORT_SYMBOL(physical_mem_end);
47 EXPORT_SYMBOL(_ramend);
48 EXPORT_SYMBOL(reserved_mem_dcache_on);
49
50 #ifdef CONFIG_MTD_UCLINUX
51 extern struct map_info uclinux_ram_map;
52 unsigned long memory_mtd_end, memory_mtd_start, mtd_size;
53 unsigned long _ebss;
54 EXPORT_SYMBOL(memory_mtd_end);
55 EXPORT_SYMBOL(memory_mtd_start);
56 EXPORT_SYMBOL(mtd_size);
57 #endif
58
59 char __initdata command_line[COMMAND_LINE_SIZE];
60 void __initdata *init_retx, *init_saved_retx, *init_saved_seqstat,
61 *init_saved_icplb_fault_addr, *init_saved_dcplb_fault_addr;
62
63 /* boot memmap, for parsing "memmap=" */
64 #define BFIN_MEMMAP_MAX 128 /* number of entries in bfin_memmap */
65 #define BFIN_MEMMAP_RAM 1
66 #define BFIN_MEMMAP_RESERVED 2
67 static struct bfin_memmap {
68 int nr_map;
69 struct bfin_memmap_entry {
70 unsigned long long addr; /* start of memory segment */
71 unsigned long long size;
72 unsigned long type;
73 } map[BFIN_MEMMAP_MAX];
74 } bfin_memmap __initdata;
75
76 /* for memmap sanitization */
77 struct change_member {
78 struct bfin_memmap_entry *pentry; /* pointer to original entry */
79 unsigned long long addr; /* address for this change point */
80 };
81 static struct change_member change_point_list[2*BFIN_MEMMAP_MAX] __initdata;
82 static struct change_member *change_point[2*BFIN_MEMMAP_MAX] __initdata;
83 static struct bfin_memmap_entry *overlap_list[BFIN_MEMMAP_MAX] __initdata;
84 static struct bfin_memmap_entry new_map[BFIN_MEMMAP_MAX] __initdata;
85
86 DEFINE_PER_CPU(struct blackfin_cpudata, cpu_data);
87
88 static int early_init_clkin_hz(char *buf);
89
90 #if defined(CONFIG_BFIN_DCACHE) || defined(CONFIG_BFIN_ICACHE)
91 void __init generate_cplb_tables(void)
92 {
93 unsigned int cpu;
94
95 generate_cplb_tables_all();
96 /* Generate per-CPU I&D CPLB tables */
97 for (cpu = 0; cpu < num_possible_cpus(); ++cpu)
98 generate_cplb_tables_cpu(cpu);
99 }
100 #endif
101
102 void __cpuinit bfin_setup_caches(unsigned int cpu)
103 {
104 #ifdef CONFIG_BFIN_ICACHE
105 bfin_icache_init(icplb_tbl[cpu]);
106 #endif
107
108 #ifdef CONFIG_BFIN_DCACHE
109 bfin_dcache_init(dcplb_tbl[cpu]);
110 #endif
111
112 /*
113 * In cache coherence emulation mode, we need to have the
114 * D-cache enabled before running any atomic operation which
115 * might invove cache invalidation (i.e. spinlock, rwlock).
116 * So printk's are deferred until then.
117 */
118 #ifdef CONFIG_BFIN_ICACHE
119 printk(KERN_INFO "Instruction Cache Enabled for CPU%u\n", cpu);
120 printk(KERN_INFO " External memory:"
121 # ifdef CONFIG_BFIN_EXTMEM_ICACHEABLE
122 " cacheable"
123 # else
124 " uncacheable"
125 # endif
126 " in instruction cache\n");
127 if (L2_LENGTH)
128 printk(KERN_INFO " L2 SRAM :"
129 # ifdef CONFIG_BFIN_L2_ICACHEABLE
130 " cacheable"
131 # else
132 " uncacheable"
133 # endif
134 " in instruction cache\n");
135
136 #else
137 printk(KERN_INFO "Instruction Cache Disabled for CPU%u\n", cpu);
138 #endif
139
140 #ifdef CONFIG_BFIN_DCACHE
141 printk(KERN_INFO "Data Cache Enabled for CPU%u\n", cpu);
142 printk(KERN_INFO " External memory:"
143 # if defined CONFIG_BFIN_EXTMEM_WRITEBACK
144 " cacheable (write-back)"
145 # elif defined CONFIG_BFIN_EXTMEM_WRITETHROUGH
146 " cacheable (write-through)"
147 # else
148 " uncacheable"
149 # endif
150 " in data cache\n");
151 if (L2_LENGTH)
152 printk(KERN_INFO " L2 SRAM :"
153 # if defined CONFIG_BFIN_L2_WRITEBACK
154 " cacheable (write-back)"
155 # elif defined CONFIG_BFIN_L2_WRITETHROUGH
156 " cacheable (write-through)"
157 # else
158 " uncacheable"
159 # endif
160 " in data cache\n");
161 #else
162 printk(KERN_INFO "Data Cache Disabled for CPU%u\n", cpu);
163 #endif
164 }
165
166 void __cpuinit bfin_setup_cpudata(unsigned int cpu)
167 {
168 struct blackfin_cpudata *cpudata = &per_cpu(cpu_data, cpu);
169
170 cpudata->idle = current;
171 cpudata->loops_per_jiffy = loops_per_jiffy;
172 cpudata->imemctl = bfin_read_IMEM_CONTROL();
173 cpudata->dmemctl = bfin_read_DMEM_CONTROL();
174 }
175
176 void __init bfin_cache_init(void)
177 {
178 #if defined(CONFIG_BFIN_DCACHE) || defined(CONFIG_BFIN_ICACHE)
179 generate_cplb_tables();
180 #endif
181 bfin_setup_caches(0);
182 }
183
184 void __init bfin_relocate_l1_mem(void)
185 {
186 unsigned long l1_code_length;
187 unsigned long l1_data_a_length;
188 unsigned long l1_data_b_length;
189 unsigned long l2_length;
190
191 /*
192 * due to the ALIGN(4) in the arch/blackfin/kernel/vmlinux.lds.S
193 * we know that everything about l1 text/data is nice and aligned,
194 * so copy by 4 byte chunks, and don't worry about overlapping
195 * src/dest.
196 *
197 * We can't use the dma_memcpy functions, since they can call
198 * scheduler functions which might be in L1 :( and core writes
199 * into L1 instruction cause bad access errors, so we are stuck,
200 * we are required to use DMA, but can't use the common dma
201 * functions. We can't use memcpy either - since that might be
202 * going to be in the relocated L1
203 */
204
205 blackfin_dma_early_init();
206
207 /* if necessary, copy _stext_l1 to _etext_l1 to L1 instruction SRAM */
208 l1_code_length = _etext_l1 - _stext_l1;
209 if (l1_code_length)
210 early_dma_memcpy(_stext_l1, _l1_lma_start, l1_code_length);
211
212 /* if necessary, copy _sdata_l1 to _sbss_l1 to L1 data bank A SRAM */
213 l1_data_a_length = _sbss_l1 - _sdata_l1;
214 if (l1_data_a_length)
215 early_dma_memcpy(_sdata_l1, _l1_lma_start + l1_code_length, l1_data_a_length);
216
217 /* if necessary, copy _sdata_b_l1 to _sbss_b_l1 to L1 data bank B SRAM */
218 l1_data_b_length = _sbss_b_l1 - _sdata_b_l1;
219 if (l1_data_b_length)
220 early_dma_memcpy(_sdata_b_l1, _l1_lma_start + l1_code_length +
221 l1_data_a_length, l1_data_b_length);
222
223 early_dma_memcpy_done();
224
225 /* if necessary, copy _stext_l2 to _edata_l2 to L2 SRAM */
226 if (L2_LENGTH != 0) {
227 l2_length = _sbss_l2 - _stext_l2;
228 if (l2_length)
229 memcpy(_stext_l2, _l2_lma_start, l2_length);
230 }
231 }
232
233 /* add_memory_region to memmap */
234 static void __init add_memory_region(unsigned long long start,
235 unsigned long long size, int type)
236 {
237 int i;
238
239 i = bfin_memmap.nr_map;
240
241 if (i == BFIN_MEMMAP_MAX) {
242 printk(KERN_ERR "Ooops! Too many entries in the memory map!\n");
243 return;
244 }
245
246 bfin_memmap.map[i].addr = start;
247 bfin_memmap.map[i].size = size;
248 bfin_memmap.map[i].type = type;
249 bfin_memmap.nr_map++;
250 }
251
252 /*
253 * Sanitize the boot memmap, removing overlaps.
254 */
255 static int __init sanitize_memmap(struct bfin_memmap_entry *map, int *pnr_map)
256 {
257 struct change_member *change_tmp;
258 unsigned long current_type, last_type;
259 unsigned long long last_addr;
260 int chgidx, still_changing;
261 int overlap_entries;
262 int new_entry;
263 int old_nr, new_nr, chg_nr;
264 int i;
265
266 /*
267 Visually we're performing the following (1,2,3,4 = memory types)
268
269 Sample memory map (w/overlaps):
270 ____22__________________
271 ______________________4_
272 ____1111________________
273 _44_____________________
274 11111111________________
275 ____________________33__
276 ___________44___________
277 __________33333_________
278 ______________22________
279 ___________________2222_
280 _________111111111______
281 _____________________11_
282 _________________4______
283
284 Sanitized equivalent (no overlap):
285 1_______________________
286 _44_____________________
287 ___1____________________
288 ____22__________________
289 ______11________________
290 _________1______________
291 __________3_____________
292 ___________44___________
293 _____________33_________
294 _______________2________
295 ________________1_______
296 _________________4______
297 ___________________2____
298 ____________________33__
299 ______________________4_
300 */
301 /* if there's only one memory region, don't bother */
302 if (*pnr_map < 2)
303 return -1;
304
305 old_nr = *pnr_map;
306
307 /* bail out if we find any unreasonable addresses in memmap */
308 for (i = 0; i < old_nr; i++)
309 if (map[i].addr + map[i].size < map[i].addr)
310 return -1;
311
312 /* create pointers for initial change-point information (for sorting) */
313 for (i = 0; i < 2*old_nr; i++)
314 change_point[i] = &change_point_list[i];
315
316 /* record all known change-points (starting and ending addresses),
317 omitting those that are for empty memory regions */
318 chgidx = 0;
319 for (i = 0; i < old_nr; i++) {
320 if (map[i].size != 0) {
321 change_point[chgidx]->addr = map[i].addr;
322 change_point[chgidx++]->pentry = &map[i];
323 change_point[chgidx]->addr = map[i].addr + map[i].size;
324 change_point[chgidx++]->pentry = &map[i];
325 }
326 }
327 chg_nr = chgidx; /* true number of change-points */
328
329 /* sort change-point list by memory addresses (low -> high) */
330 still_changing = 1;
331 while (still_changing) {
332 still_changing = 0;
333 for (i = 1; i < chg_nr; i++) {
334 /* if <current_addr> > <last_addr>, swap */
335 /* or, if current=<start_addr> & last=<end_addr>, swap */
336 if ((change_point[i]->addr < change_point[i-1]->addr) ||
337 ((change_point[i]->addr == change_point[i-1]->addr) &&
338 (change_point[i]->addr == change_point[i]->pentry->addr) &&
339 (change_point[i-1]->addr != change_point[i-1]->pentry->addr))
340 ) {
341 change_tmp = change_point[i];
342 change_point[i] = change_point[i-1];
343 change_point[i-1] = change_tmp;
344 still_changing = 1;
345 }
346 }
347 }
348
349 /* create a new memmap, removing overlaps */
350 overlap_entries = 0; /* number of entries in the overlap table */
351 new_entry = 0; /* index for creating new memmap entries */
352 last_type = 0; /* start with undefined memory type */
353 last_addr = 0; /* start with 0 as last starting address */
354 /* loop through change-points, determining affect on the new memmap */
355 for (chgidx = 0; chgidx < chg_nr; chgidx++) {
356 /* keep track of all overlapping memmap entries */
357 if (change_point[chgidx]->addr == change_point[chgidx]->pentry->addr) {
358 /* add map entry to overlap list (> 1 entry implies an overlap) */
359 overlap_list[overlap_entries++] = change_point[chgidx]->pentry;
360 } else {
361 /* remove entry from list (order independent, so swap with last) */
362 for (i = 0; i < overlap_entries; i++) {
363 if (overlap_list[i] == change_point[chgidx]->pentry)
364 overlap_list[i] = overlap_list[overlap_entries-1];
365 }
366 overlap_entries--;
367 }
368 /* if there are overlapping entries, decide which "type" to use */
369 /* (larger value takes precedence -- 1=usable, 2,3,4,4+=unusable) */
370 current_type = 0;
371 for (i = 0; i < overlap_entries; i++)
372 if (overlap_list[i]->type > current_type)
373 current_type = overlap_list[i]->type;
374 /* continue building up new memmap based on this information */
375 if (current_type != last_type) {
376 if (last_type != 0) {
377 new_map[new_entry].size =
378 change_point[chgidx]->addr - last_addr;
379 /* move forward only if the new size was non-zero */
380 if (new_map[new_entry].size != 0)
381 if (++new_entry >= BFIN_MEMMAP_MAX)
382 break; /* no more space left for new entries */
383 }
384 if (current_type != 0) {
385 new_map[new_entry].addr = change_point[chgidx]->addr;
386 new_map[new_entry].type = current_type;
387 last_addr = change_point[chgidx]->addr;
388 }
389 last_type = current_type;
390 }
391 }
392 new_nr = new_entry; /* retain count for new entries */
393
394 /* copy new mapping into original location */
395 memcpy(map, new_map, new_nr*sizeof(struct bfin_memmap_entry));
396 *pnr_map = new_nr;
397
398 return 0;
399 }
400
401 static void __init print_memory_map(char *who)
402 {
403 int i;
404
405 for (i = 0; i < bfin_memmap.nr_map; i++) {
406 printk(KERN_DEBUG " %s: %016Lx - %016Lx ", who,
407 bfin_memmap.map[i].addr,
408 bfin_memmap.map[i].addr + bfin_memmap.map[i].size);
409 switch (bfin_memmap.map[i].type) {
410 case BFIN_MEMMAP_RAM:
411 printk("(usable)\n");
412 break;
413 case BFIN_MEMMAP_RESERVED:
414 printk("(reserved)\n");
415 break;
416 default: printk("type %lu\n", bfin_memmap.map[i].type);
417 break;
418 }
419 }
420 }
421
422 static __init int parse_memmap(char *arg)
423 {
424 unsigned long long start_at, mem_size;
425
426 if (!arg)
427 return -EINVAL;
428
429 mem_size = memparse(arg, &arg);
430 if (*arg == '@') {
431 start_at = memparse(arg+1, &arg);
432 add_memory_region(start_at, mem_size, BFIN_MEMMAP_RAM);
433 } else if (*arg == '$') {
434 start_at = memparse(arg+1, &arg);
435 add_memory_region(start_at, mem_size, BFIN_MEMMAP_RESERVED);
436 }
437
438 return 0;
439 }
440
441 /*
442 * Initial parsing of the command line. Currently, we support:
443 * - Controlling the linux memory size: mem=xxx[KMG]
444 * - Controlling the physical memory size: max_mem=xxx[KMG][$][#]
445 * $ -> reserved memory is dcacheable
446 * # -> reserved memory is icacheable
447 * - "memmap=XXX[KkmM][@][$]XXX[KkmM]" defines a memory region
448 * @ from <start> to <start>+<mem>, type RAM
449 * $ from <start> to <start>+<mem>, type RESERVED
450 */
451 static __init void parse_cmdline_early(char *cmdline_p)
452 {
453 char c = ' ', *to = cmdline_p;
454 unsigned int memsize;
455 for (;;) {
456 if (c == ' ') {
457 if (!memcmp(to, "mem=", 4)) {
458 to += 4;
459 memsize = memparse(to, &to);
460 if (memsize)
461 _ramend = memsize;
462
463 } else if (!memcmp(to, "max_mem=", 8)) {
464 to += 8;
465 memsize = memparse(to, &to);
466 if (memsize) {
467 physical_mem_end = memsize;
468 if (*to != ' ') {
469 if (*to == '$'
470 || *(to + 1) == '$')
471 reserved_mem_dcache_on = 1;
472 if (*to == '#'
473 || *(to + 1) == '#')
474 reserved_mem_icache_on = 1;
475 }
476 }
477 } else if (!memcmp(to, "clkin_hz=", 9)) {
478 to += 9;
479 early_init_clkin_hz(to);
480 #ifdef CONFIG_EARLY_PRINTK
481 } else if (!memcmp(to, "earlyprintk=", 12)) {
482 to += 12;
483 setup_early_printk(to);
484 #endif
485 } else if (!memcmp(to, "memmap=", 7)) {
486 to += 7;
487 parse_memmap(to);
488 }
489 }
490 c = *(to++);
491 if (!c)
492 break;
493 }
494 }
495
496 /*
497 * Setup memory defaults from user config.
498 * The physical memory layout looks like:
499 *
500 * [_rambase, _ramstart]: kernel image
501 * [memory_start, memory_end]: dynamic memory managed by kernel
502 * [memory_end, _ramend]: reserved memory
503 * [memory_mtd_start(memory_end),
504 * memory_mtd_start + mtd_size]: rootfs (if any)
505 * [_ramend - DMA_UNCACHED_REGION,
506 * _ramend]: uncached DMA region
507 * [_ramend, physical_mem_end]: memory not managed by kernel
508 */
509 static __init void memory_setup(void)
510 {
511 #ifdef CONFIG_MTD_UCLINUX
512 unsigned long mtd_phys = 0;
513 #endif
514
515 _rambase = (unsigned long)_stext;
516 _ramstart = (unsigned long)_end;
517
518 if (DMA_UNCACHED_REGION > (_ramend - _ramstart)) {
519 console_init();
520 panic("DMA region exceeds memory limit: %lu.",
521 _ramend - _ramstart);
522 }
523 memory_end = _ramend - DMA_UNCACHED_REGION;
524
525 #ifdef CONFIG_MPU
526 /* Round up to multiple of 4MB */
527 memory_start = (_ramstart + 0x3fffff) & ~0x3fffff;
528 #else
529 memory_start = PAGE_ALIGN(_ramstart);
530 #endif
531
532 #if defined(CONFIG_MTD_UCLINUX)
533 /* generic memory mapped MTD driver */
534 memory_mtd_end = memory_end;
535
536 mtd_phys = _ramstart;
537 mtd_size = PAGE_ALIGN(*((unsigned long *)(mtd_phys + 8)));
538
539 # if defined(CONFIG_EXT2_FS) || defined(CONFIG_EXT3_FS)
540 if (*((unsigned short *)(mtd_phys + 0x438)) == EXT2_SUPER_MAGIC)
541 mtd_size =
542 PAGE_ALIGN(*((unsigned long *)(mtd_phys + 0x404)) << 10);
543 # endif
544
545 # if defined(CONFIG_CRAMFS)
546 if (*((unsigned long *)(mtd_phys)) == CRAMFS_MAGIC)
547 mtd_size = PAGE_ALIGN(*((unsigned long *)(mtd_phys + 0x4)));
548 # endif
549
550 # if defined(CONFIG_ROMFS_FS)
551 if (((unsigned long *)mtd_phys)[0] == ROMSB_WORD0
552 && ((unsigned long *)mtd_phys)[1] == ROMSB_WORD1)
553 mtd_size =
554 PAGE_ALIGN(be32_to_cpu(((unsigned long *)mtd_phys)[2]));
555 # if (defined(CONFIG_BFIN_EXTMEM_ICACHEABLE) && ANOMALY_05000263)
556 /* Due to a Hardware Anomaly we need to limit the size of usable
557 * instruction memory to max 60MB, 56 if HUNT_FOR_ZERO is on
558 * 05000263 - Hardware loop corrupted when taking an ICPLB exception
559 */
560 # if (defined(CONFIG_DEBUG_HUNT_FOR_ZERO))
561 if (memory_end >= 56 * 1024 * 1024)
562 memory_end = 56 * 1024 * 1024;
563 # else
564 if (memory_end >= 60 * 1024 * 1024)
565 memory_end = 60 * 1024 * 1024;
566 # endif /* CONFIG_DEBUG_HUNT_FOR_ZERO */
567 # endif /* ANOMALY_05000263 */
568 # endif /* CONFIG_ROMFS_FS */
569
570 memory_end -= mtd_size;
571
572 if (mtd_size == 0) {
573 console_init();
574 panic("Don't boot kernel without rootfs attached.");
575 }
576
577 /* Relocate MTD image to the top of memory after the uncached memory area */
578 uclinux_ram_map.phys = memory_mtd_start = memory_end;
579 uclinux_ram_map.size = mtd_size;
580 dma_memcpy((void *)uclinux_ram_map.phys, _end, uclinux_ram_map.size);
581 #endif /* CONFIG_MTD_UCLINUX */
582
583 #if (defined(CONFIG_BFIN_EXTMEM_ICACHEABLE) && ANOMALY_05000263)
584 /* Due to a Hardware Anomaly we need to limit the size of usable
585 * instruction memory to max 60MB, 56 if HUNT_FOR_ZERO is on
586 * 05000263 - Hardware loop corrupted when taking an ICPLB exception
587 */
588 #if (defined(CONFIG_DEBUG_HUNT_FOR_ZERO))
589 if (memory_end >= 56 * 1024 * 1024)
590 memory_end = 56 * 1024 * 1024;
591 #else
592 if (memory_end >= 60 * 1024 * 1024)
593 memory_end = 60 * 1024 * 1024;
594 #endif /* CONFIG_DEBUG_HUNT_FOR_ZERO */
595 printk(KERN_NOTICE "Warning: limiting memory to %liMB due to hardware anomaly 05000263\n", memory_end >> 20);
596 #endif /* ANOMALY_05000263 */
597
598 #ifdef CONFIG_MPU
599 page_mask_nelts = ((_ramend >> PAGE_SHIFT) + 31) / 32;
600 page_mask_order = get_order(3 * page_mask_nelts * sizeof(long));
601 #endif
602
603 #if !defined(CONFIG_MTD_UCLINUX)
604 /*In case there is no valid CPLB behind memory_end make sure we don't get to close*/
605 memory_end -= SIZE_4K;
606 #endif
607
608 init_mm.start_code = (unsigned long)_stext;
609 init_mm.end_code = (unsigned long)_etext;
610 init_mm.end_data = (unsigned long)_edata;
611 init_mm.brk = (unsigned long)0;
612
613 printk(KERN_INFO "Board Memory: %ldMB\n", physical_mem_end >> 20);
614 printk(KERN_INFO "Kernel Managed Memory: %ldMB\n", _ramend >> 20);
615
616 printk(KERN_INFO "Memory map:\n"
617 KERN_INFO " fixedcode = 0x%p-0x%p\n"
618 KERN_INFO " text = 0x%p-0x%p\n"
619 KERN_INFO " rodata = 0x%p-0x%p\n"
620 KERN_INFO " bss = 0x%p-0x%p\n"
621 KERN_INFO " data = 0x%p-0x%p\n"
622 KERN_INFO " stack = 0x%p-0x%p\n"
623 KERN_INFO " init = 0x%p-0x%p\n"
624 KERN_INFO " available = 0x%p-0x%p\n"
625 #ifdef CONFIG_MTD_UCLINUX
626 KERN_INFO " rootfs = 0x%p-0x%p\n"
627 #endif
628 #if DMA_UNCACHED_REGION > 0
629 KERN_INFO " DMA Zone = 0x%p-0x%p\n"
630 #endif
631 , (void *)FIXED_CODE_START, (void *)FIXED_CODE_END,
632 _stext, _etext,
633 __start_rodata, __end_rodata,
634 __bss_start, __bss_stop,
635 _sdata, _edata,
636 (void *)&init_thread_union,
637 (void *)((int)(&init_thread_union) + 0x2000),
638 __init_begin, __init_end,
639 (void *)_ramstart, (void *)memory_end
640 #ifdef CONFIG_MTD_UCLINUX
641 , (void *)memory_mtd_start, (void *)(memory_mtd_start + mtd_size)
642 #endif
643 #if DMA_UNCACHED_REGION > 0
644 , (void *)(_ramend - DMA_UNCACHED_REGION), (void *)(_ramend)
645 #endif
646 );
647 }
648
649 /*
650 * Find the lowest, highest page frame number we have available
651 */
652 void __init find_min_max_pfn(void)
653 {
654 int i;
655
656 max_pfn = 0;
657 min_low_pfn = memory_end;
658
659 for (i = 0; i < bfin_memmap.nr_map; i++) {
660 unsigned long start, end;
661 /* RAM? */
662 if (bfin_memmap.map[i].type != BFIN_MEMMAP_RAM)
663 continue;
664 start = PFN_UP(bfin_memmap.map[i].addr);
665 end = PFN_DOWN(bfin_memmap.map[i].addr +
666 bfin_memmap.map[i].size);
667 if (start >= end)
668 continue;
669 if (end > max_pfn)
670 max_pfn = end;
671 if (start < min_low_pfn)
672 min_low_pfn = start;
673 }
674 }
675
676 static __init void setup_bootmem_allocator(void)
677 {
678 int bootmap_size;
679 int i;
680 unsigned long start_pfn, end_pfn;
681 unsigned long curr_pfn, last_pfn, size;
682
683 /* mark memory between memory_start and memory_end usable */
684 add_memory_region(memory_start,
685 memory_end - memory_start, BFIN_MEMMAP_RAM);
686 /* sanity check for overlap */
687 sanitize_memmap(bfin_memmap.map, &bfin_memmap.nr_map);
688 print_memory_map("boot memmap");
689
690 /* intialize globals in linux/bootmem.h */
691 find_min_max_pfn();
692 /* pfn of the last usable page frame */
693 if (max_pfn > memory_end >> PAGE_SHIFT)
694 max_pfn = memory_end >> PAGE_SHIFT;
695 /* pfn of last page frame directly mapped by kernel */
696 max_low_pfn = max_pfn;
697 /* pfn of the first usable page frame after kernel image*/
698 if (min_low_pfn < memory_start >> PAGE_SHIFT)
699 min_low_pfn = memory_start >> PAGE_SHIFT;
700
701 start_pfn = PAGE_OFFSET >> PAGE_SHIFT;
702 end_pfn = memory_end >> PAGE_SHIFT;
703
704 /*
705 * give all the memory to the bootmap allocator, tell it to put the
706 * boot mem_map at the start of memory.
707 */
708 bootmap_size = init_bootmem_node(NODE_DATA(0),
709 memory_start >> PAGE_SHIFT, /* map goes here */
710 start_pfn, end_pfn);
711
712 /* register the memmap regions with the bootmem allocator */
713 for (i = 0; i < bfin_memmap.nr_map; i++) {
714 /*
715 * Reserve usable memory
716 */
717 if (bfin_memmap.map[i].type != BFIN_MEMMAP_RAM)
718 continue;
719 /*
720 * We are rounding up the start address of usable memory:
721 */
722 curr_pfn = PFN_UP(bfin_memmap.map[i].addr);
723 if (curr_pfn >= end_pfn)
724 continue;
725 /*
726 * ... and at the end of the usable range downwards:
727 */
728 last_pfn = PFN_DOWN(bfin_memmap.map[i].addr +
729 bfin_memmap.map[i].size);
730
731 if (last_pfn > end_pfn)
732 last_pfn = end_pfn;
733
734 /*
735 * .. finally, did all the rounding and playing
736 * around just make the area go away?
737 */
738 if (last_pfn <= curr_pfn)
739 continue;
740
741 size = last_pfn - curr_pfn;
742 free_bootmem(PFN_PHYS(curr_pfn), PFN_PHYS(size));
743 }
744
745 /* reserve memory before memory_start, including bootmap */
746 reserve_bootmem(PAGE_OFFSET,
747 memory_start + bootmap_size + PAGE_SIZE - 1 - PAGE_OFFSET,
748 BOOTMEM_DEFAULT);
749 }
750
751 #define EBSZ_TO_MEG(ebsz) \
752 ({ \
753 int meg = 0; \
754 switch (ebsz & 0xf) { \
755 case 0x1: meg = 16; break; \
756 case 0x3: meg = 32; break; \
757 case 0x5: meg = 64; break; \
758 case 0x7: meg = 128; break; \
759 case 0x9: meg = 256; break; \
760 case 0xb: meg = 512; break; \
761 } \
762 meg; \
763 })
764 static inline int __init get_mem_size(void)
765 {
766 #if defined(EBIU_SDBCTL)
767 # if defined(BF561_FAMILY)
768 int ret = 0;
769 u32 sdbctl = bfin_read_EBIU_SDBCTL();
770 ret += EBSZ_TO_MEG(sdbctl >> 0);
771 ret += EBSZ_TO_MEG(sdbctl >> 8);
772 ret += EBSZ_TO_MEG(sdbctl >> 16);
773 ret += EBSZ_TO_MEG(sdbctl >> 24);
774 return ret;
775 # else
776 return EBSZ_TO_MEG(bfin_read_EBIU_SDBCTL());
777 # endif
778 #elif defined(EBIU_DDRCTL1)
779 u32 ddrctl = bfin_read_EBIU_DDRCTL1();
780 int ret = 0;
781 switch (ddrctl & 0xc0000) {
782 case DEVSZ_64: ret = 64 / 8;
783 case DEVSZ_128: ret = 128 / 8;
784 case DEVSZ_256: ret = 256 / 8;
785 case DEVSZ_512: ret = 512 / 8;
786 }
787 switch (ddrctl & 0x30000) {
788 case DEVWD_4: ret *= 2;
789 case DEVWD_8: ret *= 2;
790 case DEVWD_16: break;
791 }
792 if ((ddrctl & 0xc000) == 0x4000)
793 ret *= 2;
794 return ret;
795 #endif
796 BUG();
797 }
798
799 void __init setup_arch(char **cmdline_p)
800 {
801 unsigned long sclk, cclk;
802
803 /* Check to make sure we are running on the right processor */
804 if (unlikely(CPUID != bfin_cpuid()))
805 printk(KERN_ERR "ERROR: Not running on ADSP-%s: unknown CPUID 0x%04x Rev 0.%d\n",
806 CPU, bfin_cpuid(), bfin_revid());
807
808 #ifdef CONFIG_DUMMY_CONSOLE
809 conswitchp = &dummy_con;
810 #endif
811
812 #if defined(CONFIG_CMDLINE_BOOL)
813 strncpy(&command_line[0], CONFIG_CMDLINE, sizeof(command_line));
814 command_line[sizeof(command_line) - 1] = 0;
815 #endif
816
817 /* Keep a copy of command line */
818 *cmdline_p = &command_line[0];
819 memcpy(boot_command_line, command_line, COMMAND_LINE_SIZE);
820 boot_command_line[COMMAND_LINE_SIZE - 1] = '\0';
821
822 memset(&bfin_memmap, 0, sizeof(bfin_memmap));
823
824 /* If the user does not specify things on the command line, use
825 * what the bootloader set things up as
826 */
827 physical_mem_end = 0;
828 parse_cmdline_early(&command_line[0]);
829
830 if (_ramend == 0)
831 _ramend = get_mem_size() * 1024 * 1024;
832
833 if (physical_mem_end == 0)
834 physical_mem_end = _ramend;
835
836 memory_setup();
837
838 /* Initialize Async memory banks */
839 bfin_write_EBIU_AMBCTL0(AMBCTL0VAL);
840 bfin_write_EBIU_AMBCTL1(AMBCTL1VAL);
841 bfin_write_EBIU_AMGCTL(AMGCTLVAL);
842 #ifdef CONFIG_EBIU_MBSCTLVAL
843 bfin_write_EBIU_MBSCTL(CONFIG_EBIU_MBSCTLVAL);
844 bfin_write_EBIU_MODE(CONFIG_EBIU_MODEVAL);
845 bfin_write_EBIU_FCTL(CONFIG_EBIU_FCTLVAL);
846 #endif
847
848 cclk = get_cclk();
849 sclk = get_sclk();
850
851 if ((ANOMALY_05000273 || ANOMALY_05000274) && (cclk >> 1) < sclk)
852 panic("ANOMALY 05000273 or 05000274: CCLK must be >= 2*SCLK");
853
854 #ifdef BF561_FAMILY
855 if (ANOMALY_05000266) {
856 bfin_read_IMDMA_D0_IRQ_STATUS();
857 bfin_read_IMDMA_D1_IRQ_STATUS();
858 }
859 #endif
860 printk(KERN_INFO "Hardware Trace ");
861 if (bfin_read_TBUFCTL() & 0x1)
862 printk("Active ");
863 else
864 printk("Off ");
865 if (bfin_read_TBUFCTL() & 0x2)
866 printk("and Enabled\n");
867 else
868 printk("and Disabled\n");
869
870 #if defined(CONFIG_CHR_DEV_FLASH) || defined(CONFIG_BLK_DEV_FLASH)
871 /* we need to initialize the Flashrom device here since we might
872 * do things with flash early on in the boot
873 */
874 flash_probe();
875 #endif
876
877 printk(KERN_INFO "Boot Mode: %i\n", bfin_read_SYSCR() & 0xF);
878
879 /* Newer parts mirror SWRST bits in SYSCR */
880 #if defined(CONFIG_BF53x) || defined(CONFIG_BF561) || \
881 defined(CONFIG_BF538) || defined(CONFIG_BF539)
882 _bfin_swrst = bfin_read_SWRST();
883 #else
884 /* Clear boot mode field */
885 _bfin_swrst = bfin_read_SYSCR() & ~0xf;
886 #endif
887
888 #ifdef CONFIG_DEBUG_DOUBLEFAULT_PRINT
889 bfin_write_SWRST(_bfin_swrst & ~DOUBLE_FAULT);
890 #endif
891 #ifdef CONFIG_DEBUG_DOUBLEFAULT_RESET
892 bfin_write_SWRST(_bfin_swrst | DOUBLE_FAULT);
893 #endif
894
895 #ifdef CONFIG_SMP
896 if (_bfin_swrst & SWRST_DBL_FAULT_A) {
897 #else
898 if (_bfin_swrst & RESET_DOUBLE) {
899 #endif
900 printk(KERN_EMERG "Recovering from DOUBLE FAULT event\n");
901 #ifdef CONFIG_DEBUG_DOUBLEFAULT
902 /* We assume the crashing kernel, and the current symbol table match */
903 printk(KERN_EMERG " While handling exception (EXCAUSE = 0x%x) at %pF\n",
904 (int)init_saved_seqstat & SEQSTAT_EXCAUSE, init_saved_retx);
905 printk(KERN_NOTICE " DCPLB_FAULT_ADDR: %pF\n", init_saved_dcplb_fault_addr);
906 printk(KERN_NOTICE " ICPLB_FAULT_ADDR: %pF\n", init_saved_icplb_fault_addr);
907 #endif
908 printk(KERN_NOTICE " The instruction at %pF caused a double exception\n",
909 init_retx);
910 } else if (_bfin_swrst & RESET_WDOG)
911 printk(KERN_INFO "Recovering from Watchdog event\n");
912 else if (_bfin_swrst & RESET_SOFTWARE)
913 printk(KERN_NOTICE "Reset caused by Software reset\n");
914
915 printk(KERN_INFO "Blackfin support (C) 2004-2009 Analog Devices, Inc.\n");
916 if (bfin_compiled_revid() == 0xffff)
917 printk(KERN_INFO "Compiled for ADSP-%s Rev any\n", CPU);
918 else if (bfin_compiled_revid() == -1)
919 printk(KERN_INFO "Compiled for ADSP-%s Rev none\n", CPU);
920 else
921 printk(KERN_INFO "Compiled for ADSP-%s Rev 0.%d\n", CPU, bfin_compiled_revid());
922
923 if (likely(CPUID == bfin_cpuid())) {
924 if (bfin_revid() != bfin_compiled_revid()) {
925 if (bfin_compiled_revid() == -1)
926 printk(KERN_ERR "Warning: Compiled for Rev none, but running on Rev %d\n",
927 bfin_revid());
928 else if (bfin_compiled_revid() != 0xffff) {
929 printk(KERN_ERR "Warning: Compiled for Rev %d, but running on Rev %d\n",
930 bfin_compiled_revid(), bfin_revid());
931 if (bfin_compiled_revid() > bfin_revid())
932 panic("Error: you are missing anomaly workarounds for this rev");
933 }
934 }
935 if (bfin_revid() < CONFIG_BF_REV_MIN || bfin_revid() > CONFIG_BF_REV_MAX)
936 printk(KERN_ERR "Warning: Unsupported Chip Revision ADSP-%s Rev 0.%d detected\n",
937 CPU, bfin_revid());
938 }
939
940 /* We can't run on BF548-0.1 due to ANOMALY 05000448 */
941 if (bfin_cpuid() == 0x27de && bfin_revid() == 1)
942 panic("You can't run on this processor due to 05000448");
943
944 printk(KERN_INFO "Blackfin Linux support by http://blackfin.uclinux.org/\n");
945
946 printk(KERN_INFO "Processor Speed: %lu MHz core clock and %lu MHz System Clock\n",
947 cclk / 1000000, sclk / 1000000);
948
949 setup_bootmem_allocator();
950
951 paging_init();
952
953 /* Copy atomic sequences to their fixed location, and sanity check that
954 these locations are the ones that we advertise to userspace. */
955 memcpy((void *)FIXED_CODE_START, &fixed_code_start,
956 FIXED_CODE_END - FIXED_CODE_START);
957 BUG_ON((char *)&sigreturn_stub - (char *)&fixed_code_start
958 != SIGRETURN_STUB - FIXED_CODE_START);
959 BUG_ON((char *)&atomic_xchg32 - (char *)&fixed_code_start
960 != ATOMIC_XCHG32 - FIXED_CODE_START);
961 BUG_ON((char *)&atomic_cas32 - (char *)&fixed_code_start
962 != ATOMIC_CAS32 - FIXED_CODE_START);
963 BUG_ON((char *)&atomic_add32 - (char *)&fixed_code_start
964 != ATOMIC_ADD32 - FIXED_CODE_START);
965 BUG_ON((char *)&atomic_sub32 - (char *)&fixed_code_start
966 != ATOMIC_SUB32 - FIXED_CODE_START);
967 BUG_ON((char *)&atomic_ior32 - (char *)&fixed_code_start
968 != ATOMIC_IOR32 - FIXED_CODE_START);
969 BUG_ON((char *)&atomic_and32 - (char *)&fixed_code_start
970 != ATOMIC_AND32 - FIXED_CODE_START);
971 BUG_ON((char *)&atomic_xor32 - (char *)&fixed_code_start
972 != ATOMIC_XOR32 - FIXED_CODE_START);
973 BUG_ON((char *)&safe_user_instruction - (char *)&fixed_code_start
974 != SAFE_USER_INSTRUCTION - FIXED_CODE_START);
975
976 #ifdef CONFIG_SMP
977 platform_init_cpus();
978 #endif
979 init_exception_vectors();
980 bfin_cache_init(); /* Initialize caches for the boot CPU */
981 }
982
983 static int __init topology_init(void)
984 {
985 unsigned int cpu;
986 /* Record CPU-private information for the boot processor. */
987 bfin_setup_cpudata(0);
988
989 for_each_possible_cpu(cpu) {
990 register_cpu(&per_cpu(cpu_data, cpu).cpu, cpu);
991 }
992
993 return 0;
994 }
995
996 subsys_initcall(topology_init);
997
998 /* Get the input clock frequency */
999 static u_long cached_clkin_hz = CONFIG_CLKIN_HZ;
1000 static u_long get_clkin_hz(void)
1001 {
1002 return cached_clkin_hz;
1003 }
1004 static int __init early_init_clkin_hz(char *buf)
1005 {
1006 cached_clkin_hz = simple_strtoul(buf, NULL, 0);
1007 #ifdef BFIN_KERNEL_CLOCK
1008 if (cached_clkin_hz != CONFIG_CLKIN_HZ)
1009 panic("cannot change clkin_hz when reprogramming clocks");
1010 #endif
1011 return 1;
1012 }
1013 early_param("clkin_hz=", early_init_clkin_hz);
1014
1015 /* Get the voltage input multiplier */
1016 static u_long get_vco(void)
1017 {
1018 static u_long cached_vco;
1019 u_long msel, pll_ctl;
1020
1021 /* The assumption here is that VCO never changes at runtime.
1022 * If, someday, we support that, then we'll have to change this.
1023 */
1024 if (cached_vco)
1025 return cached_vco;
1026
1027 pll_ctl = bfin_read_PLL_CTL();
1028 msel = (pll_ctl >> 9) & 0x3F;
1029 if (0 == msel)
1030 msel = 64;
1031
1032 cached_vco = get_clkin_hz();
1033 cached_vco >>= (1 & pll_ctl); /* DF bit */
1034 cached_vco *= msel;
1035 return cached_vco;
1036 }
1037
1038 /* Get the Core clock */
1039 u_long get_cclk(void)
1040 {
1041 static u_long cached_cclk_pll_div, cached_cclk;
1042 u_long csel, ssel;
1043
1044 if (bfin_read_PLL_STAT() & 0x1)
1045 return get_clkin_hz();
1046
1047 ssel = bfin_read_PLL_DIV();
1048 if (ssel == cached_cclk_pll_div)
1049 return cached_cclk;
1050 else
1051 cached_cclk_pll_div = ssel;
1052
1053 csel = ((ssel >> 4) & 0x03);
1054 ssel &= 0xf;
1055 if (ssel && ssel < (1 << csel)) /* SCLK > CCLK */
1056 cached_cclk = get_vco() / ssel;
1057 else
1058 cached_cclk = get_vco() >> csel;
1059 return cached_cclk;
1060 }
1061 EXPORT_SYMBOL(get_cclk);
1062
1063 /* Get the System clock */
1064 u_long get_sclk(void)
1065 {
1066 static u_long cached_sclk;
1067 u_long ssel;
1068
1069 /* The assumption here is that SCLK never changes at runtime.
1070 * If, someday, we support that, then we'll have to change this.
1071 */
1072 if (cached_sclk)
1073 return cached_sclk;
1074
1075 if (bfin_read_PLL_STAT() & 0x1)
1076 return get_clkin_hz();
1077
1078 ssel = bfin_read_PLL_DIV() & 0xf;
1079 if (0 == ssel) {
1080 printk(KERN_WARNING "Invalid System Clock\n");
1081 ssel = 1;
1082 }
1083
1084 cached_sclk = get_vco() / ssel;
1085 return cached_sclk;
1086 }
1087 EXPORT_SYMBOL(get_sclk);
1088
1089 unsigned long sclk_to_usecs(unsigned long sclk)
1090 {
1091 u64 tmp = USEC_PER_SEC * (u64)sclk;
1092 do_div(tmp, get_sclk());
1093 return tmp;
1094 }
1095 EXPORT_SYMBOL(sclk_to_usecs);
1096
1097 unsigned long usecs_to_sclk(unsigned long usecs)
1098 {
1099 u64 tmp = get_sclk() * (u64)usecs;
1100 do_div(tmp, USEC_PER_SEC);
1101 return tmp;
1102 }
1103 EXPORT_SYMBOL(usecs_to_sclk);
1104
1105 /*
1106 * Get CPU information for use by the procfs.
1107 */
1108 static int show_cpuinfo(struct seq_file *m, void *v)
1109 {
1110 char *cpu, *mmu, *fpu, *vendor, *cache;
1111 uint32_t revid;
1112 int cpu_num = *(unsigned int *)v;
1113 u_long sclk, cclk;
1114 u_int icache_size = BFIN_ICACHESIZE / 1024, dcache_size = 0, dsup_banks = 0;
1115 struct blackfin_cpudata *cpudata = &per_cpu(cpu_data, cpu_num);
1116
1117 cpu = CPU;
1118 mmu = "none";
1119 fpu = "none";
1120 revid = bfin_revid();
1121
1122 sclk = get_sclk();
1123 cclk = get_cclk();
1124
1125 switch (bfin_read_CHIPID() & CHIPID_MANUFACTURE) {
1126 case 0xca:
1127 vendor = "Analog Devices";
1128 break;
1129 default:
1130 vendor = "unknown";
1131 break;
1132 }
1133
1134 seq_printf(m, "processor\t: %d\n" "vendor_id\t: %s\n", cpu_num, vendor);
1135
1136 if (CPUID == bfin_cpuid())
1137 seq_printf(m, "cpu family\t: 0x%04x\n", CPUID);
1138 else
1139 seq_printf(m, "cpu family\t: Compiled for:0x%04x, running on:0x%04x\n",
1140 CPUID, bfin_cpuid());
1141
1142 seq_printf(m, "model name\t: ADSP-%s %lu(MHz CCLK) %lu(MHz SCLK) (%s)\n"
1143 "stepping\t: %d ",
1144 cpu, cclk/1000000, sclk/1000000,
1145 #ifdef CONFIG_MPU
1146 "mpu on",
1147 #else
1148 "mpu off",
1149 #endif
1150 revid);
1151
1152 if (bfin_revid() != bfin_compiled_revid()) {
1153 if (bfin_compiled_revid() == -1)
1154 seq_printf(m, "(Compiled for Rev none)");
1155 else if (bfin_compiled_revid() == 0xffff)
1156 seq_printf(m, "(Compiled for Rev any)");
1157 else
1158 seq_printf(m, "(Compiled for Rev %d)", bfin_compiled_revid());
1159 }
1160
1161 seq_printf(m, "\ncpu MHz\t\t: %lu.%03lu/%lu.%03lu\n",
1162 cclk/1000000, cclk%1000000,
1163 sclk/1000000, sclk%1000000);
1164 seq_printf(m, "bogomips\t: %lu.%02lu\n"
1165 "Calibration\t: %lu loops\n",
1166 (cpudata->loops_per_jiffy * HZ) / 500000,
1167 ((cpudata->loops_per_jiffy * HZ) / 5000) % 100,
1168 (cpudata->loops_per_jiffy * HZ));
1169
1170 /* Check Cache configutation */
1171 switch (cpudata->dmemctl & (1 << DMC0_P | 1 << DMC1_P)) {
1172 case ACACHE_BSRAM:
1173 cache = "dbank-A/B\t: cache/sram";
1174 dcache_size = 16;
1175 dsup_banks = 1;
1176 break;
1177 case ACACHE_BCACHE:
1178 cache = "dbank-A/B\t: cache/cache";
1179 dcache_size = 32;
1180 dsup_banks = 2;
1181 break;
1182 case ASRAM_BSRAM:
1183 cache = "dbank-A/B\t: sram/sram";
1184 dcache_size = 0;
1185 dsup_banks = 0;
1186 break;
1187 default:
1188 cache = "unknown";
1189 dcache_size = 0;
1190 dsup_banks = 0;
1191 break;
1192 }
1193
1194 /* Is it turned on? */
1195 if ((cpudata->dmemctl & (ENDCPLB | DMC_ENABLE)) != (ENDCPLB | DMC_ENABLE))
1196 dcache_size = 0;
1197
1198 if ((cpudata->imemctl & (IMC | ENICPLB)) != (IMC | ENICPLB))
1199 icache_size = 0;
1200
1201 seq_printf(m, "cache size\t: %d KB(L1 icache) "
1202 "%d KB(L1 dcache) %d KB(L2 cache)\n",
1203 icache_size, dcache_size, 0);
1204 seq_printf(m, "%s\n", cache);
1205 seq_printf(m, "external memory\t: "
1206 #if defined(CONFIG_BFIN_EXTMEM_ICACHEABLE)
1207 "cacheable"
1208 #else
1209 "uncacheable"
1210 #endif
1211 " in instruction cache\n");
1212 seq_printf(m, "external memory\t: "
1213 #if defined(CONFIG_BFIN_EXTMEM_WRITEBACK)
1214 "cacheable (write-back)"
1215 #elif defined(CONFIG_BFIN_EXTMEM_WRITETHROUGH)
1216 "cacheable (write-through)"
1217 #else
1218 "uncacheable"
1219 #endif
1220 " in data cache\n");
1221
1222 if (icache_size)
1223 seq_printf(m, "icache setup\t: %d Sub-banks/%d Ways, %d Lines/Way\n",
1224 BFIN_ISUBBANKS, BFIN_IWAYS, BFIN_ILINES);
1225 else
1226 seq_printf(m, "icache setup\t: off\n");
1227
1228 seq_printf(m,
1229 "dcache setup\t: %d Super-banks/%d Sub-banks/%d Ways, %d Lines/Way\n",
1230 dsup_banks, BFIN_DSUBBANKS, BFIN_DWAYS,
1231 BFIN_DLINES);
1232 #ifdef __ARCH_SYNC_CORE_DCACHE
1233 seq_printf(m, "SMP Dcache Flushes\t: %lu\n\n", cpudata->dcache_invld_count);
1234 #endif
1235 #ifdef __ARCH_SYNC_CORE_ICACHE
1236 seq_printf(m, "SMP Icache Flushes\t: %lu\n\n", cpudata->icache_invld_count);
1237 #endif
1238 #ifdef CONFIG_BFIN_ICACHE_LOCK
1239 switch ((cpudata->imemctl >> 3) & WAYALL_L) {
1240 case WAY0_L:
1241 seq_printf(m, "Way0 Locked-Down\n");
1242 break;
1243 case WAY1_L:
1244 seq_printf(m, "Way1 Locked-Down\n");
1245 break;
1246 case WAY01_L:
1247 seq_printf(m, "Way0,Way1 Locked-Down\n");
1248 break;
1249 case WAY2_L:
1250 seq_printf(m, "Way2 Locked-Down\n");
1251 break;
1252 case WAY02_L:
1253 seq_printf(m, "Way0,Way2 Locked-Down\n");
1254 break;
1255 case WAY12_L:
1256 seq_printf(m, "Way1,Way2 Locked-Down\n");
1257 break;
1258 case WAY012_L:
1259 seq_printf(m, "Way0,Way1 & Way2 Locked-Down\n");
1260 break;
1261 case WAY3_L:
1262 seq_printf(m, "Way3 Locked-Down\n");
1263 break;
1264 case WAY03_L:
1265 seq_printf(m, "Way0,Way3 Locked-Down\n");
1266 break;
1267 case WAY13_L:
1268 seq_printf(m, "Way1,Way3 Locked-Down\n");
1269 break;
1270 case WAY013_L:
1271 seq_printf(m, "Way 0,Way1,Way3 Locked-Down\n");
1272 break;
1273 case WAY32_L:
1274 seq_printf(m, "Way3,Way2 Locked-Down\n");
1275 break;
1276 case WAY320_L:
1277 seq_printf(m, "Way3,Way2,Way0 Locked-Down\n");
1278 break;
1279 case WAY321_L:
1280 seq_printf(m, "Way3,Way2,Way1 Locked-Down\n");
1281 break;
1282 case WAYALL_L:
1283 seq_printf(m, "All Ways are locked\n");
1284 break;
1285 default:
1286 seq_printf(m, "No Ways are locked\n");
1287 }
1288 #endif
1289
1290 if (cpu_num != num_possible_cpus() - 1)
1291 return 0;
1292
1293 if (L2_LENGTH) {
1294 seq_printf(m, "L2 SRAM\t\t: %dKB\n", L2_LENGTH/0x400);
1295 seq_printf(m, "L2 SRAM\t\t: "
1296 #if defined(CONFIG_BFIN_L2_ICACHEABLE)
1297 "cacheable"
1298 #else
1299 "uncacheable"
1300 #endif
1301 " in instruction cache\n");
1302 seq_printf(m, "L2 SRAM\t\t: "
1303 #if defined(CONFIG_BFIN_L2_WRITEBACK)
1304 "cacheable (write-back)"
1305 #elif defined(CONFIG_BFIN_L2_WRITETHROUGH)
1306 "cacheable (write-through)"
1307 #else
1308 "uncacheable"
1309 #endif
1310 " in data cache\n");
1311 }
1312 seq_printf(m, "board name\t: %s\n", bfin_board_name);
1313 seq_printf(m, "board memory\t: %ld kB (0x%p -> 0x%p)\n",
1314 physical_mem_end >> 10, (void *)0, (void *)physical_mem_end);
1315 seq_printf(m, "kernel memory\t: %d kB (0x%p -> 0x%p)\n",
1316 ((int)memory_end - (int)_stext) >> 10,
1317 _stext,
1318 (void *)memory_end);
1319 seq_printf(m, "\n");
1320
1321 return 0;
1322 }
1323
1324 static void *c_start(struct seq_file *m, loff_t *pos)
1325 {
1326 if (*pos == 0)
1327 *pos = first_cpu(cpu_online_map);
1328 if (*pos >= num_online_cpus())
1329 return NULL;
1330
1331 return pos;
1332 }
1333
1334 static void *c_next(struct seq_file *m, void *v, loff_t *pos)
1335 {
1336 *pos = next_cpu(*pos, cpu_online_map);
1337
1338 return c_start(m, pos);
1339 }
1340
1341 static void c_stop(struct seq_file *m, void *v)
1342 {
1343 }
1344
1345 const struct seq_operations cpuinfo_op = {
1346 .start = c_start,
1347 .next = c_next,
1348 .stop = c_stop,
1349 .show = show_cpuinfo,
1350 };
1351
1352 void __init cmdline_init(const char *r0)
1353 {
1354 if (r0)
1355 strncpy(command_line, r0, COMMAND_LINE_SIZE);
1356 }
Linux kernel - Deliverables
This page took 0.057992 seconds and 6 git commands to generate.