arch/blackfin/mach-bf518/include/mach/anomaly.h

   1 /*
   2  * File: include/asm-blackfin/mach-bf518/anomaly.h
   3  * Bugs: Enter bugs at http://blackfin.uclinux.org/
   4  *
   5  * Copyright (C) 2004-2008 Analog Devices Inc.
   6  * Licensed under the GPL-2 or later.
   7  */
   8
   9 /* This file shoule be up to date with:
  10  *  - ????
  11  */
  12
  13 #ifndef _MACH_ANOMALY_H_
  14 #define _MACH_ANOMALY_H_
  15
  16 /* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
  17 #define ANOMALY_05000074 (1)
  18 /* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
  19 #define ANOMALY_05000122 (1)
  20 /* False Hardware Error from an Access in the Shadow of a Conditional Branch */
  21 #define ANOMALY_05000245 (1)
  22 /* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */
  23 #define ANOMALY_05000265 (1)
  24 /* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
  25 #define ANOMALY_05000310 (1)
  26 /* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
  27 #define ANOMALY_05000366 (1)
  28 /* Lockbox SESR Firmware Does Not Save/Restore Full Context */
  29 #define ANOMALY_05000405 (1)
  30 /* Lockbox Firmware Memory Cleanup Routine Does not Clear Registers */
  31 #define ANOMALY_05000408 (1)
  32 /* Speculative Fetches Can Cause Undesired External FIFO Operations */
  33 #define ANOMALY_05000416 (1)
  34 /* TWI Fall Time (Tof) May Violate the Minimum I2C Specification */
  35 #define ANOMALY_05000421 (1)
  36 /* TWI Input Capacitance (Ci) May Violate the Maximum I2C Specification */
  37 #define ANOMALY_05000422 (1)
  38 /* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */
  39 #define ANOMALY_05000426 (1)
  40 /* Software System Reset Corrupts PLL_LOCKCNT Register */
  41 #define ANOMALY_05000430 (1)
  42 /* Incorrect Use of Stack in Lockbox Firmware During Authentication */
  43 #define ANOMALY_05000431 (1)
  44 /* Certain SIC Registers are not Reset After Soft or Core Double Fault Reset */
  45 #define ANOMALY_05000435 (1)
  46 /* PORTx_DRIVE and PORTx_HYSTERESIS Registers Read Back Incorrect Values */
  47 #define ANOMALY_05000438 (1)
  48 /* Preboot Cannot be Used to Program the PLL_DIV Register */
  49 #define ANOMALY_05000439 (1)
  50 /* bfrom_SysControl() Cannot be Used to Write the PLL_DIV Register */
  51 #define ANOMALY_05000440 (1)
  52 /* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
  53 #define ANOMALY_05000443 (1)
  54 /* Incorrect L1 Instruction Bank B Memory Map Location */
  55 #define ANOMALY_05000444 (1)
  56
  57 /* Anomalies that don't exist on this proc */
  58 #define ANOMALY_05000125 (0)
  59 #define ANOMALY_05000158 (0)
  60 #define ANOMALY_05000183 (0)
  61 #define ANOMALY_05000198 (0)
  62 #define ANOMALY_05000230 (0)
  63 #define ANOMALY_05000244 (0)
  64 #define ANOMALY_05000261 (0)
  65 #define ANOMALY_05000263 (0)
  66 #define ANOMALY_05000266 (0)
  67 #define ANOMALY_05000273 (0)
  68 #define ANOMALY_05000285 (0)
  69 #define ANOMALY_05000307 (0)
  70 #define ANOMALY_05000311 (0)
  71 #define ANOMALY_05000312 (0)
  72 #define ANOMALY_05000323 (0)
  73 #define ANOMALY_05000353 (0)
  74 #define ANOMALY_05000363 (0)
  75 #define ANOMALY_05000386 (0)
  76 #define ANOMALY_05000412 (0)
  77 #define ANOMALY_05000432 (0)
  78
  79 #endif