2 * File: include/asm-blackfin/mach-bf538/blackfin.h
14 * Bugs: Enter bugs at http://blackfin.uclinux.org/
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License as published by
18 * the Free Software Foundation; either version 2, or (at your option)
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
26 * You should have received a copy of the GNU General Public License
27 * along with this program; see the file COPYING.
28 * If not, write to the Free Software Foundation,
29 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
32 #ifndef _MACH_BLACKFIN_H_
33 #define _MACH_BLACKFIN_H_
43 #if !defined(__ASSEMBLY__)
44 #include "cdefBF538.h"
46 #if defined(CONFIG_BF539)
47 #include "cdefBF539.h"
51 /* UART_IIR Register */
52 #define STATUS(x) ((x << 1) & 0x06)
53 #define STATUS_P1 0x02
54 #define STATUS_P0 0x01
56 #define BFIN_UART_NR_PORTS 3
58 #define OFFSET_THR 0x00 /* Transmit Holding register */
59 #define OFFSET_RBR 0x00 /* Receive Buffer register */
60 #define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */
61 #define OFFSET_IER 0x04 /* Interrupt Enable Register */
62 #define OFFSET_DLH 0x04 /* Divisor Latch (High-Byte) */
63 #define OFFSET_IIR 0x08 /* Interrupt Identification Register */
64 #define OFFSET_LCR 0x0C /* Line Control Register */
65 #define OFFSET_MCR 0x10 /* Modem Control Register */
66 #define OFFSET_LSR 0x14 /* Line Status Register */
67 #define OFFSET_MSR 0x18 /* Modem Status Register */
68 #define OFFSET_SCR 0x1C /* SCR Scratch Register */
69 #define OFFSET_GCTL 0x24 /* Global Control Register */
72 #define bfin_read_STOPCK_OFF() bfin_read_STOPCK()
73 #define bfin_write_STOPCK_OFF(val) bfin_write_STOPCK(val)
74 #define STOPCK_OFF STOPCK
77 #define CCLK_DIV1 CSEL_DIV1 /* CCLK = VCO / 1 */
78 #define CCLK_DIV2 CSEL_DIV2 /* CCLK = VCO / 2 */
79 #define CCLK_DIV4 CSEL_DIV4 /* CCLK = VCO / 4 */
80 #define CCLK_DIV8 CSEL_DIV8 /* CCLK = VCO / 8 */
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