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[deliverable/linux.git] / arch / blackfin / mach-bf548 / boards / ezkit.c
1 /*
2 * Copyright 2004-2009 Analog Devices Inc.
3 * 2005 National ICT Australia (NICTA)
4 * Aidan Williams <aidan@nicta.com.au>
5 *
6 * Licensed under the GPL-2 or later.
7 */
8
9 #include <linux/device.h>
10 #include <linux/platform_device.h>
11 #include <linux/mtd/mtd.h>
12 #include <linux/mtd/partitions.h>
13 #include <linux/mtd/physmap.h>
14 #include <linux/spi/spi.h>
15 #include <linux/spi/flash.h>
16 #include <linux/irq.h>
17 #include <linux/i2c.h>
18 #include <linux/interrupt.h>
19 #include <linux/usb/musb.h>
20 #include <linux/pinctrl/machine.h>
21 #include <linux/pinctrl/pinconf-generic.h>
22 #include <linux/platform_data/pinctrl-adi2.h>
23 #include <asm/bfin5xx_spi.h>
24 #include <asm/dma.h>
25 #include <asm/gpio.h>
26 #include <asm/nand.h>
27 #include <asm/dpmc.h>
28 #include <asm/bfin_sport.h>
29 #include <asm/portmux.h>
30 #include <asm/bfin_sdh.h>
31 #include <mach/bf54x_keys.h>
32 #include <linux/input.h>
33 #include <linux/spi/ad7877.h>
34
35 /*
36 * Name the Board for the /proc/cpuinfo
37 */
38 const char bfin_board_name[] = "ADI BF548-EZKIT";
39
40 /*
41 * Driver needs to know address, irq and flag pin.
42 */
43
44 #if IS_ENABLED(CONFIG_USB_ISP1760_HCD)
45 #include <linux/usb/isp1760.h>
46 static struct resource bfin_isp1760_resources[] = {
47 [0] = {
48 .start = 0x2C0C0000,
49 .end = 0x2C0C0000 + 0xfffff,
50 .flags = IORESOURCE_MEM,
51 },
52 [1] = {
53 .start = IRQ_PG7,
54 .end = IRQ_PG7,
55 .flags = IORESOURCE_IRQ,
56 },
57 };
58
59 static struct isp1760_platform_data isp1760_priv = {
60 .is_isp1761 = 0,
61 .bus_width_16 = 1,
62 .port1_otg = 0,
63 .analog_oc = 0,
64 .dack_polarity_high = 0,
65 .dreq_polarity_high = 0,
66 };
67
68 static struct platform_device bfin_isp1760_device = {
69 .name = "isp1760",
70 .id = 0,
71 .dev = {
72 .platform_data = &isp1760_priv,
73 },
74 .num_resources = ARRAY_SIZE(bfin_isp1760_resources),
75 .resource = bfin_isp1760_resources,
76 };
77 #endif
78
79 #if IS_ENABLED(CONFIG_FB_BF54X_LQ043)
80
81 #include <mach/bf54x-lq043.h>
82
83 static struct bfin_bf54xfb_mach_info bf54x_lq043_data = {
84 .width = 95,
85 .height = 54,
86 .xres = {480, 480, 480},
87 .yres = {272, 272, 272},
88 .bpp = {24, 24, 24},
89 .disp = GPIO_PE3,
90 };
91
92 static struct resource bf54x_lq043_resources[] = {
93 {
94 .start = IRQ_EPPI0_ERR,
95 .end = IRQ_EPPI0_ERR,
96 .flags = IORESOURCE_IRQ,
97 },
98 };
99
100 static struct platform_device bf54x_lq043_device = {
101 .name = "bf54x-lq043",
102 .id = -1,
103 .num_resources = ARRAY_SIZE(bf54x_lq043_resources),
104 .resource = bf54x_lq043_resources,
105 .dev = {
106 .platform_data = &bf54x_lq043_data,
107 },
108 };
109 #endif
110
111 #if IS_ENABLED(CONFIG_KEYBOARD_BFIN)
112 static const unsigned int bf548_keymap[] = {
113 KEYVAL(0, 0, KEY_ENTER),
114 KEYVAL(0, 1, KEY_HELP),
115 KEYVAL(0, 2, KEY_0),
116 KEYVAL(0, 3, KEY_BACKSPACE),
117 KEYVAL(1, 0, KEY_TAB),
118 KEYVAL(1, 1, KEY_9),
119 KEYVAL(1, 2, KEY_8),
120 KEYVAL(1, 3, KEY_7),
121 KEYVAL(2, 0, KEY_DOWN),
122 KEYVAL(2, 1, KEY_6),
123 KEYVAL(2, 2, KEY_5),
124 KEYVAL(2, 3, KEY_4),
125 KEYVAL(3, 0, KEY_UP),
126 KEYVAL(3, 1, KEY_3),
127 KEYVAL(3, 2, KEY_2),
128 KEYVAL(3, 3, KEY_1),
129 };
130
131 static struct bfin_kpad_platform_data bf54x_kpad_data = {
132 .rows = 4,
133 .cols = 4,
134 .keymap = bf548_keymap,
135 .keymapsize = ARRAY_SIZE(bf548_keymap),
136 .repeat = 0,
137 .debounce_time = 5000, /* ns (5ms) */
138 .coldrive_time = 1000, /* ns (1ms) */
139 .keyup_test_interval = 50, /* ms (50ms) */
140 };
141
142 static struct resource bf54x_kpad_resources[] = {
143 {
144 .start = IRQ_KEY,
145 .end = IRQ_KEY,
146 .flags = IORESOURCE_IRQ,
147 },
148 };
149
150 static struct platform_device bf54x_kpad_device = {
151 .name = "bf54x-keys",
152 .id = -1,
153 .num_resources = ARRAY_SIZE(bf54x_kpad_resources),
154 .resource = bf54x_kpad_resources,
155 .dev = {
156 .platform_data = &bf54x_kpad_data,
157 },
158 };
159 #endif
160
161 #if IS_ENABLED(CONFIG_INPUT_BFIN_ROTARY)
162 #include <asm/bfin_rotary.h>
163
164 static struct bfin_rotary_platform_data bfin_rotary_data = {
165 /*.rotary_up_key = KEY_UP,*/
166 /*.rotary_down_key = KEY_DOWN,*/
167 .rotary_rel_code = REL_WHEEL,
168 .rotary_button_key = KEY_ENTER,
169 .debounce = 10, /* 0..17 */
170 .mode = ROT_QUAD_ENC | ROT_DEBE,
171 .pm_wakeup = 1,
172 };
173
174 static struct resource bfin_rotary_resources[] = {
175 {
176 .start = IRQ_CNT,
177 .end = IRQ_CNT,
178 .flags = IORESOURCE_IRQ,
179 },
180 };
181
182 static struct platform_device bfin_rotary_device = {
183 .name = "bfin-rotary",
184 .id = -1,
185 .num_resources = ARRAY_SIZE(bfin_rotary_resources),
186 .resource = bfin_rotary_resources,
187 .dev = {
188 .platform_data = &bfin_rotary_data,
189 },
190 };
191 #endif
192
193 #if IS_ENABLED(CONFIG_INPUT_ADXL34X)
194 #include <linux/input/adxl34x.h>
195 static const struct adxl34x_platform_data adxl34x_info = {
196 .x_axis_offset = 0,
197 .y_axis_offset = 0,
198 .z_axis_offset = 0,
199 .tap_threshold = 0x31,
200 .tap_duration = 0x10,
201 .tap_latency = 0x60,
202 .tap_window = 0xF0,
203 .tap_axis_control = ADXL_TAP_X_EN | ADXL_TAP_Y_EN | ADXL_TAP_Z_EN,
204 .act_axis_control = 0xFF,
205 .activity_threshold = 5,
206 .inactivity_threshold = 3,
207 .inactivity_time = 4,
208 .free_fall_threshold = 0x7,
209 .free_fall_time = 0x20,
210 .data_rate = 0x8,
211 .data_range = ADXL_FULL_RES,
212
213 .ev_type = EV_ABS,
214 .ev_code_x = ABS_X, /* EV_REL */
215 .ev_code_y = ABS_Y, /* EV_REL */
216 .ev_code_z = ABS_Z, /* EV_REL */
217
218 .ev_code_tap = {BTN_TOUCH, BTN_TOUCH, BTN_TOUCH}, /* EV_KEY x,y,z */
219
220 /* .ev_code_ff = KEY_F,*/ /* EV_KEY */
221 /* .ev_code_act_inactivity = KEY_A,*/ /* EV_KEY */
222 .power_mode = ADXL_AUTO_SLEEP | ADXL_LINK,
223 .fifo_mode = ADXL_FIFO_STREAM,
224 .orientation_enable = ADXL_EN_ORIENTATION_3D,
225 .deadzone_angle = ADXL_DEADZONE_ANGLE_10p8,
226 .divisor_length = ADXL_LP_FILTER_DIVISOR_16,
227 /* EV_KEY {+Z, +Y, +X, -X, -Y, -Z} */
228 .ev_codes_orient_3d = {BTN_Z, BTN_Y, BTN_X, BTN_A, BTN_B, BTN_C},
229 };
230 #endif
231
232 #if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
233 static struct platform_device rtc_device = {
234 .name = "rtc-bfin",
235 .id = -1,
236 };
237 #endif
238
239 #if IS_ENABLED(CONFIG_SERIAL_BFIN)
240 #ifdef CONFIG_SERIAL_BFIN_UART0
241 static struct resource bfin_uart0_resources[] = {
242 {
243 .start = UART0_DLL,
244 .end = UART0_RBR+2,
245 .flags = IORESOURCE_MEM,
246 },
247 #ifdef CONFIG_EARLY_PRINTK
248 {
249 .start = PORTE_FER,
250 .end = PORTE_FER+2,
251 .flags = IORESOURCE_REG,
252 },
253 #endif
254 {
255 .start = IRQ_UART0_TX,
256 .end = IRQ_UART0_TX,
257 .flags = IORESOURCE_IRQ,
258 },
259 {
260 .start = IRQ_UART0_RX,
261 .end = IRQ_UART0_RX,
262 .flags = IORESOURCE_IRQ,
263 },
264 {
265 .start = IRQ_UART0_ERROR,
266 .end = IRQ_UART0_ERROR,
267 .flags = IORESOURCE_IRQ,
268 },
269 {
270 .start = CH_UART0_TX,
271 .end = CH_UART0_TX,
272 .flags = IORESOURCE_DMA,
273 },
274 {
275 .start = CH_UART0_RX,
276 .end = CH_UART0_RX,
277 .flags = IORESOURCE_DMA,
278 },
279 };
280
281 static unsigned short bfin_uart0_peripherals[] = {
282 P_UART0_TX, P_UART0_RX, 0
283 };
284
285 static struct platform_device bfin_uart0_device = {
286 .name = "bfin-uart",
287 .id = 0,
288 .num_resources = ARRAY_SIZE(bfin_uart0_resources),
289 .resource = bfin_uart0_resources,
290 .dev = {
291 .platform_data = &bfin_uart0_peripherals, /* Passed to driver */
292 },
293 };
294 #endif
295 #ifdef CONFIG_SERIAL_BFIN_UART1
296 static struct resource bfin_uart1_resources[] = {
297 {
298 .start = UART1_DLL,
299 .end = UART1_RBR+2,
300 .flags = IORESOURCE_MEM,
301 },
302 #ifdef CONFIG_EARLY_PRINTK
303 {
304 .start = PORTH_FER,
305 .end = PORTH_FER+2,
306 .flags = IORESOURCE_REG,
307 },
308 #endif
309 {
310 .start = IRQ_UART1_TX,
311 .end = IRQ_UART1_TX,
312 .flags = IORESOURCE_IRQ,
313 },
314 {
315 .start = IRQ_UART1_RX,
316 .end = IRQ_UART1_RX,
317 .flags = IORESOURCE_IRQ,
318 },
319 {
320 .start = IRQ_UART1_ERROR,
321 .end = IRQ_UART1_ERROR,
322 .flags = IORESOURCE_IRQ,
323 },
324 {
325 .start = CH_UART1_TX,
326 .end = CH_UART1_TX,
327 .flags = IORESOURCE_DMA,
328 },
329 {
330 .start = CH_UART1_RX,
331 .end = CH_UART1_RX,
332 .flags = IORESOURCE_DMA,
333 },
334 #ifdef CONFIG_BFIN_UART1_CTSRTS
335 { /* CTS pin -- 0 means not supported */
336 .start = GPIO_PE10,
337 .end = GPIO_PE10,
338 .flags = IORESOURCE_IO,
339 },
340 { /* RTS pin -- 0 means not supported */
341 .start = GPIO_PE9,
342 .end = GPIO_PE9,
343 .flags = IORESOURCE_IO,
344 },
345 #endif
346 };
347
348 static unsigned short bfin_uart1_peripherals[] = {
349 P_UART1_TX, P_UART1_RX,
350 #ifdef CONFIG_BFIN_UART1_CTSRTS
351 P_UART1_RTS, P_UART1_CTS,
352 #endif
353 0
354 };
355
356 static struct platform_device bfin_uart1_device = {
357 .name = "bfin-uart",
358 .id = 1,
359 .num_resources = ARRAY_SIZE(bfin_uart1_resources),
360 .resource = bfin_uart1_resources,
361 .dev = {
362 .platform_data = &bfin_uart1_peripherals, /* Passed to driver */
363 },
364 };
365 #endif
366 #ifdef CONFIG_SERIAL_BFIN_UART2
367 static struct resource bfin_uart2_resources[] = {
368 {
369 .start = UART2_DLL,
370 .end = UART2_RBR+2,
371 .flags = IORESOURCE_MEM,
372 },
373 #ifdef CONFIG_EARLY_PRINTK
374 {
375 .start = PORTB_FER,
376 .end = PORTB_FER+2,
377 .flags = IORESOURCE_REG,
378 },
379 #endif
380 {
381 .start = IRQ_UART2_TX,
382 .end = IRQ_UART2_TX,
383 .flags = IORESOURCE_IRQ,
384 },
385 {
386 .start = IRQ_UART2_RX,
387 .end = IRQ_UART2_RX,
388 .flags = IORESOURCE_IRQ,
389 },
390 {
391 .start = IRQ_UART2_ERROR,
392 .end = IRQ_UART2_ERROR,
393 .flags = IORESOURCE_IRQ,
394 },
395 {
396 .start = CH_UART2_TX,
397 .end = CH_UART2_TX,
398 .flags = IORESOURCE_DMA,
399 },
400 {
401 .start = CH_UART2_RX,
402 .end = CH_UART2_RX,
403 .flags = IORESOURCE_DMA,
404 },
405 };
406
407 static unsigned short bfin_uart2_peripherals[] = {
408 P_UART2_TX, P_UART2_RX, 0
409 };
410
411 static struct platform_device bfin_uart2_device = {
412 .name = "bfin-uart",
413 .id = 2,
414 .num_resources = ARRAY_SIZE(bfin_uart2_resources),
415 .resource = bfin_uart2_resources,
416 .dev = {
417 .platform_data = &bfin_uart2_peripherals, /* Passed to driver */
418 },
419 };
420 #endif
421 #ifdef CONFIG_SERIAL_BFIN_UART3
422 static struct resource bfin_uart3_resources[] = {
423 {
424 .start = UART3_DLL,
425 .end = UART3_RBR+2,
426 .flags = IORESOURCE_MEM,
427 },
428 #ifdef CONFIG_EARLY_PRINTK
429 {
430 .start = PORTB_FER,
431 .end = PORTB_FER+2,
432 .flags = IORESOURCE_REG,
433 },
434 #endif
435 {
436 .start = IRQ_UART3_TX,
437 .end = IRQ_UART3_TX,
438 .flags = IORESOURCE_IRQ,
439 },
440 {
441 .start = IRQ_UART3_RX,
442 .end = IRQ_UART3_RX,
443 .flags = IORESOURCE_IRQ,
444 },
445 {
446 .start = IRQ_UART3_ERROR,
447 .end = IRQ_UART3_ERROR,
448 .flags = IORESOURCE_IRQ,
449 },
450 {
451 .start = CH_UART3_TX,
452 .end = CH_UART3_TX,
453 .flags = IORESOURCE_DMA,
454 },
455 {
456 .start = CH_UART3_RX,
457 .end = CH_UART3_RX,
458 .flags = IORESOURCE_DMA,
459 },
460 #ifdef CONFIG_BFIN_UART3_CTSRTS
461 { /* CTS pin -- 0 means not supported */
462 .start = GPIO_PB3,
463 .end = GPIO_PB3,
464 .flags = IORESOURCE_IO,
465 },
466 { /* RTS pin -- 0 means not supported */
467 .start = GPIO_PB2,
468 .end = GPIO_PB2,
469 .flags = IORESOURCE_IO,
470 },
471 #endif
472 };
473
474 static unsigned short bfin_uart3_peripherals[] = {
475 P_UART3_TX, P_UART3_RX,
476 #ifdef CONFIG_BFIN_UART3_CTSRTS
477 P_UART3_RTS, P_UART3_CTS,
478 #endif
479 0
480 };
481
482 static struct platform_device bfin_uart3_device = {
483 .name = "bfin-uart",
484 .id = 3,
485 .num_resources = ARRAY_SIZE(bfin_uart3_resources),
486 .resource = bfin_uart3_resources,
487 .dev = {
488 .platform_data = &bfin_uart3_peripherals, /* Passed to driver */
489 },
490 };
491 #endif
492 #endif
493
494 #if IS_ENABLED(CONFIG_BFIN_SIR)
495 #ifdef CONFIG_BFIN_SIR0
496 static struct resource bfin_sir0_resources[] = {
497 {
498 .start = 0xFFC00400,
499 .end = 0xFFC004FF,
500 .flags = IORESOURCE_MEM,
501 },
502 {
503 .start = IRQ_UART0_RX,
504 .end = IRQ_UART0_RX+1,
505 .flags = IORESOURCE_IRQ,
506 },
507 {
508 .start = CH_UART0_RX,
509 .end = CH_UART0_RX+1,
510 .flags = IORESOURCE_DMA,
511 },
512 };
513 static struct platform_device bfin_sir0_device = {
514 .name = "bfin_sir",
515 .id = 0,
516 .num_resources = ARRAY_SIZE(bfin_sir0_resources),
517 .resource = bfin_sir0_resources,
518 };
519 #endif
520 #ifdef CONFIG_BFIN_SIR1
521 static struct resource bfin_sir1_resources[] = {
522 {
523 .start = 0xFFC02000,
524 .end = 0xFFC020FF,
525 .flags = IORESOURCE_MEM,
526 },
527 {
528 .start = IRQ_UART1_RX,
529 .end = IRQ_UART1_RX+1,
530 .flags = IORESOURCE_IRQ,
531 },
532 {
533 .start = CH_UART1_RX,
534 .end = CH_UART1_RX+1,
535 .flags = IORESOURCE_DMA,
536 },
537 };
538 static struct platform_device bfin_sir1_device = {
539 .name = "bfin_sir",
540 .id = 1,
541 .num_resources = ARRAY_SIZE(bfin_sir1_resources),
542 .resource = bfin_sir1_resources,
543 };
544 #endif
545 #ifdef CONFIG_BFIN_SIR2
546 static struct resource bfin_sir2_resources[] = {
547 {
548 .start = 0xFFC02100,
549 .end = 0xFFC021FF,
550 .flags = IORESOURCE_MEM,
551 },
552 {
553 .start = IRQ_UART2_RX,
554 .end = IRQ_UART2_RX+1,
555 .flags = IORESOURCE_IRQ,
556 },
557 {
558 .start = CH_UART2_RX,
559 .end = CH_UART2_RX+1,
560 .flags = IORESOURCE_DMA,
561 },
562 };
563 static struct platform_device bfin_sir2_device = {
564 .name = "bfin_sir",
565 .id = 2,
566 .num_resources = ARRAY_SIZE(bfin_sir2_resources),
567 .resource = bfin_sir2_resources,
568 };
569 #endif
570 #ifdef CONFIG_BFIN_SIR3
571 static struct resource bfin_sir3_resources[] = {
572 {
573 .start = 0xFFC03100,
574 .end = 0xFFC031FF,
575 .flags = IORESOURCE_MEM,
576 },
577 {
578 .start = IRQ_UART3_RX,
579 .end = IRQ_UART3_RX+1,
580 .flags = IORESOURCE_IRQ,
581 },
582 {
583 .start = CH_UART3_RX,
584 .end = CH_UART3_RX+1,
585 .flags = IORESOURCE_DMA,
586 },
587 };
588 static struct platform_device bfin_sir3_device = {
589 .name = "bfin_sir",
590 .id = 3,
591 .num_resources = ARRAY_SIZE(bfin_sir3_resources),
592 .resource = bfin_sir3_resources,
593 };
594 #endif
595 #endif
596
597 #if IS_ENABLED(CONFIG_SMSC911X)
598 #include <linux/smsc911x.h>
599
600 static struct resource smsc911x_resources[] = {
601 {
602 .name = "smsc911x-memory",
603 .start = 0x24000000,
604 .end = 0x24000000 + 0xFF,
605 .flags = IORESOURCE_MEM,
606 },
607 {
608 .start = IRQ_PE8,
609 .end = IRQ_PE8,
610 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
611 },
612 };
613
614 static struct smsc911x_platform_config smsc911x_config = {
615 .flags = SMSC911X_USE_32BIT,
616 .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
617 .irq_type = SMSC911X_IRQ_TYPE_OPEN_DRAIN,
618 .phy_interface = PHY_INTERFACE_MODE_MII,
619 };
620
621 static struct platform_device smsc911x_device = {
622 .name = "smsc911x",
623 .id = 0,
624 .num_resources = ARRAY_SIZE(smsc911x_resources),
625 .resource = smsc911x_resources,
626 .dev = {
627 .platform_data = &smsc911x_config,
628 },
629 };
630 #endif
631
632 #if IS_ENABLED(CONFIG_USB_MUSB_HDRC)
633 static struct resource musb_resources[] = {
634 [0] = {
635 .start = 0xFFC03C00,
636 .end = 0xFFC040FF,
637 .flags = IORESOURCE_MEM,
638 },
639 [1] = { /* general IRQ */
640 .start = IRQ_USB_INT0,
641 .end = IRQ_USB_INT0,
642 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
643 .name = "mc"
644 },
645 [2] = { /* DMA IRQ */
646 .start = IRQ_USB_DMA,
647 .end = IRQ_USB_DMA,
648 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
649 .name = "dma"
650 },
651 };
652
653 static struct musb_hdrc_config musb_config = {
654 .multipoint = 0,
655 .dyn_fifo = 0,
656 .soft_con = 1,
657 .dma = 1,
658 .num_eps = 8,
659 .dma_channels = 8,
660 .gpio_vrsel = GPIO_PE7,
661 /* Some custom boards need to be active low, just set it to "0"
662 * if it is the case.
663 */
664 .gpio_vrsel_active = 1,
665 .clkin = 24, /* musb CLKIN in MHZ */
666 };
667
668 static struct musb_hdrc_platform_data musb_plat = {
669 #if defined(CONFIG_USB_MUSB_HDRC) && defined(CONFIG_USB_GADGET_MUSB_HDRC)
670 .mode = MUSB_OTG,
671 #elif defined(CONFIG_USB_MUSB_HDRC)
672 .mode = MUSB_HOST,
673 #elif defined(CONFIG_USB_GADGET_MUSB_HDRC)
674 .mode = MUSB_PERIPHERAL,
675 #endif
676 .config = &musb_config,
677 };
678
679 static u64 musb_dmamask = ~(u32)0;
680
681 static struct platform_device musb_device = {
682 .name = "musb-blackfin",
683 .id = 0,
684 .dev = {
685 .dma_mask = &musb_dmamask,
686 .coherent_dma_mask = 0xffffffff,
687 .platform_data = &musb_plat,
688 },
689 .num_resources = ARRAY_SIZE(musb_resources),
690 .resource = musb_resources,
691 };
692 #endif
693
694 #if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
695 #ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
696 static struct resource bfin_sport0_uart_resources[] = {
697 {
698 .start = SPORT0_TCR1,
699 .end = SPORT0_MRCS3+4,
700 .flags = IORESOURCE_MEM,
701 },
702 {
703 .start = IRQ_SPORT0_RX,
704 .end = IRQ_SPORT0_RX+1,
705 .flags = IORESOURCE_IRQ,
706 },
707 {
708 .start = IRQ_SPORT0_ERROR,
709 .end = IRQ_SPORT0_ERROR,
710 .flags = IORESOURCE_IRQ,
711 },
712 };
713
714 static unsigned short bfin_sport0_peripherals[] = {
715 P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
716 P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
717 };
718
719 static struct platform_device bfin_sport0_uart_device = {
720 .name = "bfin-sport-uart",
721 .id = 0,
722 .num_resources = ARRAY_SIZE(bfin_sport0_uart_resources),
723 .resource = bfin_sport0_uart_resources,
724 .dev = {
725 .platform_data = &bfin_sport0_peripherals, /* Passed to driver */
726 },
727 };
728 #endif
729 #ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
730 static struct resource bfin_sport1_uart_resources[] = {
731 {
732 .start = SPORT1_TCR1,
733 .end = SPORT1_MRCS3+4,
734 .flags = IORESOURCE_MEM,
735 },
736 {
737 .start = IRQ_SPORT1_RX,
738 .end = IRQ_SPORT1_RX+1,
739 .flags = IORESOURCE_IRQ,
740 },
741 {
742 .start = IRQ_SPORT1_ERROR,
743 .end = IRQ_SPORT1_ERROR,
744 .flags = IORESOURCE_IRQ,
745 },
746 };
747
748 static unsigned short bfin_sport1_peripherals[] = {
749 P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
750 P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
751 };
752
753 static struct platform_device bfin_sport1_uart_device = {
754 .name = "bfin-sport-uart",
755 .id = 1,
756 .num_resources = ARRAY_SIZE(bfin_sport1_uart_resources),
757 .resource = bfin_sport1_uart_resources,
758 .dev = {
759 .platform_data = &bfin_sport1_peripherals, /* Passed to driver */
760 },
761 };
762 #endif
763 #ifdef CONFIG_SERIAL_BFIN_SPORT2_UART
764 static struct resource bfin_sport2_uart_resources[] = {
765 {
766 .start = SPORT2_TCR1,
767 .end = SPORT2_MRCS3+4,
768 .flags = IORESOURCE_MEM,
769 },
770 {
771 .start = IRQ_SPORT2_RX,
772 .end = IRQ_SPORT2_RX+1,
773 .flags = IORESOURCE_IRQ,
774 },
775 {
776 .start = IRQ_SPORT2_ERROR,
777 .end = IRQ_SPORT2_ERROR,
778 .flags = IORESOURCE_IRQ,
779 },
780 };
781
782 static unsigned short bfin_sport2_peripherals[] = {
783 P_SPORT2_TFS, P_SPORT2_DTPRI, P_SPORT2_TSCLK, P_SPORT2_RFS,
784 P_SPORT2_DRPRI, P_SPORT2_RSCLK, P_SPORT2_DRSEC, P_SPORT2_DTSEC, 0
785 };
786
787 static struct platform_device bfin_sport2_uart_device = {
788 .name = "bfin-sport-uart",
789 .id = 2,
790 .num_resources = ARRAY_SIZE(bfin_sport2_uart_resources),
791 .resource = bfin_sport2_uart_resources,
792 .dev = {
793 .platform_data = &bfin_sport2_peripherals, /* Passed to driver */
794 },
795 };
796 #endif
797 #ifdef CONFIG_SERIAL_BFIN_SPORT3_UART
798 static struct resource bfin_sport3_uart_resources[] = {
799 {
800 .start = SPORT3_TCR1,
801 .end = SPORT3_MRCS3+4,
802 .flags = IORESOURCE_MEM,
803 },
804 {
805 .start = IRQ_SPORT3_RX,
806 .end = IRQ_SPORT3_RX+1,
807 .flags = IORESOURCE_IRQ,
808 },
809 {
810 .start = IRQ_SPORT3_ERROR,
811 .end = IRQ_SPORT3_ERROR,
812 .flags = IORESOURCE_IRQ,
813 },
814 };
815
816 static unsigned short bfin_sport3_peripherals[] = {
817 P_SPORT3_TFS, P_SPORT3_DTPRI, P_SPORT3_TSCLK, P_SPORT3_RFS,
818 P_SPORT3_DRPRI, P_SPORT3_RSCLK, P_SPORT3_DRSEC, P_SPORT3_DTSEC, 0
819 };
820
821 static struct platform_device bfin_sport3_uart_device = {
822 .name = "bfin-sport-uart",
823 .id = 3,
824 .num_resources = ARRAY_SIZE(bfin_sport3_uart_resources),
825 .resource = bfin_sport3_uart_resources,
826 .dev = {
827 .platform_data = &bfin_sport3_peripherals, /* Passed to driver */
828 },
829 };
830 #endif
831 #endif
832
833 #if IS_ENABLED(CONFIG_CAN_BFIN)
834
835 static unsigned short bfin_can0_peripherals[] = {
836 P_CAN0_RX, P_CAN0_TX, 0
837 };
838
839 static struct resource bfin_can0_resources[] = {
840 {
841 .start = 0xFFC02A00,
842 .end = 0xFFC02FFF,
843 .flags = IORESOURCE_MEM,
844 },
845 {
846 .start = IRQ_CAN0_RX,
847 .end = IRQ_CAN0_RX,
848 .flags = IORESOURCE_IRQ,
849 },
850 {
851 .start = IRQ_CAN0_TX,
852 .end = IRQ_CAN0_TX,
853 .flags = IORESOURCE_IRQ,
854 },
855 {
856 .start = IRQ_CAN0_ERROR,
857 .end = IRQ_CAN0_ERROR,
858 .flags = IORESOURCE_IRQ,
859 },
860 };
861
862 static struct platform_device bfin_can0_device = {
863 .name = "bfin_can",
864 .id = 0,
865 .num_resources = ARRAY_SIZE(bfin_can0_resources),
866 .resource = bfin_can0_resources,
867 .dev = {
868 .platform_data = &bfin_can0_peripherals, /* Passed to driver */
869 },
870 };
871
872 static unsigned short bfin_can1_peripherals[] = {
873 P_CAN1_RX, P_CAN1_TX, 0
874 };
875
876 static struct resource bfin_can1_resources[] = {
877 {
878 .start = 0xFFC03200,
879 .end = 0xFFC037FF,
880 .flags = IORESOURCE_MEM,
881 },
882 {
883 .start = IRQ_CAN1_RX,
884 .end = IRQ_CAN1_RX,
885 .flags = IORESOURCE_IRQ,
886 },
887 {
888 .start = IRQ_CAN1_TX,
889 .end = IRQ_CAN1_TX,
890 .flags = IORESOURCE_IRQ,
891 },
892 {
893 .start = IRQ_CAN1_ERROR,
894 .end = IRQ_CAN1_ERROR,
895 .flags = IORESOURCE_IRQ,
896 },
897 };
898
899 static struct platform_device bfin_can1_device = {
900 .name = "bfin_can",
901 .id = 1,
902 .num_resources = ARRAY_SIZE(bfin_can1_resources),
903 .resource = bfin_can1_resources,
904 .dev = {
905 .platform_data = &bfin_can1_peripherals, /* Passed to driver */
906 },
907 };
908
909 #endif
910
911 #if IS_ENABLED(CONFIG_PATA_BF54X)
912 static struct resource bfin_atapi_resources[] = {
913 {
914 .start = 0xFFC03800,
915 .end = 0xFFC0386F,
916 .flags = IORESOURCE_MEM,
917 },
918 {
919 .start = IRQ_ATAPI_ERR,
920 .end = IRQ_ATAPI_ERR,
921 .flags = IORESOURCE_IRQ,
922 },
923 };
924
925 static struct platform_device bfin_atapi_device = {
926 .name = "pata-bf54x",
927 .id = -1,
928 .num_resources = ARRAY_SIZE(bfin_atapi_resources),
929 .resource = bfin_atapi_resources,
930 };
931 #endif
932
933 #if IS_ENABLED(CONFIG_MTD_NAND_BF5XX)
934 static struct mtd_partition partition_info[] = {
935 {
936 .name = "bootloader(nand)",
937 .offset = 0,
938 .size = 0x80000,
939 }, {
940 .name = "linux kernel(nand)",
941 .offset = MTDPART_OFS_APPEND,
942 .size = 4 * 1024 * 1024,
943 },
944 {
945 .name = "file system(nand)",
946 .offset = MTDPART_OFS_APPEND,
947 .size = MTDPART_SIZ_FULL,
948 },
949 };
950
951 static struct bf5xx_nand_platform bf5xx_nand_platform = {
952 .data_width = NFC_NWIDTH_8,
953 .partitions = partition_info,
954 .nr_partitions = ARRAY_SIZE(partition_info),
955 .rd_dly = 3,
956 .wr_dly = 3,
957 };
958
959 static struct resource bf5xx_nand_resources[] = {
960 {
961 .start = 0xFFC03B00,
962 .end = 0xFFC03B4F,
963 .flags = IORESOURCE_MEM,
964 },
965 {
966 .start = CH_NFC,
967 .end = CH_NFC,
968 .flags = IORESOURCE_IRQ,
969 },
970 };
971
972 static struct platform_device bf5xx_nand_device = {
973 .name = "bf5xx-nand",
974 .id = 0,
975 .num_resources = ARRAY_SIZE(bf5xx_nand_resources),
976 .resource = bf5xx_nand_resources,
977 .dev = {
978 .platform_data = &bf5xx_nand_platform,
979 },
980 };
981 #endif
982
983 #if IS_ENABLED(CONFIG_SDH_BFIN)
984
985 static struct bfin_sd_host bfin_sdh_data = {
986 .dma_chan = CH_SDH,
987 .irq_int0 = IRQ_SDH_MASK0,
988 .pin_req = {P_SD_D0, P_SD_D1, P_SD_D2, P_SD_D3, P_SD_CLK, P_SD_CMD, 0},
989 };
990
991 static struct platform_device bf54x_sdh_device = {
992 .name = "bfin-sdh",
993 .id = 0,
994 .dev = {
995 .platform_data = &bfin_sdh_data,
996 },
997 };
998 #endif
999
1000 #if IS_ENABLED(CONFIG_MTD_PHYSMAP)
1001 static struct mtd_partition ezkit_partitions[] = {
1002 {
1003 .name = "bootloader(nor)",
1004 .size = 0x80000,
1005 .offset = 0,
1006 }, {
1007 .name = "linux kernel(nor)",
1008 .size = 0x400000,
1009 .offset = MTDPART_OFS_APPEND,
1010 }, {
1011 .name = "file system(nor)",
1012 .size = 0x1000000 - 0x80000 - 0x400000 - 0x8000 * 4,
1013 .offset = MTDPART_OFS_APPEND,
1014 }, {
1015 .name = "config(nor)",
1016 .size = 0x8000 * 3,
1017 .offset = MTDPART_OFS_APPEND,
1018 }, {
1019 .name = "u-boot env(nor)",
1020 .size = 0x8000,
1021 .offset = MTDPART_OFS_APPEND,
1022 }
1023 };
1024
1025 static struct physmap_flash_data ezkit_flash_data = {
1026 .width = 2,
1027 .parts = ezkit_partitions,
1028 .nr_parts = ARRAY_SIZE(ezkit_partitions),
1029 };
1030
1031 static struct resource ezkit_flash_resource = {
1032 .start = 0x20000000,
1033 .end = 0x21ffffff,
1034 .flags = IORESOURCE_MEM,
1035 };
1036
1037 static struct platform_device ezkit_flash_device = {
1038 .name = "physmap-flash",
1039 .id = 0,
1040 .dev = {
1041 .platform_data = &ezkit_flash_data,
1042 },
1043 .num_resources = 1,
1044 .resource = &ezkit_flash_resource,
1045 };
1046 #endif
1047
1048 #if IS_ENABLED(CONFIG_MTD_M25P80)
1049 /* SPI flash chip (m25p16) */
1050 static struct mtd_partition bfin_spi_flash_partitions[] = {
1051 {
1052 .name = "bootloader(spi)",
1053 .size = 0x00080000,
1054 .offset = 0,
1055 .mask_flags = MTD_CAP_ROM
1056 }, {
1057 .name = "linux kernel(spi)",
1058 .size = MTDPART_SIZ_FULL,
1059 .offset = MTDPART_OFS_APPEND,
1060 }
1061 };
1062
1063 static struct flash_platform_data bfin_spi_flash_data = {
1064 .name = "m25p80",
1065 .parts = bfin_spi_flash_partitions,
1066 .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
1067 .type = "m25p16",
1068 };
1069
1070 static struct bfin5xx_spi_chip spi_flash_chip_info = {
1071 .enable_dma = 0, /* use dma transfer with this chip*/
1072 };
1073 #endif
1074
1075 #if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7877)
1076 static const struct ad7877_platform_data bfin_ad7877_ts_info = {
1077 .model = 7877,
1078 .vref_delay_usecs = 50, /* internal, no capacitor */
1079 .x_plate_ohms = 419,
1080 .y_plate_ohms = 486,
1081 .pressure_max = 1000,
1082 .pressure_min = 0,
1083 .stopacq_polarity = 1,
1084 .first_conversion_delay = 3,
1085 .acquisition_time = 1,
1086 .averaging = 1,
1087 .pen_down_acc_interval = 1,
1088 };
1089 #endif
1090
1091 #ifdef CONFIG_PINCTRL_ADI2
1092
1093 # define ADI_PINT_DEVNAME "adi-gpio-pint"
1094 # define ADI_GPIO_DEVNAME "adi-gpio"
1095 # define ADI_PINCTRL_DEVNAME "pinctrl-adi2"
1096
1097 static struct platform_device bfin_pinctrl_device = {
1098 .name = ADI_PINCTRL_DEVNAME,
1099 .id = 0,
1100 };
1101
1102 static struct resource bfin_pint0_resources[] = {
1103 {
1104 .start = PINT0_MASK_SET,
1105 .end = PINT0_LATCH + 3,
1106 .flags = IORESOURCE_MEM,
1107 },
1108 {
1109 .start = IRQ_PINT0,
1110 .end = IRQ_PINT0,
1111 .flags = IORESOURCE_IRQ,
1112 },
1113 };
1114
1115 static struct platform_device bfin_pint0_device = {
1116 .name = ADI_PINT_DEVNAME,
1117 .id = 0,
1118 .num_resources = ARRAY_SIZE(bfin_pint0_resources),
1119 .resource = bfin_pint0_resources,
1120 };
1121
1122 static struct resource bfin_pint1_resources[] = {
1123 {
1124 .start = PINT1_MASK_SET,
1125 .end = PINT1_LATCH + 3,
1126 .flags = IORESOURCE_MEM,
1127 },
1128 {
1129 .start = IRQ_PINT1,
1130 .end = IRQ_PINT1,
1131 .flags = IORESOURCE_IRQ,
1132 },
1133 };
1134
1135 static struct platform_device bfin_pint1_device = {
1136 .name = ADI_PINT_DEVNAME,
1137 .id = 1,
1138 .num_resources = ARRAY_SIZE(bfin_pint1_resources),
1139 .resource = bfin_pint1_resources,
1140 };
1141
1142 static struct resource bfin_pint2_resources[] = {
1143 {
1144 .start = PINT2_MASK_SET,
1145 .end = PINT2_LATCH + 3,
1146 .flags = IORESOURCE_MEM,
1147 },
1148 {
1149 .start = IRQ_PINT2,
1150 .end = IRQ_PINT2,
1151 .flags = IORESOURCE_IRQ,
1152 },
1153 };
1154
1155 static struct platform_device bfin_pint2_device = {
1156 .name = ADI_PINT_DEVNAME,
1157 .id = 2,
1158 .num_resources = ARRAY_SIZE(bfin_pint2_resources),
1159 .resource = bfin_pint2_resources,
1160 };
1161
1162 static struct resource bfin_pint3_resources[] = {
1163 {
1164 .start = PINT3_MASK_SET,
1165 .end = PINT3_LATCH + 3,
1166 .flags = IORESOURCE_MEM,
1167 },
1168 {
1169 .start = IRQ_PINT3,
1170 .end = IRQ_PINT3,
1171 .flags = IORESOURCE_IRQ,
1172 },
1173 };
1174
1175 static struct platform_device bfin_pint3_device = {
1176 .name = ADI_PINT_DEVNAME,
1177 .id = 3,
1178 .num_resources = ARRAY_SIZE(bfin_pint3_resources),
1179 .resource = bfin_pint3_resources,
1180 };
1181
1182 static struct resource bfin_gpa_resources[] = {
1183 {
1184 .start = PORTA_FER,
1185 .end = PORTA_MUX + 3,
1186 .flags = IORESOURCE_MEM,
1187 },
1188 { /* optional */
1189 .start = IRQ_PA0,
1190 .end = IRQ_PA0,
1191 .flags = IORESOURCE_IRQ,
1192 },
1193 };
1194
1195 static struct adi_pinctrl_gpio_platform_data bfin_gpa_pdata = {
1196 .port_gpio_base = GPIO_PA0, /* Optional */
1197 .port_pin_base = GPIO_PA0,
1198 .port_width = GPIO_BANKSIZE,
1199 .pint_id = 0, /* PINT0 */
1200 .pint_assign = true, /* PINT upper 16 bit */
1201 .pint_map = 0, /* mapping mask in PINT */
1202 };
1203
1204 static struct platform_device bfin_gpa_device = {
1205 .name = ADI_GPIO_DEVNAME,
1206 .id = 0,
1207 .num_resources = ARRAY_SIZE(bfin_gpa_resources),
1208 .resource = bfin_gpa_resources,
1209 .dev = {
1210 .platform_data = &bfin_gpa_pdata, /* Passed to driver */
1211 },
1212 };
1213
1214 static struct resource bfin_gpb_resources[] = {
1215 {
1216 .start = PORTB_FER,
1217 .end = PORTB_MUX + 3,
1218 .flags = IORESOURCE_MEM,
1219 },
1220 {
1221 .start = IRQ_PB0,
1222 .end = IRQ_PB0,
1223 .flags = IORESOURCE_IRQ,
1224 },
1225 };
1226
1227 static struct adi_pinctrl_gpio_platform_data bfin_gpb_pdata = {
1228 .port_gpio_base = GPIO_PB0,
1229 .port_pin_base = GPIO_PB0,
1230 .port_width = 15,
1231 .pint_id = 0,
1232 .pint_assign = true,
1233 .pint_map = 1,
1234 };
1235
1236 static struct platform_device bfin_gpb_device = {
1237 .name = ADI_GPIO_DEVNAME,
1238 .id = 1,
1239 .num_resources = ARRAY_SIZE(bfin_gpb_resources),
1240 .resource = bfin_gpb_resources,
1241 .dev = {
1242 .platform_data = &bfin_gpb_pdata, /* Passed to driver */
1243 },
1244 };
1245
1246 static struct resource bfin_gpc_resources[] = {
1247 {
1248 .start = PORTC_FER,
1249 .end = PORTC_MUX + 3,
1250 .flags = IORESOURCE_MEM,
1251 },
1252 {
1253 .start = IRQ_PC0,
1254 .end = IRQ_PC0,
1255 .flags = IORESOURCE_IRQ,
1256 },
1257 };
1258
1259 static struct adi_pinctrl_gpio_platform_data bfin_gpc_pdata = {
1260 .port_gpio_base = GPIO_PC0,
1261 .port_pin_base = GPIO_PC0,
1262 .port_width = 14,
1263 .pint_id = 2,
1264 .pint_assign = true,
1265 .pint_map = 0,
1266 };
1267
1268 static struct platform_device bfin_gpc_device = {
1269 .name = ADI_GPIO_DEVNAME,
1270 .id = 2,
1271 .num_resources = ARRAY_SIZE(bfin_gpc_resources),
1272 .resource = bfin_gpc_resources,
1273 .dev = {
1274 .platform_data = &bfin_gpc_pdata, /* Passed to driver */
1275 },
1276 };
1277
1278 static struct resource bfin_gpd_resources[] = {
1279 {
1280 .start = PORTD_FER,
1281 .end = PORTD_MUX + 3,
1282 .flags = IORESOURCE_MEM,
1283 },
1284 {
1285 .start = IRQ_PD0,
1286 .end = IRQ_PD0,
1287 .flags = IORESOURCE_IRQ,
1288 },
1289 };
1290
1291 static struct adi_pinctrl_gpio_platform_data bfin_gpd_pdata = {
1292 .port_gpio_base = GPIO_PD0,
1293 .port_pin_base = GPIO_PD0,
1294 .port_width = GPIO_BANKSIZE,
1295 .pint_id = 2,
1296 .pint_assign = false,
1297 .pint_map = 1,
1298 };
1299
1300 static struct platform_device bfin_gpd_device = {
1301 .name = ADI_GPIO_DEVNAME,
1302 .id = 3,
1303 .num_resources = ARRAY_SIZE(bfin_gpd_resources),
1304 .resource = bfin_gpd_resources,
1305 .dev = {
1306 .platform_data = &bfin_gpd_pdata, /* Passed to driver */
1307 },
1308 };
1309
1310 static struct resource bfin_gpe_resources[] = {
1311 {
1312 .start = PORTE_FER,
1313 .end = PORTE_MUX + 3,
1314 .flags = IORESOURCE_MEM,
1315 },
1316 {
1317 .start = IRQ_PE0,
1318 .end = IRQ_PE0,
1319 .flags = IORESOURCE_IRQ,
1320 },
1321 };
1322
1323 static struct adi_pinctrl_gpio_platform_data bfin_gpe_pdata = {
1324 .port_gpio_base = GPIO_PE0,
1325 .port_pin_base = GPIO_PE0,
1326 .port_width = GPIO_BANKSIZE,
1327 .pint_id = 3,
1328 .pint_assign = true,
1329 .pint_map = 2,
1330 };
1331
1332 static struct platform_device bfin_gpe_device = {
1333 .name = ADI_GPIO_DEVNAME,
1334 .id = 4,
1335 .num_resources = ARRAY_SIZE(bfin_gpe_resources),
1336 .resource = bfin_gpe_resources,
1337 .dev = {
1338 .platform_data = &bfin_gpe_pdata, /* Passed to driver */
1339 },
1340 };
1341
1342 static struct resource bfin_gpf_resources[] = {
1343 {
1344 .start = PORTF_FER,
1345 .end = PORTF_MUX + 3,
1346 .flags = IORESOURCE_MEM,
1347 },
1348 {
1349 .start = IRQ_PF0,
1350 .end = IRQ_PF0,
1351 .flags = IORESOURCE_IRQ,
1352 },
1353 };
1354
1355 static struct adi_pinctrl_gpio_platform_data bfin_gpf_pdata = {
1356 .port_gpio_base = GPIO_PF0,
1357 .port_pin_base = GPIO_PF0,
1358 .port_width = GPIO_BANKSIZE,
1359 .pint_id = 3,
1360 .pint_assign = false,
1361 .pint_map = 3,
1362 };
1363
1364 static struct platform_device bfin_gpf_device = {
1365 .name = ADI_GPIO_DEVNAME,
1366 .id = 5,
1367 .num_resources = ARRAY_SIZE(bfin_gpf_resources),
1368 .resource = bfin_gpf_resources,
1369 .dev = {
1370 .platform_data = &bfin_gpf_pdata, /* Passed to driver */
1371 },
1372 };
1373
1374 static struct resource bfin_gpg_resources[] = {
1375 {
1376 .start = PORTG_FER,
1377 .end = PORTG_MUX + 3,
1378 .flags = IORESOURCE_MEM,
1379 },
1380 {
1381 .start = IRQ_PG0,
1382 .end = IRQ_PG0,
1383 .flags = IORESOURCE_IRQ,
1384 },
1385 };
1386
1387 static struct adi_pinctrl_gpio_platform_data bfin_gpg_pdata = {
1388 .port_gpio_base = GPIO_PG0,
1389 .port_pin_base = GPIO_PG0,
1390 .port_width = GPIO_BANKSIZE,
1391 .pint_id = -1,
1392 };
1393
1394 static struct platform_device bfin_gpg_device = {
1395 .name = ADI_GPIO_DEVNAME,
1396 .id = 6,
1397 .num_resources = ARRAY_SIZE(bfin_gpg_resources),
1398 .resource = bfin_gpg_resources,
1399 .dev = {
1400 .platform_data = &bfin_gpg_pdata, /* Passed to driver */
1401 },
1402 };
1403
1404 static struct resource bfin_gph_resources[] = {
1405 {
1406 .start = PORTH_FER,
1407 .end = PORTH_MUX + 3,
1408 .flags = IORESOURCE_MEM,
1409 },
1410 {
1411 .start = IRQ_PH0,
1412 .end = IRQ_PH0,
1413 .flags = IORESOURCE_IRQ,
1414 },
1415 };
1416
1417 static struct adi_pinctrl_gpio_platform_data bfin_gph_pdata = {
1418 .port_gpio_base = GPIO_PH0,
1419 .port_pin_base = GPIO_PH0,
1420 .port_width = 14,
1421 .pint_id = -1,
1422 };
1423
1424 static struct platform_device bfin_gph_device = {
1425 .name = ADI_GPIO_DEVNAME,
1426 .id = 7,
1427 .num_resources = ARRAY_SIZE(bfin_gph_resources),
1428 .resource = bfin_gph_resources,
1429 .dev = {
1430 .platform_data = &bfin_gph_pdata, /* Passed to driver */
1431 },
1432 };
1433
1434 static struct resource bfin_gpi_resources[] = {
1435 {
1436 .start = PORTI_FER,
1437 .end = PORTI_MUX + 3,
1438 .flags = IORESOURCE_MEM,
1439 },
1440 {
1441 .start = IRQ_PI0,
1442 .end = IRQ_PI0,
1443 .flags = IORESOURCE_IRQ,
1444 },
1445 };
1446
1447 static struct adi_pinctrl_gpio_platform_data bfin_gpi_pdata = {
1448 .port_gpio_base = GPIO_PI0,
1449 .port_pin_base = GPIO_PI0,
1450 .port_width = GPIO_BANKSIZE,
1451 .pint_id = -1,
1452 };
1453
1454 static struct platform_device bfin_gpi_device = {
1455 .name = ADI_GPIO_DEVNAME,
1456 .id = 8,
1457 .num_resources = ARRAY_SIZE(bfin_gpi_resources),
1458 .resource = bfin_gpi_resources,
1459 .dev = {
1460 .platform_data = &bfin_gpi_pdata, /* Passed to driver */
1461 },
1462 };
1463
1464 static struct resource bfin_gpj_resources[] = {
1465 {
1466 .start = PORTJ_FER,
1467 .end = PORTJ_MUX + 3,
1468 .flags = IORESOURCE_MEM,
1469 },
1470 {
1471 .start = IRQ_PJ0,
1472 .end = IRQ_PJ0,
1473 .flags = IORESOURCE_IRQ,
1474 },
1475 };
1476
1477 static struct adi_pinctrl_gpio_platform_data bfin_gpj_pdata = {
1478 .port_gpio_base = GPIO_PJ0,
1479 .port_pin_base = GPIO_PJ0,
1480 .port_width = 14,
1481 .pint_id = -1,
1482 };
1483
1484 static struct platform_device bfin_gpj_device = {
1485 .name = ADI_GPIO_DEVNAME,
1486 .id = 9,
1487 .num_resources = ARRAY_SIZE(bfin_gpj_resources),
1488 .resource = bfin_gpj_resources,
1489 .dev = {
1490 .platform_data = &bfin_gpj_pdata, /* Passed to driver */
1491 },
1492 };
1493
1494 #endif
1495
1496 static struct spi_board_info bfin_spi_board_info[] __initdata = {
1497 #if IS_ENABLED(CONFIG_MTD_M25P80)
1498 {
1499 /* the modalias must be the same as spi device driver name */
1500 .modalias = "m25p80", /* Name of spi_driver for this device */
1501 .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
1502 .bus_num = 0, /* Framework bus number */
1503 .chip_select = MAX_CTRL_CS + GPIO_PE4, /* SPI_SSEL1*/
1504 .platform_data = &bfin_spi_flash_data,
1505 .controller_data = &spi_flash_chip_info,
1506 .mode = SPI_MODE_3,
1507 },
1508 #endif
1509 #if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD183X)
1510 {
1511 .modalias = "ad183x",
1512 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
1513 .bus_num = 1,
1514 .chip_select = MAX_CTRL_CS + GPIO_PG6, /* SPI_SSEL2 */
1515 },
1516 #endif
1517 #if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7877)
1518 {
1519 .modalias = "ad7877",
1520 .platform_data = &bfin_ad7877_ts_info,
1521 .irq = IRQ_PB4, /* old boards (<=Rev 1.3) use IRQ_PJ11 */
1522 .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */
1523 .bus_num = 0,
1524 .chip_select = MAX_CTRL_CS + GPIO_PE5, /* SPI_SSEL2 */
1525 },
1526 #endif
1527 #if IS_ENABLED(CONFIG_SPI_SPIDEV)
1528 {
1529 .modalias = "spidev",
1530 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
1531 .bus_num = 0,
1532 .chip_select = MAX_CTRL_CS + GPIO_PE4, /* SPI_SSEL1 */
1533 },
1534 #endif
1535 #if IS_ENABLED(CONFIG_INPUT_ADXL34X_SPI)
1536 {
1537 .modalias = "adxl34x",
1538 .platform_data = &adxl34x_info,
1539 .irq = IRQ_PC5,
1540 .max_speed_hz = 5000000, /* max spi clock (SCK) speed in HZ */
1541 .bus_num = 1,
1542 .chip_select = MAX_CTRL_CS + GPIO_PG6, /* SPI_SSEL2 */
1543 .mode = SPI_MODE_3,
1544 },
1545 #endif
1546 };
1547 #if IS_ENABLED(CONFIG_SPI_BFIN5XX)
1548 /* SPI (0) */
1549 static struct resource bfin_spi0_resource[] = {
1550 [0] = {
1551 .start = SPI0_REGBASE,
1552 .end = SPI0_REGBASE + 0xFF,
1553 .flags = IORESOURCE_MEM,
1554 },
1555 [1] = {
1556 .start = CH_SPI0,
1557 .end = CH_SPI0,
1558 .flags = IORESOURCE_DMA,
1559 },
1560 [2] = {
1561 .start = IRQ_SPI0,
1562 .end = IRQ_SPI0,
1563 .flags = IORESOURCE_IRQ,
1564 }
1565 };
1566
1567 /* SPI (1) */
1568 static struct resource bfin_spi1_resource[] = {
1569 [0] = {
1570 .start = SPI1_REGBASE,
1571 .end = SPI1_REGBASE + 0xFF,
1572 .flags = IORESOURCE_MEM,
1573 },
1574 [1] = {
1575 .start = CH_SPI1,
1576 .end = CH_SPI1,
1577 .flags = IORESOURCE_DMA,
1578 },
1579 [2] = {
1580 .start = IRQ_SPI1,
1581 .end = IRQ_SPI1,
1582 .flags = IORESOURCE_IRQ,
1583 }
1584 };
1585
1586 /* SPI controller data */
1587 static struct bfin5xx_spi_master bf54x_spi_master_info0 = {
1588 .num_chipselect = MAX_CTRL_CS + MAX_BLACKFIN_GPIOS,
1589 .enable_dma = 1, /* master has the ability to do dma transfer */
1590 .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
1591 };
1592
1593 static struct platform_device bf54x_spi_master0 = {
1594 .name = "bfin-spi",
1595 .id = 0, /* Bus number */
1596 .num_resources = ARRAY_SIZE(bfin_spi0_resource),
1597 .resource = bfin_spi0_resource,
1598 .dev = {
1599 .platform_data = &bf54x_spi_master_info0, /* Passed to driver */
1600 },
1601 };
1602
1603 static struct bfin5xx_spi_master bf54x_spi_master_info1 = {
1604 .num_chipselect = MAX_CTRL_CS + MAX_BLACKFIN_GPIOS,
1605 .enable_dma = 1, /* master has the ability to do dma transfer */
1606 .pin_req = {P_SPI1_SCK, P_SPI1_MISO, P_SPI1_MOSI, 0},
1607 };
1608
1609 static struct platform_device bf54x_spi_master1 = {
1610 .name = "bfin-spi",
1611 .id = 1, /* Bus number */
1612 .num_resources = ARRAY_SIZE(bfin_spi1_resource),
1613 .resource = bfin_spi1_resource,
1614 .dev = {
1615 .platform_data = &bf54x_spi_master_info1, /* Passed to driver */
1616 },
1617 };
1618 #endif /* spi master and devices */
1619
1620 #if IS_ENABLED(CONFIG_VIDEO_BLACKFIN_CAPTURE)
1621 #include <linux/videodev2.h>
1622 #include <media/blackfin/bfin_capture.h>
1623 #include <media/blackfin/ppi.h>
1624
1625 static const unsigned short ppi_req[] = {
1626 P_PPI1_D0, P_PPI1_D1, P_PPI1_D2, P_PPI1_D3,
1627 P_PPI1_D4, P_PPI1_D5, P_PPI1_D6, P_PPI1_D7,
1628 P_PPI1_CLK, P_PPI1_FS1, P_PPI1_FS2,
1629 0,
1630 };
1631
1632 static const struct ppi_info ppi_info = {
1633 .type = PPI_TYPE_EPPI,
1634 .dma_ch = CH_EPPI1,
1635 .irq_err = IRQ_EPPI1_ERROR,
1636 .base = (void __iomem *)EPPI1_STATUS,
1637 .pin_req = ppi_req,
1638 };
1639
1640 #if IS_ENABLED(CONFIG_VIDEO_VS6624)
1641 static struct v4l2_input vs6624_inputs[] = {
1642 {
1643 .index = 0,
1644 .name = "Camera",
1645 .type = V4L2_INPUT_TYPE_CAMERA,
1646 .std = V4L2_STD_UNKNOWN,
1647 },
1648 };
1649
1650 static struct bcap_route vs6624_routes[] = {
1651 {
1652 .input = 0,
1653 .output = 0,
1654 },
1655 };
1656
1657 static const unsigned vs6624_ce_pin = GPIO_PG6;
1658
1659 static struct bfin_capture_config bfin_capture_data = {
1660 .card_name = "BF548",
1661 .inputs = vs6624_inputs,
1662 .num_inputs = ARRAY_SIZE(vs6624_inputs),
1663 .routes = vs6624_routes,
1664 .i2c_adapter_id = 0,
1665 .board_info = {
1666 .type = "vs6624",
1667 .addr = 0x10,
1668 .platform_data = (void *)&vs6624_ce_pin,
1669 },
1670 .ppi_info = &ppi_info,
1671 .ppi_control = (POLC | PACKEN | DLEN_8 | XFR_TYPE | 0x20),
1672 .int_mask = 0xFFFFFFFF, /* disable error interrupt on eppi */
1673 .blank_clocks = 8, /* 8 clocks as SAV and EAV */
1674 };
1675 #endif
1676
1677 static struct platform_device bfin_capture_device = {
1678 .name = "bfin_capture",
1679 .dev = {
1680 .platform_data = &bfin_capture_data,
1681 },
1682 };
1683 #endif
1684
1685 #if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
1686 static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0};
1687
1688 static struct resource bfin_twi0_resource[] = {
1689 [0] = {
1690 .start = TWI0_REGBASE,
1691 .end = TWI0_REGBASE + 0xFF,
1692 .flags = IORESOURCE_MEM,
1693 },
1694 [1] = {
1695 .start = IRQ_TWI0,
1696 .end = IRQ_TWI0,
1697 .flags = IORESOURCE_IRQ,
1698 },
1699 };
1700
1701 static struct platform_device i2c_bfin_twi0_device = {
1702 .name = "i2c-bfin-twi",
1703 .id = 0,
1704 .num_resources = ARRAY_SIZE(bfin_twi0_resource),
1705 .resource = bfin_twi0_resource,
1706 .dev = {
1707 .platform_data = &bfin_twi0_pins,
1708 },
1709 };
1710
1711 #if !defined(CONFIG_BF542) /* The BF542 only has 1 TWI */
1712 static const u16 bfin_twi1_pins[] = {P_TWI1_SCL, P_TWI1_SDA, 0};
1713
1714 static struct resource bfin_twi1_resource[] = {
1715 [0] = {
1716 .start = TWI1_REGBASE,
1717 .end = TWI1_REGBASE + 0xFF,
1718 .flags = IORESOURCE_MEM,
1719 },
1720 [1] = {
1721 .start = IRQ_TWI1,
1722 .end = IRQ_TWI1,
1723 .flags = IORESOURCE_IRQ,
1724 },
1725 };
1726
1727 static struct platform_device i2c_bfin_twi1_device = {
1728 .name = "i2c-bfin-twi",
1729 .id = 1,
1730 .num_resources = ARRAY_SIZE(bfin_twi1_resource),
1731 .resource = bfin_twi1_resource,
1732 .dev = {
1733 .platform_data = &bfin_twi1_pins,
1734 },
1735 };
1736 #endif
1737 #endif
1738
1739 static struct i2c_board_info __initdata bfin_i2c_board_info0[] = {
1740 #if IS_ENABLED(CONFIG_SND_SOC_SSM2602)
1741 {
1742 I2C_BOARD_INFO("ssm2602", 0x1b),
1743 },
1744 #endif
1745 };
1746
1747 #if !defined(CONFIG_BF542) /* The BF542 only has 1 TWI */
1748 static struct i2c_board_info __initdata bfin_i2c_board_info1[] = {
1749 #if IS_ENABLED(CONFIG_BFIN_TWI_LCD)
1750 {
1751 I2C_BOARD_INFO("pcf8574_lcd", 0x22),
1752 },
1753 #endif
1754 #if IS_ENABLED(CONFIG_INPUT_PCF8574)
1755 {
1756 I2C_BOARD_INFO("pcf8574_keypad", 0x27),
1757 .irq = 212,
1758 },
1759 #endif
1760 #if IS_ENABLED(CONFIG_INPUT_ADXL34X_I2C)
1761 {
1762 I2C_BOARD_INFO("adxl34x", 0x53),
1763 .irq = IRQ_PC5,
1764 .platform_data = (void *)&adxl34x_info,
1765 },
1766 #endif
1767 #if IS_ENABLED(CONFIG_BFIN_TWI_LCD)
1768 {
1769 I2C_BOARD_INFO("ad5252", 0x2f),
1770 },
1771 #endif
1772 };
1773 #endif
1774
1775 #if IS_ENABLED(CONFIG_KEYBOARD_GPIO)
1776 #include <linux/gpio_keys.h>
1777
1778 static struct gpio_keys_button bfin_gpio_keys_table[] = {
1779 {BTN_0, GPIO_PB8, 1, "gpio-keys: BTN0"},
1780 {BTN_1, GPIO_PB9, 1, "gpio-keys: BTN1"},
1781 {BTN_2, GPIO_PB10, 1, "gpio-keys: BTN2"},
1782 {BTN_3, GPIO_PB11, 1, "gpio-keys: BTN3"},
1783 };
1784
1785 static struct gpio_keys_platform_data bfin_gpio_keys_data = {
1786 .buttons = bfin_gpio_keys_table,
1787 .nbuttons = ARRAY_SIZE(bfin_gpio_keys_table),
1788 };
1789
1790 static struct platform_device bfin_device_gpiokeys = {
1791 .name = "gpio-keys",
1792 .dev = {
1793 .platform_data = &bfin_gpio_keys_data,
1794 },
1795 };
1796 #endif
1797
1798 static const unsigned int cclk_vlev_datasheet[] =
1799 {
1800 /*
1801 * Internal VLEV BF54XSBBC1533
1802 ****temporarily using these values until data sheet is updated
1803 */
1804 VRPAIR(VLEV_085, 150000000),
1805 VRPAIR(VLEV_090, 250000000),
1806 VRPAIR(VLEV_110, 276000000),
1807 VRPAIR(VLEV_115, 301000000),
1808 VRPAIR(VLEV_120, 525000000),
1809 VRPAIR(VLEV_125, 550000000),
1810 VRPAIR(VLEV_130, 600000000),
1811 };
1812
1813 static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
1814 .tuple_tab = cclk_vlev_datasheet,
1815 .tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
1816 .vr_settling_time = 25 /* us */,
1817 };
1818
1819 static struct platform_device bfin_dpmc = {
1820 .name = "bfin dpmc",
1821 .dev = {
1822 .platform_data = &bfin_dmpc_vreg_data,
1823 },
1824 };
1825
1826 #if IS_ENABLED(CONFIG_SND_BF5XX_I2S) || \
1827 IS_ENABLED(CONFIG_SND_BF5XX_AC97)
1828
1829 #define SPORT_REQ(x) \
1830 [x] = {P_SPORT##x##_TFS, P_SPORT##x##_DTPRI, P_SPORT##x##_TSCLK, \
1831 P_SPORT##x##_RFS, P_SPORT##x##_DRPRI, P_SPORT##x##_RSCLK, 0}
1832
1833 static const u16 bfin_snd_pin[][7] = {
1834 SPORT_REQ(0),
1835 SPORT_REQ(1),
1836 SPORT_REQ(2),
1837 SPORT_REQ(3),
1838 };
1839
1840 static struct bfin_snd_platform_data bfin_snd_data[] = {
1841 {
1842 .pin_req = &bfin_snd_pin[0][0],
1843 },
1844 {
1845 .pin_req = &bfin_snd_pin[1][0],
1846 },
1847 {
1848 .pin_req = &bfin_snd_pin[2][0],
1849 },
1850 {
1851 .pin_req = &bfin_snd_pin[3][0],
1852 },
1853 };
1854
1855 #define BFIN_SND_RES(x) \
1856 [x] = { \
1857 { \
1858 .start = SPORT##x##_TCR1, \
1859 .end = SPORT##x##_TCR1, \
1860 .flags = IORESOURCE_MEM \
1861 }, \
1862 { \
1863 .start = CH_SPORT##x##_RX, \
1864 .end = CH_SPORT##x##_RX, \
1865 .flags = IORESOURCE_DMA, \
1866 }, \
1867 { \
1868 .start = CH_SPORT##x##_TX, \
1869 .end = CH_SPORT##x##_TX, \
1870 .flags = IORESOURCE_DMA, \
1871 }, \
1872 { \
1873 .start = IRQ_SPORT##x##_ERROR, \
1874 .end = IRQ_SPORT##x##_ERROR, \
1875 .flags = IORESOURCE_IRQ, \
1876 } \
1877 }
1878
1879 static struct resource bfin_snd_resources[][4] = {
1880 BFIN_SND_RES(0),
1881 BFIN_SND_RES(1),
1882 BFIN_SND_RES(2),
1883 BFIN_SND_RES(3),
1884 };
1885 #endif
1886
1887 #if IS_ENABLED(CONFIG_SND_BF5XX_I2S)
1888 static struct platform_device bfin_i2s_pcm = {
1889 .name = "bfin-i2s-pcm-audio",
1890 .id = -1,
1891 };
1892 #endif
1893
1894 #if IS_ENABLED(CONFIG_SND_BF5XX_AC97)
1895 static struct platform_device bfin_ac97_pcm = {
1896 .name = "bfin-ac97-pcm-audio",
1897 .id = -1,
1898 };
1899 #endif
1900
1901 #if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD73311)
1902 static struct platform_device bfin_ad73311_codec_device = {
1903 .name = "ad73311",
1904 .id = -1,
1905 };
1906 #endif
1907
1908 #if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD1980)
1909 static struct platform_device bfin_ad1980_codec_device = {
1910 .name = "ad1980",
1911 .id = -1,
1912 };
1913 #endif
1914
1915 #if IS_ENABLED(CONFIG_SND_BF5XX_SOC_I2S)
1916 static struct platform_device bfin_i2s = {
1917 .name = "bfin-i2s",
1918 .id = CONFIG_SND_BF5XX_SPORT_NUM,
1919 .num_resources = ARRAY_SIZE(bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM]),
1920 .resource = bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM],
1921 .dev = {
1922 .platform_data = &bfin_snd_data[CONFIG_SND_BF5XX_SPORT_NUM],
1923 },
1924 };
1925 #endif
1926
1927 #if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AC97)
1928 static struct platform_device bfin_ac97 = {
1929 .name = "bfin-ac97",
1930 .id = CONFIG_SND_BF5XX_SPORT_NUM,
1931 .num_resources = ARRAY_SIZE(bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM]),
1932 .resource = bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM],
1933 .dev = {
1934 .platform_data = &bfin_snd_data[CONFIG_SND_BF5XX_SPORT_NUM],
1935 },
1936 };
1937 #endif
1938
1939 static struct platform_device *ezkit_devices[] __initdata = {
1940
1941 &bfin_dpmc,
1942 #if defined(CONFIG_PINCTRL_ADI2)
1943 &bfin_pinctrl_device,
1944 &bfin_pint0_device,
1945 &bfin_pint1_device,
1946 &bfin_pint2_device,
1947 &bfin_pint3_device,
1948 &bfin_gpa_device,
1949 &bfin_gpb_device,
1950 &bfin_gpc_device,
1951 &bfin_gpd_device,
1952 &bfin_gpe_device,
1953 &bfin_gpf_device,
1954 &bfin_gpg_device,
1955 &bfin_gph_device,
1956 &bfin_gpi_device,
1957 &bfin_gpj_device,
1958 #endif
1959
1960 #if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
1961 &rtc_device,
1962 #endif
1963
1964 #if IS_ENABLED(CONFIG_SERIAL_BFIN)
1965 #ifdef CONFIG_SERIAL_BFIN_UART0
1966 &bfin_uart0_device,
1967 #endif
1968 #ifdef CONFIG_SERIAL_BFIN_UART1
1969 &bfin_uart1_device,
1970 #endif
1971 #ifdef CONFIG_SERIAL_BFIN_UART2
1972 &bfin_uart2_device,
1973 #endif
1974 #ifdef CONFIG_SERIAL_BFIN_UART3
1975 &bfin_uart3_device,
1976 #endif
1977 #endif
1978
1979 #if IS_ENABLED(CONFIG_BFIN_SIR)
1980 #ifdef CONFIG_BFIN_SIR0
1981 &bfin_sir0_device,
1982 #endif
1983 #ifdef CONFIG_BFIN_SIR1
1984 &bfin_sir1_device,
1985 #endif
1986 #ifdef CONFIG_BFIN_SIR2
1987 &bfin_sir2_device,
1988 #endif
1989 #ifdef CONFIG_BFIN_SIR3
1990 &bfin_sir3_device,
1991 #endif
1992 #endif
1993
1994 #if IS_ENABLED(CONFIG_FB_BF54X_LQ043)
1995 &bf54x_lq043_device,
1996 #endif
1997
1998 #if IS_ENABLED(CONFIG_SMSC911X)
1999 &smsc911x_device,
2000 #endif
2001
2002 #if IS_ENABLED(CONFIG_USB_MUSB_HDRC)
2003 &musb_device,
2004 #endif
2005
2006 #if IS_ENABLED(CONFIG_USB_ISP1760_HCD)
2007 &bfin_isp1760_device,
2008 #endif
2009
2010 #if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
2011 #ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
2012 &bfin_sport0_uart_device,
2013 #endif
2014 #ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
2015 &bfin_sport1_uart_device,
2016 #endif
2017 #ifdef CONFIG_SERIAL_BFIN_SPORT2_UART
2018 &bfin_sport2_uart_device,
2019 #endif
2020 #ifdef CONFIG_SERIAL_BFIN_SPORT3_UART
2021 &bfin_sport3_uart_device,
2022 #endif
2023 #endif
2024
2025 #if IS_ENABLED(CONFIG_CAN_BFIN)
2026 &bfin_can0_device,
2027 &bfin_can1_device,
2028 #endif
2029
2030 #if IS_ENABLED(CONFIG_PATA_BF54X)
2031 &bfin_atapi_device,
2032 #endif
2033
2034 #if IS_ENABLED(CONFIG_MTD_NAND_BF5XX)
2035 &bf5xx_nand_device,
2036 #endif
2037
2038 #if IS_ENABLED(CONFIG_SDH_BFIN)
2039 &bf54x_sdh_device,
2040 #endif
2041
2042 #if IS_ENABLED(CONFIG_SPI_BFIN5XX)
2043 &bf54x_spi_master0,
2044 &bf54x_spi_master1,
2045 #endif
2046 #if IS_ENABLED(CONFIG_VIDEO_BLACKFIN_CAPTURE)
2047 &bfin_capture_device,
2048 #endif
2049
2050 #if IS_ENABLED(CONFIG_KEYBOARD_BFIN)
2051 &bf54x_kpad_device,
2052 #endif
2053
2054 #if IS_ENABLED(CONFIG_INPUT_BFIN_ROTARY)
2055 &bfin_rotary_device,
2056 #endif
2057
2058 #if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
2059 &i2c_bfin_twi0_device,
2060 #if !defined(CONFIG_BF542)
2061 &i2c_bfin_twi1_device,
2062 #endif
2063 #endif
2064
2065 #if IS_ENABLED(CONFIG_KEYBOARD_GPIO)
2066 &bfin_device_gpiokeys,
2067 #endif
2068
2069 #if IS_ENABLED(CONFIG_MTD_PHYSMAP)
2070 &ezkit_flash_device,
2071 #endif
2072
2073 #if IS_ENABLED(CONFIG_SND_BF5XX_I2S)
2074 &bfin_i2s_pcm,
2075 #endif
2076
2077 #if IS_ENABLED(CONFIG_SND_BF5XX_AC97)
2078 &bfin_ac97_pcm,
2079 #endif
2080
2081 #if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD1980)
2082 &bfin_ad1980_codec_device,
2083 #endif
2084
2085 #if IS_ENABLED(CONFIG_SND_BF5XX_I2S)
2086 &bfin_i2s,
2087 #endif
2088
2089 #if IS_ENABLED(CONFIG_SND_BF5XX_AC97)
2090 &bfin_ac97,
2091 #endif
2092 };
2093
2094 /* Pin control settings */
2095 static struct pinctrl_map __initdata bfin_pinmux_map[] = {
2096 /* per-device maps */
2097 PIN_MAP_MUX_GROUP_DEFAULT("bfin-uart.0", "pinctrl-adi2.0", NULL, "uart0"),
2098 PIN_MAP_MUX_GROUP_DEFAULT("bfin-uart.1", "pinctrl-adi2.0", NULL, "uart1"),
2099 #ifdef CONFIG_BFIN_UART1_CTSRTS
2100 PIN_MAP_MUX_GROUP_DEFAULT("bfin-uart.1", "pinctrl-adi2.0", NULL, "uart1_ctsrts"),
2101 #endif
2102 PIN_MAP_MUX_GROUP_DEFAULT("bfin-uart.2", "pinctrl-adi2.0", NULL, "uart2"),
2103 PIN_MAP_MUX_GROUP_DEFAULT("bfin-uart.3", "pinctrl-adi2.0", NULL, "uart3"),
2104 #ifdef CONFIG_BFIN_UART3_CTSRTS
2105 PIN_MAP_MUX_GROUP_DEFAULT("bfin-uart.3", "pinctrl-adi2.0", NULL, "uart3_ctsrts"),
2106 #endif
2107 PIN_MAP_MUX_GROUP_DEFAULT("bfin_sir.0", "pinctrl-adi2.0", NULL, "uart0"),
2108 PIN_MAP_MUX_GROUP_DEFAULT("bfin_sir.1", "pinctrl-adi2.0", NULL, "uart1"),
2109 PIN_MAP_MUX_GROUP_DEFAULT("bfin_sir.2", "pinctrl-adi2.0", NULL, "uart2"),
2110 PIN_MAP_MUX_GROUP_DEFAULT("bfin_sir.3", "pinctrl-adi2.0", NULL, "uart3"),
2111 PIN_MAP_MUX_GROUP_DEFAULT("bfin-sdh.0", "pinctrl-adi2.0", NULL, "rsi0"),
2112 PIN_MAP_MUX_GROUP_DEFAULT("bfin-spi.0", "pinctrl-adi2.0", NULL, "spi0"),
2113 PIN_MAP_MUX_GROUP_DEFAULT("bfin-spi.1", "pinctrl-adi2.0", NULL, "spi1"),
2114 PIN_MAP_MUX_GROUP_DEFAULT("i2c-bfin-twi.0", "pinctrl-adi2.0", NULL, "twi0"),
2115 #if !defined(CONFIG_BF542) /* The BF542 only has 1 TWI */
2116 PIN_MAP_MUX_GROUP_DEFAULT("i2c-bfin-twi.1", "pinctrl-adi2.0", NULL, "twi1"),
2117 #endif
2118 PIN_MAP_MUX_GROUP_DEFAULT("bfin-rotary", "pinctrl-adi2.0", NULL, "rotary"),
2119 PIN_MAP_MUX_GROUP_DEFAULT("bfin_can.0", "pinctrl-adi2.0", NULL, "can0"),
2120 PIN_MAP_MUX_GROUP_DEFAULT("bfin_can.1", "pinctrl-adi2.0", NULL, "can1"),
2121 PIN_MAP_MUX_GROUP_DEFAULT("bf54x-lq043", "pinctrl-adi2.0", NULL, "ppi0_24b"),
2122 PIN_MAP_MUX_GROUP_DEFAULT("bfin-i2s.0", "pinctrl-adi2.0", NULL, "sport0"),
2123 PIN_MAP_MUX_GROUP_DEFAULT("bfin-tdm.0", "pinctrl-adi2.0", NULL, "sport0"),
2124 PIN_MAP_MUX_GROUP_DEFAULT("bfin-ac97.0", "pinctrl-adi2.0", NULL, "sport0"),
2125 PIN_MAP_MUX_GROUP_DEFAULT("bfin-i2s.1", "pinctrl-adi2.0", NULL, "sport1"),
2126 PIN_MAP_MUX_GROUP_DEFAULT("bfin-tdm.1", "pinctrl-adi2.0", NULL, "sport1"),
2127 PIN_MAP_MUX_GROUP_DEFAULT("bfin-ac97.1", "pinctrl-adi2.0", NULL, "sport1"),
2128 PIN_MAP_MUX_GROUP_DEFAULT("bfin-i2s.2", "pinctrl-adi2.0", NULL, "sport2"),
2129 PIN_MAP_MUX_GROUP_DEFAULT("bfin-tdm.2", "pinctrl-adi2.0", NULL, "sport2"),
2130 PIN_MAP_MUX_GROUP_DEFAULT("bfin-ac97.2", "pinctrl-adi2.0", NULL, "sport2"),
2131 PIN_MAP_MUX_GROUP_DEFAULT("bfin-i2s.3", "pinctrl-adi2.0", NULL, "sport3"),
2132 PIN_MAP_MUX_GROUP_DEFAULT("bfin-tdm.3", "pinctrl-adi2.0", NULL, "sport3"),
2133 PIN_MAP_MUX_GROUP_DEFAULT("bfin-ac97.3", "pinctrl-adi2.0", NULL, "sport3"),
2134 PIN_MAP_MUX_GROUP_DEFAULT("bfin-sport-uart.0", "pinctrl-adi2.0", NULL, "sport0"),
2135 PIN_MAP_MUX_GROUP_DEFAULT("bfin-sport-uart.1", "pinctrl-adi2.0", NULL, "sport1"),
2136 PIN_MAP_MUX_GROUP_DEFAULT("bfin-sport-uart.2", "pinctrl-adi2.0", NULL, "sport2"),
2137 PIN_MAP_MUX_GROUP_DEFAULT("bfin-sport-uart.3", "pinctrl-adi2.0", NULL, "sport3"),
2138 PIN_MAP_MUX_GROUP_DEFAULT("pata-bf54x", "pinctrl-adi2.0", NULL, "atapi"),
2139 #ifdef CONFIG_BF548_ATAPI_ALTERNATIVE_PORT
2140 PIN_MAP_MUX_GROUP_DEFAULT("pata-bf54x", "pinctrl-adi2.0", NULL, "atapi_alter"),
2141 #endif
2142 PIN_MAP_MUX_GROUP_DEFAULT("bf5xx-nand.0", "pinctrl-adi2.0", NULL, "nfc0"),
2143 PIN_MAP_MUX_GROUP_DEFAULT("bf54x-keys", "pinctrl-adi2.0", NULL, "keys_4x4"),
2144 };
2145
2146 static int __init ezkit_init(void)
2147 {
2148 printk(KERN_INFO "%s(): registering device resources\n", __func__);
2149
2150 /* Initialize pinmuxing */
2151 pinctrl_register_mappings(bfin_pinmux_map,
2152 ARRAY_SIZE(bfin_pinmux_map));
2153
2154 i2c_register_board_info(0, bfin_i2c_board_info0,
2155 ARRAY_SIZE(bfin_i2c_board_info0));
2156 #if !defined(CONFIG_BF542) /* The BF542 only has 1 TWI */
2157 i2c_register_board_info(1, bfin_i2c_board_info1,
2158 ARRAY_SIZE(bfin_i2c_board_info1));
2159 #endif
2160
2161 platform_add_devices(ezkit_devices, ARRAY_SIZE(ezkit_devices));
2162
2163 spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
2164
2165 return 0;
2166 }
2167
2168 arch_initcall(ezkit_init);
2169
2170 static struct platform_device *ezkit_early_devices[] __initdata = {
2171 #if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
2172 #ifdef CONFIG_SERIAL_BFIN_UART0
2173 &bfin_uart0_device,
2174 #endif
2175 #ifdef CONFIG_SERIAL_BFIN_UART1
2176 &bfin_uart1_device,
2177 #endif
2178 #ifdef CONFIG_SERIAL_BFIN_UART2
2179 &bfin_uart2_device,
2180 #endif
2181 #ifdef CONFIG_SERIAL_BFIN_UART3
2182 &bfin_uart3_device,
2183 #endif
2184 #endif
2185 };
2186
2187 void __init native_machine_early_platform_add_devices(void)
2188 {
2189 printk(KERN_INFO "register early platform devices\n");
2190 early_platform_add_devices(ezkit_early_devices,
2191 ARRAY_SIZE(ezkit_early_devices));
2192 }
Linux kernel - Deliverables
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