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[deliverable/linux.git] / arch / blackfin / mach-bf609 / boards / ezkit.c
1 /*
2 * Copyright 2004-2009 Analog Devices Inc.
3 * 2005 National ICT Australia (NICTA)
4 * Aidan Williams <aidan@nicta.com.au>
5 *
6 * Licensed under the GPL-2 or later.
7 */
8
9 #include <linux/device.h>
10 #include <linux/platform_device.h>
11 #include <linux/mtd/mtd.h>
12 #include <linux/mtd/partitions.h>
13 #include <linux/mtd/physmap.h>
14 #include <linux/spi/spi.h>
15 #include <linux/spi/flash.h>
16 #include <linux/irq.h>
17 #include <linux/i2c.h>
18 #include <linux/interrupt.h>
19 #include <linux/usb/musb.h>
20 #include <asm/bfin6xx_spi.h>
21 #include <asm/dma.h>
22 #include <asm/gpio.h>
23 #include <asm/nand.h>
24 #include <asm/dpmc.h>
25 #include <asm/portmux.h>
26 #include <asm/bfin_sdh.h>
27 #include <linux/input.h>
28 #include <linux/spi/ad7877.h>
29
30 /*
31 * Name the Board for the /proc/cpuinfo
32 */
33 const char bfin_board_name[] = "ADI BF609-EZKIT";
34
35 /*
36 * Driver needs to know address, irq and flag pin.
37 */
38
39 #if defined(CONFIG_USB_ISP1760_HCD) || defined(CONFIG_USB_ISP1760_HCD_MODULE)
40 #include <linux/usb/isp1760.h>
41 static struct resource bfin_isp1760_resources[] = {
42 [0] = {
43 .start = 0x2C0C0000,
44 .end = 0x2C0C0000 + 0xfffff,
45 .flags = IORESOURCE_MEM,
46 },
47 [1] = {
48 .start = IRQ_PG7,
49 .end = IRQ_PG7,
50 .flags = IORESOURCE_IRQ,
51 },
52 };
53
54 static struct isp1760_platform_data isp1760_priv = {
55 .is_isp1761 = 0,
56 .bus_width_16 = 1,
57 .port1_otg = 0,
58 .analog_oc = 0,
59 .dack_polarity_high = 0,
60 .dreq_polarity_high = 0,
61 };
62
63 static struct platform_device bfin_isp1760_device = {
64 .name = "isp1760",
65 .id = 0,
66 .dev = {
67 .platform_data = &isp1760_priv,
68 },
69 .num_resources = ARRAY_SIZE(bfin_isp1760_resources),
70 .resource = bfin_isp1760_resources,
71 };
72 #endif
73
74 #if defined(CONFIG_INPUT_BFIN_ROTARY) || defined(CONFIG_INPUT_BFIN_ROTARY_MODULE)
75 #include <asm/bfin_rotary.h>
76
77 static struct bfin_rotary_platform_data bfin_rotary_data = {
78 /*.rotary_up_key = KEY_UP,*/
79 /*.rotary_down_key = KEY_DOWN,*/
80 .rotary_rel_code = REL_WHEEL,
81 .rotary_button_key = KEY_ENTER,
82 .debounce = 10, /* 0..17 */
83 .mode = ROT_QUAD_ENC | ROT_DEBE,
84 };
85
86 static struct resource bfin_rotary_resources[] = {
87 {
88 .start = IRQ_CNT,
89 .end = IRQ_CNT,
90 .flags = IORESOURCE_IRQ,
91 },
92 };
93
94 static struct platform_device bfin_rotary_device = {
95 .name = "bfin-rotary",
96 .id = -1,
97 .num_resources = ARRAY_SIZE(bfin_rotary_resources),
98 .resource = bfin_rotary_resources,
99 .dev = {
100 .platform_data = &bfin_rotary_data,
101 },
102 };
103 #endif
104
105 #if defined(CONFIG_STMMAC_ETH) || defined(CONFIG_STMMAC_ETH_MODULE)
106 #include <linux/stmmac.h>
107
108 static unsigned short pins[] = P_RMII0;
109
110 static struct stmmac_mdio_bus_data phy_private_data = {
111 .bus_id = 0,
112 .phy_mask = 1,
113 };
114
115 static struct plat_stmmacenet_data eth_private_data = {
116 .bus_id = 0,
117 .enh_desc = 1,
118 .phy_addr = 1,
119 .mdio_bus_data = &phy_private_data,
120 };
121
122 static struct platform_device bfin_eth_device = {
123 .name = "stmmaceth",
124 .id = 0,
125 .num_resources = 2,
126 .resource = (struct resource[]) {
127 {
128 .start = EMAC0_MACCFG,
129 .end = EMAC0_MACCFG + 0x1274,
130 .flags = IORESOURCE_MEM,
131 },
132 {
133 .name = "macirq",
134 .start = IRQ_EMAC0_STAT,
135 .end = IRQ_EMAC0_STAT,
136 .flags = IORESOURCE_IRQ,
137 },
138 },
139 .dev = {
140 .power.can_wakeup = 1,
141 .platform_data = &eth_private_data,
142 }
143 };
144 #endif
145
146 #if defined(CONFIG_INPUT_ADXL34X) || defined(CONFIG_INPUT_ADXL34X_MODULE)
147 #include <linux/input/adxl34x.h>
148 static const struct adxl34x_platform_data adxl34x_info = {
149 .x_axis_offset = 0,
150 .y_axis_offset = 0,
151 .z_axis_offset = 0,
152 .tap_threshold = 0x31,
153 .tap_duration = 0x10,
154 .tap_latency = 0x60,
155 .tap_window = 0xF0,
156 .tap_axis_control = ADXL_TAP_X_EN | ADXL_TAP_Y_EN | ADXL_TAP_Z_EN,
157 .act_axis_control = 0xFF,
158 .activity_threshold = 5,
159 .inactivity_threshold = 3,
160 .inactivity_time = 4,
161 .free_fall_threshold = 0x7,
162 .free_fall_time = 0x20,
163 .data_rate = 0x8,
164 .data_range = ADXL_FULL_RES,
165
166 .ev_type = EV_ABS,
167 .ev_code_x = ABS_X, /* EV_REL */
168 .ev_code_y = ABS_Y, /* EV_REL */
169 .ev_code_z = ABS_Z, /* EV_REL */
170
171 .ev_code_tap = {BTN_TOUCH, BTN_TOUCH, BTN_TOUCH}, /* EV_KEY x,y,z */
172
173 /* .ev_code_ff = KEY_F,*/ /* EV_KEY */
174 /* .ev_code_act_inactivity = KEY_A,*/ /* EV_KEY */
175 .power_mode = ADXL_AUTO_SLEEP | ADXL_LINK,
176 .fifo_mode = ADXL_FIFO_STREAM,
177 .orientation_enable = ADXL_EN_ORIENTATION_3D,
178 .deadzone_angle = ADXL_DEADZONE_ANGLE_10p8,
179 .divisor_length = ADXL_LP_FILTER_DIVISOR_16,
180 /* EV_KEY {+Z, +Y, +X, -X, -Y, -Z} */
181 .ev_codes_orient_3d = {BTN_Z, BTN_Y, BTN_X, BTN_A, BTN_B, BTN_C},
182 };
183 #endif
184
185 #if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
186 static struct platform_device rtc_device = {
187 .name = "rtc-bfin",
188 .id = -1,
189 };
190 #endif
191
192 #if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
193 #ifdef CONFIG_SERIAL_BFIN_UART0
194 static struct resource bfin_uart0_resources[] = {
195 {
196 .start = UART0_REVID,
197 .end = UART0_RXDIV+4,
198 .flags = IORESOURCE_MEM,
199 },
200 {
201 .start = IRQ_UART0_TX,
202 .end = IRQ_UART0_TX,
203 .flags = IORESOURCE_IRQ,
204 },
205 {
206 .start = IRQ_UART0_RX,
207 .end = IRQ_UART0_RX,
208 .flags = IORESOURCE_IRQ,
209 },
210 {
211 .start = IRQ_UART0_STAT,
212 .end = IRQ_UART0_STAT,
213 .flags = IORESOURCE_IRQ,
214 },
215 {
216 .start = CH_UART0_TX,
217 .end = CH_UART0_TX,
218 .flags = IORESOURCE_DMA,
219 },
220 {
221 .start = CH_UART0_RX,
222 .end = CH_UART0_RX,
223 .flags = IORESOURCE_DMA,
224 },
225 #ifdef CONFIG_BFIN_UART0_CTSRTS
226 { /* CTS pin -- 0 means not supported */
227 .start = GPIO_PD10,
228 .end = GPIO_PD10,
229 .flags = IORESOURCE_IO,
230 },
231 { /* RTS pin -- 0 means not supported */
232 .start = GPIO_PD9,
233 .end = GPIO_PD9,
234 .flags = IORESOURCE_IO,
235 },
236 #endif
237 };
238
239 static unsigned short bfin_uart0_peripherals[] = {
240 P_UART0_TX, P_UART0_RX,
241 #ifdef CONFIG_BFIN_UART0_CTSRTS
242 P_UART0_RTS, P_UART0_CTS,
243 #endif
244 0
245 };
246
247 static struct platform_device bfin_uart0_device = {
248 .name = "bfin-uart",
249 .id = 0,
250 .num_resources = ARRAY_SIZE(bfin_uart0_resources),
251 .resource = bfin_uart0_resources,
252 .dev = {
253 .platform_data = &bfin_uart0_peripherals, /* Passed to driver */
254 },
255 };
256 #endif
257 #ifdef CONFIG_SERIAL_BFIN_UART1
258 static struct resource bfin_uart1_resources[] = {
259 {
260 .start = UART1_REVID,
261 .end = UART1_RXDIV+4,
262 .flags = IORESOURCE_MEM,
263 },
264 {
265 .start = IRQ_UART1_TX,
266 .end = IRQ_UART1_TX,
267 .flags = IORESOURCE_IRQ,
268 },
269 {
270 .start = IRQ_UART1_RX,
271 .end = IRQ_UART1_RX,
272 .flags = IORESOURCE_IRQ,
273 },
274 {
275 .start = IRQ_UART1_STAT,
276 .end = IRQ_UART1_STAT,
277 .flags = IORESOURCE_IRQ,
278 },
279 {
280 .start = CH_UART1_TX,
281 .end = CH_UART1_TX,
282 .flags = IORESOURCE_DMA,
283 },
284 {
285 .start = CH_UART1_RX,
286 .end = CH_UART1_RX,
287 .flags = IORESOURCE_DMA,
288 },
289 #ifdef CONFIG_BFIN_UART1_CTSRTS
290 { /* CTS pin -- 0 means not supported */
291 .start = GPIO_PG13,
292 .end = GPIO_PG13,
293 .flags = IORESOURCE_IO,
294 },
295 { /* RTS pin -- 0 means not supported */
296 .start = GPIO_PG10,
297 .end = GPIO_PG10,
298 .flags = IORESOURCE_IO,
299 },
300 #endif
301 };
302
303 static unsigned short bfin_uart1_peripherals[] = {
304 P_UART1_TX, P_UART1_RX,
305 #ifdef CONFIG_BFIN_UART1_CTSRTS
306 P_UART1_RTS, P_UART1_CTS,
307 #endif
308 0
309 };
310
311 static struct platform_device bfin_uart1_device = {
312 .name = "bfin-uart",
313 .id = 1,
314 .num_resources = ARRAY_SIZE(bfin_uart1_resources),
315 .resource = bfin_uart1_resources,
316 .dev = {
317 .platform_data = &bfin_uart1_peripherals, /* Passed to driver */
318 },
319 };
320 #endif
321 #endif
322
323 #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
324 #ifdef CONFIG_BFIN_SIR0
325 static struct resource bfin_sir0_resources[] = {
326 {
327 .start = 0xFFC00400,
328 .end = 0xFFC004FF,
329 .flags = IORESOURCE_MEM,
330 },
331 {
332 .start = IRQ_UART0_TX,
333 .end = IRQ_UART0_TX+1,
334 .flags = IORESOURCE_IRQ,
335 },
336 {
337 .start = CH_UART0_TX,
338 .end = CH_UART0_TX+1,
339 .flags = IORESOURCE_DMA,
340 },
341 };
342 static struct platform_device bfin_sir0_device = {
343 .name = "bfin_sir",
344 .id = 0,
345 .num_resources = ARRAY_SIZE(bfin_sir0_resources),
346 .resource = bfin_sir0_resources,
347 };
348 #endif
349 #ifdef CONFIG_BFIN_SIR1
350 static struct resource bfin_sir1_resources[] = {
351 {
352 .start = 0xFFC02000,
353 .end = 0xFFC020FF,
354 .flags = IORESOURCE_MEM,
355 },
356 {
357 .start = IRQ_UART1_TX,
358 .end = IRQ_UART1_TX+1,
359 .flags = IORESOURCE_IRQ,
360 },
361 {
362 .start = CH_UART1_TX,
363 .end = CH_UART1_TX+1,
364 .flags = IORESOURCE_DMA,
365 },
366 };
367 static struct platform_device bfin_sir1_device = {
368 .name = "bfin_sir",
369 .id = 1,
370 .num_resources = ARRAY_SIZE(bfin_sir1_resources),
371 .resource = bfin_sir1_resources,
372 };
373 #endif
374 #endif
375
376 #if defined(CONFIG_USB_MUSB_HDRC) || defined(CONFIG_USB_MUSB_HDRC_MODULE)
377 static struct resource musb_resources[] = {
378 [0] = {
379 .start = 0xFFCC1000,
380 .end = 0xFFCC1398,
381 .flags = IORESOURCE_MEM,
382 },
383 [1] = { /* general IRQ */
384 .start = IRQ_USB_STAT,
385 .end = IRQ_USB_STAT,
386 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
387 .name = "mc"
388 },
389 [2] = { /* DMA IRQ */
390 .start = IRQ_USB_DMA,
391 .end = IRQ_USB_DMA,
392 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
393 .name = "dma"
394 },
395 };
396
397 static struct musb_hdrc_config musb_config = {
398 .multipoint = 1,
399 .dyn_fifo = 0,
400 .dma = 1,
401 .num_eps = 16,
402 .dma_channels = 8,
403 .clkin = 48, /* musb CLKIN in MHZ */
404 };
405
406 static struct musb_hdrc_platform_data musb_plat = {
407 #if defined(CONFIG_USB_MUSB_HDRC) && defined(CONFIG_USB_GADGET_MUSB_HDRC)
408 .mode = MUSB_OTG,
409 #elif defined(CONFIG_USB_MUSB_HDRC)
410 .mode = MUSB_HOST,
411 #elif defined(CONFIG_USB_GADGET_MUSB_HDRC)
412 .mode = MUSB_PERIPHERAL,
413 #endif
414 .config = &musb_config,
415 };
416
417 static u64 musb_dmamask = ~(u32)0;
418
419 static struct platform_device musb_device = {
420 .name = "musb-blackfin",
421 .id = 0,
422 .dev = {
423 .dma_mask = &musb_dmamask,
424 .coherent_dma_mask = 0xffffffff,
425 .platform_data = &musb_plat,
426 },
427 .num_resources = ARRAY_SIZE(musb_resources),
428 .resource = musb_resources,
429 };
430 #endif
431
432 #if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
433 #ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
434 static struct resource bfin_sport0_uart_resources[] = {
435 {
436 .start = SPORT0_TCR1,
437 .end = SPORT0_MRCS3+4,
438 .flags = IORESOURCE_MEM,
439 },
440 {
441 .start = IRQ_SPORT0_RX,
442 .end = IRQ_SPORT0_RX+1,
443 .flags = IORESOURCE_IRQ,
444 },
445 {
446 .start = IRQ_SPORT0_ERROR,
447 .end = IRQ_SPORT0_ERROR,
448 .flags = IORESOURCE_IRQ,
449 },
450 };
451
452 static unsigned short bfin_sport0_peripherals[] = {
453 P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
454 P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
455 };
456
457 static struct platform_device bfin_sport0_uart_device = {
458 .name = "bfin-sport-uart",
459 .id = 0,
460 .num_resources = ARRAY_SIZE(bfin_sport0_uart_resources),
461 .resource = bfin_sport0_uart_resources,
462 .dev = {
463 .platform_data = &bfin_sport0_peripherals, /* Passed to driver */
464 },
465 };
466 #endif
467 #ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
468 static struct resource bfin_sport1_uart_resources[] = {
469 {
470 .start = SPORT1_TCR1,
471 .end = SPORT1_MRCS3+4,
472 .flags = IORESOURCE_MEM,
473 },
474 {
475 .start = IRQ_SPORT1_RX,
476 .end = IRQ_SPORT1_RX+1,
477 .flags = IORESOURCE_IRQ,
478 },
479 {
480 .start = IRQ_SPORT1_ERROR,
481 .end = IRQ_SPORT1_ERROR,
482 .flags = IORESOURCE_IRQ,
483 },
484 };
485
486 static unsigned short bfin_sport1_peripherals[] = {
487 P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
488 P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
489 };
490
491 static struct platform_device bfin_sport1_uart_device = {
492 .name = "bfin-sport-uart",
493 .id = 1,
494 .num_resources = ARRAY_SIZE(bfin_sport1_uart_resources),
495 .resource = bfin_sport1_uart_resources,
496 .dev = {
497 .platform_data = &bfin_sport1_peripherals, /* Passed to driver */
498 },
499 };
500 #endif
501 #ifdef CONFIG_SERIAL_BFIN_SPORT2_UART
502 static struct resource bfin_sport2_uart_resources[] = {
503 {
504 .start = SPORT2_TCR1,
505 .end = SPORT2_MRCS3+4,
506 .flags = IORESOURCE_MEM,
507 },
508 {
509 .start = IRQ_SPORT2_RX,
510 .end = IRQ_SPORT2_RX+1,
511 .flags = IORESOURCE_IRQ,
512 },
513 {
514 .start = IRQ_SPORT2_ERROR,
515 .end = IRQ_SPORT2_ERROR,
516 .flags = IORESOURCE_IRQ,
517 },
518 };
519
520 static unsigned short bfin_sport2_peripherals[] = {
521 P_SPORT2_TFS, P_SPORT2_DTPRI, P_SPORT2_TSCLK, P_SPORT2_RFS,
522 P_SPORT2_DRPRI, P_SPORT2_RSCLK, P_SPORT2_DRSEC, P_SPORT2_DTSEC, 0
523 };
524
525 static struct platform_device bfin_sport2_uart_device = {
526 .name = "bfin-sport-uart",
527 .id = 2,
528 .num_resources = ARRAY_SIZE(bfin_sport2_uart_resources),
529 .resource = bfin_sport2_uart_resources,
530 .dev = {
531 .platform_data = &bfin_sport2_peripherals, /* Passed to driver */
532 },
533 };
534 #endif
535 #endif
536
537 #if defined(CONFIG_CAN_BFIN) || defined(CONFIG_CAN_BFIN_MODULE)
538
539 static unsigned short bfin_can0_peripherals[] = {
540 P_CAN0_RX, P_CAN0_TX, 0
541 };
542
543 static struct resource bfin_can0_resources[] = {
544 {
545 .start = 0xFFC00A00,
546 .end = 0xFFC00FFF,
547 .flags = IORESOURCE_MEM,
548 },
549 {
550 .start = IRQ_CAN0_RX,
551 .end = IRQ_CAN0_RX,
552 .flags = IORESOURCE_IRQ,
553 },
554 {
555 .start = IRQ_CAN0_TX,
556 .end = IRQ_CAN0_TX,
557 .flags = IORESOURCE_IRQ,
558 },
559 {
560 .start = IRQ_CAN0_STAT,
561 .end = IRQ_CAN0_STAT,
562 .flags = IORESOURCE_IRQ,
563 },
564 };
565
566 static struct platform_device bfin_can0_device = {
567 .name = "bfin_can",
568 .id = 0,
569 .num_resources = ARRAY_SIZE(bfin_can0_resources),
570 .resource = bfin_can0_resources,
571 .dev = {
572 .platform_data = &bfin_can0_peripherals, /* Passed to driver */
573 },
574 };
575
576 #endif
577
578 #if defined(CONFIG_MTD_NAND_BF5XX) || defined(CONFIG_MTD_NAND_BF5XX_MODULE)
579 static struct mtd_partition partition_info[] = {
580 {
581 .name = "bootloader(nand)",
582 .offset = 0,
583 .size = 0x80000,
584 }, {
585 .name = "linux kernel(nand)",
586 .offset = MTDPART_OFS_APPEND,
587 .size = 4 * 1024 * 1024,
588 },
589 {
590 .name = "file system(nand)",
591 .offset = MTDPART_OFS_APPEND,
592 .size = MTDPART_SIZ_FULL,
593 },
594 };
595
596 static struct bf5xx_nand_platform bfin_nand_platform = {
597 .data_width = NFC_NWIDTH_8,
598 .partitions = partition_info,
599 .nr_partitions = ARRAY_SIZE(partition_info),
600 .rd_dly = 3,
601 .wr_dly = 3,
602 };
603
604 static struct resource bfin_nand_resources[] = {
605 {
606 .start = 0xFFC03B00,
607 .end = 0xFFC03B4F,
608 .flags = IORESOURCE_MEM,
609 },
610 {
611 .start = CH_NFC,
612 .end = CH_NFC,
613 .flags = IORESOURCE_IRQ,
614 },
615 };
616
617 static struct platform_device bfin_nand_device = {
618 .name = "bfin-nand",
619 .id = 0,
620 .num_resources = ARRAY_SIZE(bfin_nand_resources),
621 .resource = bfin_nand_resources,
622 .dev = {
623 .platform_data = &bfin_nand_platform,
624 },
625 };
626 #endif
627
628 #if defined(CONFIG_SDH_BFIN) || defined(CONFIG_SDH_BFIN_MODULE)
629
630 static struct bfin_sd_host bfin_sdh_data = {
631 .dma_chan = CH_RSI,
632 .irq_int0 = IRQ_RSI_INT0,
633 .pin_req = {P_RSI_DATA0, P_RSI_DATA1, P_RSI_DATA2, P_RSI_DATA3, P_RSI_CMD, P_RSI_CLK, 0},
634 };
635
636 static struct platform_device bfin_sdh_device = {
637 .name = "bfin-sdh",
638 .id = 0,
639 .dev = {
640 .platform_data = &bfin_sdh_data,
641 },
642 };
643 #endif
644
645 #if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
646 static struct mtd_partition ezkit_partitions[] = {
647 {
648 .name = "bootloader(nor)",
649 .size = 0x80000,
650 .offset = 0,
651 }, {
652 .name = "linux kernel(nor)",
653 .size = 0x400000,
654 .offset = MTDPART_OFS_APPEND,
655 }, {
656 .name = "file system(nor)",
657 .size = 0x1000000 - 0x80000 - 0x400000,
658 .offset = MTDPART_OFS_APPEND,
659 },
660 };
661
662 int bf609_nor_flash_init(struct platform_device *dev)
663 {
664 #define CONFIG_SMC_GCTL_VAL 0x00000010
665 const unsigned short pins[] = {
666 P_A3, P_A4, P_A5, P_A6, P_A7, P_A8, P_A9, P_A10, P_A11, P_A12,
667 P_A13, P_A14, P_A15, P_A16, P_A17, P_A18, P_A19, P_A20, P_A21,
668 P_A22, P_A23, P_A24, P_A25, P_NORCK, 0,
669 };
670
671 peripheral_request_list(pins, "smc0");
672
673 bfin_write32(SMC_GCTL, CONFIG_SMC_GCTL_VAL);
674 bfin_write32(SMC_B0CTL, 0x01002011);
675 bfin_write32(SMC_B0TIM, 0x08170977);
676 bfin_write32(SMC_B0ETIM, 0x00092231);
677 return 0;
678 }
679
680 static struct physmap_flash_data ezkit_flash_data = {
681 .width = 2,
682 .parts = ezkit_partitions,
683 .init = bf609_nor_flash_init,
684 .nr_parts = ARRAY_SIZE(ezkit_partitions),
685 #ifdef CONFIG_ROMKERNEL
686 .probe_type = "map_rom",
687 #endif
688 };
689
690 static struct resource ezkit_flash_resource = {
691 .start = 0xb0000000,
692 .end = 0xb0ffffff,
693 .flags = IORESOURCE_MEM,
694 };
695
696 static struct platform_device ezkit_flash_device = {
697 .name = "physmap-flash",
698 .id = 0,
699 .dev = {
700 .platform_data = &ezkit_flash_data,
701 },
702 .num_resources = 1,
703 .resource = &ezkit_flash_resource,
704 };
705 #endif
706
707 #if defined(CONFIG_MTD_M25P80) \
708 || defined(CONFIG_MTD_M25P80_MODULE)
709 /* SPI flash chip (w25q32) */
710 static struct mtd_partition bfin_spi_flash_partitions[] = {
711 {
712 .name = "bootloader(spi)",
713 .size = 0x00080000,
714 .offset = 0,
715 .mask_flags = MTD_CAP_ROM
716 }, {
717 .name = "linux kernel(spi)",
718 .size = 0x00180000,
719 .offset = MTDPART_OFS_APPEND,
720 }, {
721 .name = "file system(spi)",
722 .size = MTDPART_SIZ_FULL,
723 .offset = MTDPART_OFS_APPEND,
724 }
725 };
726
727 static struct flash_platform_data bfin_spi_flash_data = {
728 .name = "m25p80",
729 .parts = bfin_spi_flash_partitions,
730 .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
731 .type = "w25q32",
732 };
733
734 static struct bfin6xx_spi_chip spi_flash_chip_info = {
735 .enable_dma = true, /* use dma transfer with this chip*/
736 };
737 #endif
738
739 #if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
740 static struct bfin6xx_spi_chip spidev_chip_info = {
741 .enable_dma = true,
742 };
743 #endif
744
745 #if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE)
746 static struct platform_device bfin_i2s_pcm = {
747 .name = "bfin-i2s-pcm-audio",
748 .id = -1,
749 };
750 #endif
751
752 #if defined(CONFIG_SND_BF6XX_SOC_I2S) || \
753 defined(CONFIG_SND_BF6XX_SOC_I2S_MODULE)
754 #include <asm/bfin_sport3.h>
755 static struct resource bfin_snd_resources[] = {
756 {
757 .start = SPORT0_CTL_A,
758 .end = SPORT0_CTL_A,
759 .flags = IORESOURCE_MEM,
760 },
761 {
762 .start = SPORT0_CTL_B,
763 .end = SPORT0_CTL_B,
764 .flags = IORESOURCE_MEM,
765 },
766 {
767 .start = CH_SPORT0_TX,
768 .end = CH_SPORT0_TX,
769 .flags = IORESOURCE_DMA,
770 },
771 {
772 .start = CH_SPORT0_RX,
773 .end = CH_SPORT0_RX,
774 .flags = IORESOURCE_DMA,
775 },
776 {
777 .start = IRQ_SPORT0_TX_STAT,
778 .end = IRQ_SPORT0_TX_STAT,
779 .flags = IORESOURCE_IRQ,
780 },
781 {
782 .start = IRQ_SPORT0_RX_STAT,
783 .end = IRQ_SPORT0_RX_STAT,
784 .flags = IORESOURCE_IRQ,
785 },
786 };
787
788 static const unsigned short bfin_snd_pin[] = {
789 P_SPORT0_ACLK, P_SPORT0_AFS, P_SPORT0_AD0, P_SPORT0_BCLK,
790 P_SPORT0_BFS, P_SPORT0_BD0, 0,
791 };
792
793 static struct bfin_snd_platform_data bfin_snd_data = {
794 .pin_req = bfin_snd_pin,
795 };
796
797 static struct platform_device bfin_i2s = {
798 .name = "bfin-i2s",
799 .num_resources = ARRAY_SIZE(bfin_snd_resources),
800 .resource = bfin_snd_resources,
801 .dev = {
802 .platform_data = &bfin_snd_data,
803 },
804 };
805 #endif
806
807 #if defined(CONFIG_SND_SOC_BFIN_EVAL_ADAU1X61) || \
808 defined(CONFIG_SND_SOC_BFIN_EVAL_ADAU1X61_MODULE)
809 static struct platform_device adau1761_device = {
810 .name = "bfin-eval-adau1x61",
811 };
812 #endif
813
814 #if defined(CONFIG_SND_SOC_ADAU1761) || defined(CONFIG_SND_SOC_ADAU1761_MODULE)
815 #include <sound/adau17x1.h>
816 static struct adau1761_platform_data adau1761_info = {
817 .lineout_mode = ADAU1761_OUTPUT_MODE_LINE,
818 .headphone_mode = ADAU1761_OUTPUT_MODE_HEADPHONE_CAPLESS,
819 };
820 #endif
821
822 #if defined(CONFIG_VIDEO_BLACKFIN_CAPTURE) \
823 || defined(CONFIG_VIDEO_BLACKFIN_CAPTURE_MODULE)
824 #include <linux/videodev2.h>
825 #include <media/blackfin/bfin_capture.h>
826 #include <media/blackfin/ppi.h>
827
828 static const unsigned short ppi_req[] = {
829 P_PPI0_D0, P_PPI0_D1, P_PPI0_D2, P_PPI0_D3,
830 P_PPI0_D4, P_PPI0_D5, P_PPI0_D6, P_PPI0_D7,
831 P_PPI0_D8, P_PPI0_D9, P_PPI0_D10, P_PPI0_D11,
832 P_PPI0_D12, P_PPI0_D13, P_PPI0_D14, P_PPI0_D15,
833 #if !defined(CONFIG_VIDEO_VS6624) && !defined(CONFIG_VIDEO_VS6624_MODULE)
834 P_PPI0_D16, P_PPI0_D17, P_PPI0_D18, P_PPI0_D19,
835 P_PPI0_D20, P_PPI0_D21, P_PPI0_D22, P_PPI0_D23,
836 #endif
837 P_PPI0_CLK, P_PPI0_FS1, P_PPI0_FS2,
838 0,
839 };
840
841 static const struct ppi_info ppi_info = {
842 .type = PPI_TYPE_EPPI3,
843 .dma_ch = CH_EPPI0_CH0,
844 .irq_err = IRQ_EPPI0_STAT,
845 .base = (void __iomem *)EPPI0_STAT,
846 .pin_req = ppi_req,
847 };
848
849 #if defined(CONFIG_VIDEO_VS6624) \
850 || defined(CONFIG_VIDEO_VS6624_MODULE)
851 static struct v4l2_input vs6624_inputs[] = {
852 {
853 .index = 0,
854 .name = "Camera",
855 .type = V4L2_INPUT_TYPE_CAMERA,
856 .std = V4L2_STD_UNKNOWN,
857 },
858 };
859
860 static struct bcap_route vs6624_routes[] = {
861 {
862 .input = 0,
863 .output = 0,
864 },
865 };
866
867 static const unsigned vs6624_ce_pin = GPIO_PE4;
868
869 static struct bfin_capture_config bfin_capture_data = {
870 .card_name = "BF609",
871 .inputs = vs6624_inputs,
872 .num_inputs = ARRAY_SIZE(vs6624_inputs),
873 .routes = vs6624_routes,
874 .i2c_adapter_id = 0,
875 .board_info = {
876 .type = "vs6624",
877 .addr = 0x10,
878 .platform_data = (void *)&vs6624_ce_pin,
879 },
880 .ppi_info = &ppi_info,
881 .ppi_control = (PACK_EN | DLEN_8 | EPPI_CTL_FS1HI_FS2HI
882 | EPPI_CTL_POLC3 | EPPI_CTL_SYNC2 | EPPI_CTL_NON656),
883 .blank_pixels = 4,
884 };
885 #endif
886
887 #if defined(CONFIG_VIDEO_ADV7842) \
888 || defined(CONFIG_VIDEO_ADV7842_MODULE)
889 #include <media/adv7842.h>
890
891 static struct v4l2_input adv7842_inputs[] = {
892 {
893 .index = 0,
894 .name = "Composite",
895 .type = V4L2_INPUT_TYPE_CAMERA,
896 .std = V4L2_STD_ALL,
897 .capabilities = V4L2_IN_CAP_STD,
898 },
899 {
900 .index = 1,
901 .name = "S-Video",
902 .type = V4L2_INPUT_TYPE_CAMERA,
903 .std = V4L2_STD_ALL,
904 .capabilities = V4L2_IN_CAP_STD,
905 },
906 {
907 .index = 2,
908 .name = "Component",
909 .type = V4L2_INPUT_TYPE_CAMERA,
910 .capabilities = V4L2_IN_CAP_CUSTOM_TIMINGS,
911 },
912 {
913 .index = 3,
914 .name = "VGA",
915 .type = V4L2_INPUT_TYPE_CAMERA,
916 .capabilities = V4L2_IN_CAP_CUSTOM_TIMINGS,
917 },
918 {
919 .index = 4,
920 .name = "HDMI",
921 .type = V4L2_INPUT_TYPE_CAMERA,
922 .capabilities = V4L2_IN_CAP_CUSTOM_TIMINGS,
923 },
924 };
925
926 static struct bcap_route adv7842_routes[] = {
927 {
928 .input = 3,
929 .output = 0,
930 .ppi_control = (PACK_EN | DLEN_8 | EPPI_CTL_FLDSEL
931 | EPPI_CTL_ACTIVE656),
932 },
933 {
934 .input = 4,
935 .output = 0,
936 },
937 {
938 .input = 2,
939 .output = 0,
940 },
941 {
942 .input = 1,
943 .output = 0,
944 },
945 {
946 .input = 0,
947 .output = 1,
948 .ppi_control = (EPPI_CTL_SPLTWRD | PACK_EN | DLEN_16
949 | EPPI_CTL_FS1LO_FS2LO | EPPI_CTL_POLC2
950 | EPPI_CTL_SYNC2 | EPPI_CTL_NON656),
951 },
952 };
953
954 static struct adv7842_output_format adv7842_opf[] = {
955 {
956 .op_ch_sel = ADV7842_OP_CH_SEL_BRG,
957 .op_format_sel = ADV7842_OP_FORMAT_SEL_SDR_ITU656_8,
958 .op_656_range = 1,
959 .blank_data = 1,
960 .insert_av_codes = 1,
961 },
962 {
963 .op_ch_sel = ADV7842_OP_CH_SEL_RGB,
964 .op_format_sel = ADV7842_OP_FORMAT_SEL_SDR_ITU656_16,
965 .op_656_range = 1,
966 .blank_data = 1,
967 },
968 };
969
970 static struct adv7842_platform_data adv7842_data = {
971 .opf = adv7842_opf,
972 .num_opf = ARRAY_SIZE(adv7842_opf),
973 .ain_sel = ADV7842_AIN10_11_12_NC_SYNC_4_1,
974 .prim_mode = ADV7842_PRIM_MODE_SDP,
975 .vid_std_select = ADV7842_SDP_VID_STD_CVBS_SD_4x1,
976 .inp_color_space = ADV7842_INP_COLOR_SPACE_AUTO,
977 .i2c_sdp_io = 0x30,
978 .i2c_sdp = 0x31,
979 .i2c_cp = 0x32,
980 .i2c_vdp = 0x33,
981 .i2c_afe = 0x34,
982 .i2c_hdmi = 0x35,
983 .i2c_repeater = 0x36,
984 .i2c_edid = 0x37,
985 .i2c_infoframe = 0x39,
986 .i2c_cec = 0x3a,
987 .i2c_avlink = 0x3b,
988 .i2c_ex = 0x26,
989 };
990
991 static struct bfin_capture_config bfin_capture_data = {
992 .card_name = "BF609",
993 .inputs = adv7842_inputs,
994 .num_inputs = ARRAY_SIZE(adv7842_inputs),
995 .routes = adv7842_routes,
996 .i2c_adapter_id = 0,
997 .board_info = {
998 .type = "adv7842",
999 .addr = 0x20,
1000 .platform_data = (void *)&adv7842_data,
1001 },
1002 .ppi_info = &ppi_info,
1003 .ppi_control = (PACK_EN | DLEN_8 | EPPI_CTL_FLDSEL
1004 | EPPI_CTL_ACTIVE656),
1005 };
1006 #endif
1007
1008 static struct platform_device bfin_capture_device = {
1009 .name = "bfin_capture",
1010 .dev = {
1011 .platform_data = &bfin_capture_data,
1012 },
1013 };
1014 #endif
1015
1016 #if defined(CONFIG_BFIN_CRC)
1017 #define BFIN_CRC_NAME "bfin-crc"
1018
1019 static struct resource bfin_crc0_resources[] = {
1020 {
1021 .start = REG_CRC0_CTL,
1022 .end = REG_CRC0_REVID+4,
1023 .flags = IORESOURCE_MEM,
1024 },
1025 {
1026 .start = IRQ_CRC0_DCNTEXP,
1027 .end = IRQ_CRC0_DCNTEXP,
1028 .flags = IORESOURCE_IRQ,
1029 },
1030 {
1031 .start = CH_MEM_STREAM0_SRC_CRC0,
1032 .end = CH_MEM_STREAM0_SRC_CRC0,
1033 .flags = IORESOURCE_DMA,
1034 },
1035 {
1036 .start = CH_MEM_STREAM0_DEST_CRC0,
1037 .end = CH_MEM_STREAM0_DEST_CRC0,
1038 .flags = IORESOURCE_DMA,
1039 },
1040 };
1041
1042 static struct platform_device bfin_crc0_device = {
1043 .name = BFIN_CRC_NAME,
1044 .id = 0,
1045 .num_resources = ARRAY_SIZE(bfin_crc0_resources),
1046 .resource = bfin_crc0_resources,
1047 };
1048
1049 static struct resource bfin_crc1_resources[] = {
1050 {
1051 .start = REG_CRC1_CTL,
1052 .end = REG_CRC1_REVID+4,
1053 .flags = IORESOURCE_MEM,
1054 },
1055 {
1056 .start = IRQ_CRC1_DCNTEXP,
1057 .end = IRQ_CRC1_DCNTEXP,
1058 .flags = IORESOURCE_IRQ,
1059 },
1060 {
1061 .start = CH_MEM_STREAM1_SRC_CRC1,
1062 .end = CH_MEM_STREAM1_SRC_CRC1,
1063 .flags = IORESOURCE_DMA,
1064 },
1065 {
1066 .start = CH_MEM_STREAM1_DEST_CRC1,
1067 .end = CH_MEM_STREAM1_DEST_CRC1,
1068 .flags = IORESOURCE_DMA,
1069 },
1070 };
1071
1072 static struct platform_device bfin_crc1_device = {
1073 .name = BFIN_CRC_NAME,
1074 .id = 1,
1075 .num_resources = ARRAY_SIZE(bfin_crc1_resources),
1076 .resource = bfin_crc1_resources,
1077 };
1078 #endif
1079
1080 #if defined(CONFIG_CRYPTO_DEV_BFIN_CRC)
1081 #define BFIN_CRYPTO_CRC_NAME "bfin-hmac-crc"
1082 #define BFIN_CRYPTO_CRC_POLY_DATA 0x5c5c5c5c
1083
1084 static struct resource bfin_crypto_crc_resources[] = {
1085 {
1086 .start = REG_CRC0_CTL,
1087 .end = REG_CRC0_REVID+4,
1088 .flags = IORESOURCE_MEM,
1089 },
1090 {
1091 .start = IRQ_CRC0_DCNTEXP,
1092 .end = IRQ_CRC0_DCNTEXP,
1093 .flags = IORESOURCE_IRQ,
1094 },
1095 {
1096 .start = CH_MEM_STREAM0_SRC_CRC0,
1097 .end = CH_MEM_STREAM0_SRC_CRC0,
1098 .flags = IORESOURCE_DMA,
1099 },
1100 };
1101
1102 static struct platform_device bfin_crypto_crc_device = {
1103 .name = BFIN_CRYPTO_CRC_NAME,
1104 .id = 0,
1105 .num_resources = ARRAY_SIZE(bfin_crypto_crc_resources),
1106 .resource = bfin_crypto_crc_resources,
1107 .dev = {
1108 .platform_data = (void *)BFIN_CRYPTO_CRC_POLY_DATA,
1109 },
1110 };
1111 #endif
1112
1113 #if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
1114 static const struct ad7877_platform_data bfin_ad7877_ts_info = {
1115 .model = 7877,
1116 .vref_delay_usecs = 50, /* internal, no capacitor */
1117 .x_plate_ohms = 419,
1118 .y_plate_ohms = 486,
1119 .pressure_max = 1000,
1120 .pressure_min = 0,
1121 .stopacq_polarity = 1,
1122 .first_conversion_delay = 3,
1123 .acquisition_time = 1,
1124 .averaging = 1,
1125 .pen_down_acc_interval = 1,
1126 };
1127 #endif
1128
1129 #if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
1130 #include <linux/input.h>
1131 #include <linux/gpio_keys.h>
1132
1133 static struct gpio_keys_button bfin_gpio_keys_table[] = {
1134 {BTN_0, GPIO_PB10, 1, "gpio-keys: BTN0"},
1135 {BTN_1, GPIO_PE1, 1, "gpio-keys: BTN1"},
1136 };
1137
1138 static struct gpio_keys_platform_data bfin_gpio_keys_data = {
1139 .buttons = bfin_gpio_keys_table,
1140 .nbuttons = ARRAY_SIZE(bfin_gpio_keys_table),
1141 };
1142
1143 static struct platform_device bfin_device_gpiokeys = {
1144 .name = "gpio-keys",
1145 .dev = {
1146 .platform_data = &bfin_gpio_keys_data,
1147 },
1148 };
1149 #endif
1150
1151 static struct spi_board_info bfin_spi_board_info[] __initdata = {
1152 #if defined(CONFIG_MTD_M25P80) \
1153 || defined(CONFIG_MTD_M25P80_MODULE)
1154 {
1155 /* the modalias must be the same as spi device driver name */
1156 .modalias = "m25p80", /* Name of spi_driver for this device */
1157 .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
1158 .bus_num = 0, /* Framework bus number */
1159 .chip_select = 1, /* SPI_SSEL1*/
1160 .platform_data = &bfin_spi_flash_data,
1161 .controller_data = &spi_flash_chip_info,
1162 .mode = SPI_MODE_3,
1163 },
1164 #endif
1165 #if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
1166 {
1167 .modalias = "ad7877",
1168 .platform_data = &bfin_ad7877_ts_info,
1169 .irq = IRQ_PD9,
1170 .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */
1171 .bus_num = 0,
1172 .chip_select = 4,
1173 },
1174 #endif
1175 #if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
1176 {
1177 .modalias = "spidev",
1178 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
1179 .bus_num = 0,
1180 .chip_select = 1,
1181 .controller_data = &spidev_chip_info,
1182 },
1183 #endif
1184 #if defined(CONFIG_INPUT_ADXL34X_SPI) || defined(CONFIG_INPUT_ADXL34X_SPI_MODULE)
1185 {
1186 .modalias = "adxl34x",
1187 .platform_data = &adxl34x_info,
1188 .irq = IRQ_PC5,
1189 .max_speed_hz = 5000000, /* max spi clock (SCK) speed in HZ */
1190 .bus_num = 1,
1191 .chip_select = 2,
1192 .mode = SPI_MODE_3,
1193 },
1194 #endif
1195 };
1196 #if defined(CONFIG_SPI_BFIN6XX) || defined(CONFIG_SPI_BFIN6XX_MODULE)
1197 /* SPI (0) */
1198 static struct resource bfin_spi0_resource[] = {
1199 {
1200 .start = SPI0_REGBASE,
1201 .end = SPI0_REGBASE + 0xFF,
1202 .flags = IORESOURCE_MEM,
1203 },
1204 {
1205 .start = CH_SPI0_TX,
1206 .end = CH_SPI0_TX,
1207 .flags = IORESOURCE_DMA,
1208 },
1209 {
1210 .start = CH_SPI0_RX,
1211 .end = CH_SPI0_RX,
1212 .flags = IORESOURCE_DMA,
1213 },
1214 };
1215
1216 /* SPI (1) */
1217 static struct resource bfin_spi1_resource[] = {
1218 {
1219 .start = SPI1_REGBASE,
1220 .end = SPI1_REGBASE + 0xFF,
1221 .flags = IORESOURCE_MEM,
1222 },
1223 {
1224 .start = CH_SPI1_TX,
1225 .end = CH_SPI1_TX,
1226 .flags = IORESOURCE_DMA,
1227 },
1228 {
1229 .start = CH_SPI1_RX,
1230 .end = CH_SPI1_RX,
1231 .flags = IORESOURCE_DMA,
1232 },
1233
1234 };
1235
1236 /* SPI controller data */
1237 static struct bfin6xx_spi_master bf60x_spi_master_info0 = {
1238 .num_chipselect = MAX_CTRL_CS + MAX_BLACKFIN_GPIOS,
1239 .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
1240 };
1241
1242 static struct platform_device bf60x_spi_master0 = {
1243 .name = "bfin-spi",
1244 .id = 0, /* Bus number */
1245 .num_resources = ARRAY_SIZE(bfin_spi0_resource),
1246 .resource = bfin_spi0_resource,
1247 .dev = {
1248 .platform_data = &bf60x_spi_master_info0, /* Passed to driver */
1249 },
1250 };
1251
1252 static struct bfin6xx_spi_master bf60x_spi_master_info1 = {
1253 .num_chipselect = MAX_CTRL_CS + MAX_BLACKFIN_GPIOS,
1254 .pin_req = {P_SPI1_SCK, P_SPI1_MISO, P_SPI1_MOSI, 0},
1255 };
1256
1257 static struct platform_device bf60x_spi_master1 = {
1258 .name = "bfin-spi",
1259 .id = 1, /* Bus number */
1260 .num_resources = ARRAY_SIZE(bfin_spi1_resource),
1261 .resource = bfin_spi1_resource,
1262 .dev = {
1263 .platform_data = &bf60x_spi_master_info1, /* Passed to driver */
1264 },
1265 };
1266 #endif /* spi master and devices */
1267
1268 #if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
1269 static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0};
1270
1271 static struct resource bfin_twi0_resource[] = {
1272 [0] = {
1273 .start = TWI0_CLKDIV,
1274 .end = TWI0_CLKDIV + 0xFF,
1275 .flags = IORESOURCE_MEM,
1276 },
1277 [1] = {
1278 .start = IRQ_TWI0,
1279 .end = IRQ_TWI0,
1280 .flags = IORESOURCE_IRQ,
1281 },
1282 };
1283
1284 static struct platform_device i2c_bfin_twi0_device = {
1285 .name = "i2c-bfin-twi",
1286 .id = 0,
1287 .num_resources = ARRAY_SIZE(bfin_twi0_resource),
1288 .resource = bfin_twi0_resource,
1289 .dev = {
1290 .platform_data = &bfin_twi0_pins,
1291 },
1292 };
1293
1294 static const u16 bfin_twi1_pins[] = {P_TWI1_SCL, P_TWI1_SDA, 0};
1295
1296 static struct resource bfin_twi1_resource[] = {
1297 [0] = {
1298 .start = TWI1_CLKDIV,
1299 .end = TWI1_CLKDIV + 0xFF,
1300 .flags = IORESOURCE_MEM,
1301 },
1302 [1] = {
1303 .start = IRQ_TWI1,
1304 .end = IRQ_TWI1,
1305 .flags = IORESOURCE_IRQ,
1306 },
1307 };
1308
1309 static struct platform_device i2c_bfin_twi1_device = {
1310 .name = "i2c-bfin-twi",
1311 .id = 1,
1312 .num_resources = ARRAY_SIZE(bfin_twi1_resource),
1313 .resource = bfin_twi1_resource,
1314 .dev = {
1315 .platform_data = &bfin_twi1_pins,
1316 },
1317 };
1318 #endif
1319
1320 static struct i2c_board_info __initdata bfin_i2c_board_info0[] = {
1321 #if defined(CONFIG_INPUT_ADXL34X_I2C) || defined(CONFIG_INPUT_ADXL34X_I2C_MODULE)
1322 {
1323 I2C_BOARD_INFO("adxl34x", 0x53),
1324 .irq = IRQ_PC5,
1325 .platform_data = (void *)&adxl34x_info,
1326 },
1327 #endif
1328 #if defined(CONFIG_SND_SOC_ADAU1761) || defined(CONFIG_SND_SOC_ADAU1761_MODULE)
1329 {
1330 I2C_BOARD_INFO("adau1761", 0x38),
1331 .platform_data = (void *)&adau1761_info
1332 },
1333 #endif
1334 #if defined(CONFIG_SND_SOC_SSM2602) || defined(CONFIG_SND_SOC_SSM2602_MODULE)
1335 {
1336 I2C_BOARD_INFO("ssm2602", 0x1b),
1337 },
1338 #endif
1339 };
1340
1341 static struct i2c_board_info __initdata bfin_i2c_board_info1[] = {
1342 };
1343
1344 static const unsigned int cclk_vlev_datasheet[] =
1345 {
1346 /*
1347 * Internal VLEV BF54XSBBC1533
1348 ****temporarily using these values until data sheet is updated
1349 */
1350 VRPAIR(VLEV_085, 150000000),
1351 VRPAIR(VLEV_090, 250000000),
1352 VRPAIR(VLEV_110, 276000000),
1353 VRPAIR(VLEV_115, 301000000),
1354 VRPAIR(VLEV_120, 525000000),
1355 VRPAIR(VLEV_125, 550000000),
1356 VRPAIR(VLEV_130, 600000000),
1357 };
1358
1359 static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
1360 .tuple_tab = cclk_vlev_datasheet,
1361 .tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
1362 .vr_settling_time = 25 /* us */,
1363 };
1364
1365 static struct platform_device bfin_dpmc = {
1366 .name = "bfin dpmc",
1367 .dev = {
1368 .platform_data = &bfin_dmpc_vreg_data,
1369 },
1370 };
1371
1372 static struct platform_device *ezkit_devices[] __initdata = {
1373
1374 &bfin_dpmc,
1375
1376 #if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
1377 &rtc_device,
1378 #endif
1379
1380 #if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
1381 #ifdef CONFIG_SERIAL_BFIN_UART0
1382 &bfin_uart0_device,
1383 #endif
1384 #ifdef CONFIG_SERIAL_BFIN_UART1
1385 &bfin_uart1_device,
1386 #endif
1387 #endif
1388
1389 #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
1390 #ifdef CONFIG_BFIN_SIR0
1391 &bfin_sir0_device,
1392 #endif
1393 #ifdef CONFIG_BFIN_SIR1
1394 &bfin_sir1_device,
1395 #endif
1396 #endif
1397
1398 #if defined(CONFIG_STMMAC_ETH) || defined(CONFIG_STMMAC_ETH_MODULE)
1399 &bfin_eth_device,
1400 #endif
1401
1402 #if defined(CONFIG_USB_MUSB_HDRC) || defined(CONFIG_USB_MUSB_HDRC_MODULE)
1403 &musb_device,
1404 #endif
1405
1406 #if defined(CONFIG_USB_ISP1760_HCD) || defined(CONFIG_USB_ISP1760_HCD_MODULE)
1407 &bfin_isp1760_device,
1408 #endif
1409
1410 #if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
1411 #ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
1412 &bfin_sport0_uart_device,
1413 #endif
1414 #ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
1415 &bfin_sport1_uart_device,
1416 #endif
1417 #ifdef CONFIG_SERIAL_BFIN_SPORT2_UART
1418 &bfin_sport2_uart_device,
1419 #endif
1420 #endif
1421
1422 #if defined(CONFIG_CAN_BFIN) || defined(CONFIG_CAN_BFIN_MODULE)
1423 &bfin_can0_device,
1424 #endif
1425
1426 #if defined(CONFIG_MTD_NAND_BF5XX) || defined(CONFIG_MTD_NAND_BF5XX_MODULE)
1427 &bfin_nand_device,
1428 #endif
1429
1430 #if defined(CONFIG_SDH_BFIN) || defined(CONFIG_SDH_BFIN_MODULE)
1431 &bfin_sdh_device,
1432 #endif
1433
1434 #if defined(CONFIG_SPI_BFIN6XX) || defined(CONFIG_SPI_BFIN6XX_MODULE)
1435 &bf60x_spi_master0,
1436 &bf60x_spi_master1,
1437 #endif
1438
1439 #if defined(CONFIG_INPUT_BFIN_ROTARY) || defined(CONFIG_INPUT_BFIN_ROTARY_MODULE)
1440 &bfin_rotary_device,
1441 #endif
1442
1443 #if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
1444 &i2c_bfin_twi0_device,
1445 #if !defined(CONFIG_BF542)
1446 &i2c_bfin_twi1_device,
1447 #endif
1448 #endif
1449
1450 #if defined(CONFIG_BFIN_CRC)
1451 &bfin_crc0_device,
1452 &bfin_crc1_device,
1453 #endif
1454 #if defined(CONFIG_CRYPTO_DEV_BFIN_CRC)
1455 &bfin_crypto_crc_device,
1456 #endif
1457
1458 #if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
1459 &bfin_device_gpiokeys,
1460 #endif
1461
1462 #if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
1463 &ezkit_flash_device,
1464 #endif
1465 #if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE)
1466 &bfin_i2s_pcm,
1467 #endif
1468 #if defined(CONFIG_SND_BF6XX_SOC_I2S) || \
1469 defined(CONFIG_SND_BF6XX_SOC_I2S_MODULE)
1470 &bfin_i2s,
1471 #endif
1472 #if defined(CONFIG_SND_SOC_BFIN_EVAL_ADAU1X61) || \
1473 defined(CONFIG_SND_SOC_BFIN_EVAL_ADAU1X61_MODULE)
1474 &adau1761_device,
1475 #endif
1476 #if defined(CONFIG_VIDEO_BLACKFIN_CAPTURE) \
1477 || defined(CONFIG_VIDEO_BLACKFIN_CAPTURE_MODULE)
1478 &bfin_capture_device,
1479 #endif
1480 };
1481
1482 static int __init ezkit_init(void)
1483 {
1484 printk(KERN_INFO "%s(): registering device resources\n", __func__);
1485
1486 i2c_register_board_info(0, bfin_i2c_board_info0,
1487 ARRAY_SIZE(bfin_i2c_board_info0));
1488 i2c_register_board_info(1, bfin_i2c_board_info1,
1489 ARRAY_SIZE(bfin_i2c_board_info1));
1490
1491 #if defined(CONFIG_STMMAC_ETH) || defined(CONFIG_STMMAC_ETH_MODULE)
1492 if (!peripheral_request_list(pins, "emac0"))
1493 printk(KERN_ERR "%s(): request emac pins failed\n", __func__);
1494 #endif
1495
1496 platform_add_devices(ezkit_devices, ARRAY_SIZE(ezkit_devices));
1497
1498 spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
1499
1500 return 0;
1501 }
1502
1503 arch_initcall(ezkit_init);
1504
1505 static struct platform_device *ezkit_early_devices[] __initdata = {
1506 #if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
1507 #ifdef CONFIG_SERIAL_BFIN_UART0
1508 &bfin_uart0_device,
1509 #endif
1510 #ifdef CONFIG_SERIAL_BFIN_UART1
1511 &bfin_uart1_device,
1512 #endif
1513 #endif
1514
1515 #if defined(CONFIG_SERIAL_BFIN_SPORT_CONSOLE)
1516 #ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
1517 &bfin_sport0_uart_device,
1518 #endif
1519 #ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
1520 &bfin_sport1_uart_device,
1521 #endif
1522 #ifdef CONFIG_SERIAL_BFIN_SPORT2_UART
1523 &bfin_sport2_uart_device,
1524 #endif
1525 #endif
1526 };
1527
1528 void __init native_machine_early_platform_add_devices(void)
1529 {
1530 printk(KERN_INFO "register early platform devices\n");
1531 early_platform_add_devices(ezkit_early_devices,
1532 ARRAY_SIZE(ezkit_early_devices));
1533 }
Linux kernel - Deliverables
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