arch/blackfin/mach-common/cacheinit.S

   1 /*
   2  * File:         arch/blackfin/mach-common/cacheinit.S
   3  * Based on:
   4  * Author:       LG Soft India
   5  *
   6  * Created:      ?
   7  * Description:  cache initialization
   8  *
   9  * Modified:
  10  *               Copyright 2004-2006 Analog Devices Inc.
  11  *
  12  * Bugs:         Enter bugs at http://blackfin.uclinux.org/
  13  *
  14  * This program is free software; you can redistribute it and/or modify
  15  * it under the terms of the GNU General Public License as published by
  16  * the Free Software Foundation; either version 2 of the License, or
  17  * (at your option) any later version.
  18  *
  19  * This program is distributed in the hope that it will be useful,
  20  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  21  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  22  * GNU General Public License for more details.
  23  *
  24  * You should have received a copy of the GNU General Public License
  25  * along with this program; if not, see the file COPYING, or write
  26  * to the Free Software Foundation, Inc.,
  27  * 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  28  */
  29
  30 /* This function sets up the data and instruction cache. The
  31  * tables like icplb table, dcplb table and Page Descriptor table
  32  * are defined in cplbtab.h. You can configure those tables for
  33  * your suitable requirements
  34  */
  35
  36 #include <linux/linkage.h>
  37 #include <asm/blackfin.h>
  38
  39 .text
  40
  41 #if ANOMALY_05000125
  42 #if defined(CONFIG_BFIN_ICACHE)
  43 ENTRY(_bfin_write_IMEM_CONTROL)
  44
  45         /* Enable Instruction Cache */
  46         P0.l = LO(IMEM_CONTROL);
  47         P0.h = HI(IMEM_CONTROL);
  48
  49         /* Anomaly 05000125 */
  50         CLI R1;
  51         SSYNC;          /* SSYNC required before writing to IMEM_CONTROL. */
  52         .align 8;
  53         [P0] = R0;
  54         SSYNC;
  55         STI R1;
  56         RTS;
  57
  58 ENDPROC(_bfin_write_IMEM_CONTROL)
  59 #endif
  60
  61 #if defined(CONFIG_BFIN_DCACHE)
  62 ENTRY(_bfin_write_DMEM_CONTROL)
  63         P0.l = LO(DMEM_CONTROL);
  64         P0.h = HI(DMEM_CONTROL);
  65
  66         CLI R1;
  67         SSYNC;          /* SSYNC required before writing to DMEM_CONTROL. */
  68         .align 8;
  69         [P0] = R0;
  70         SSYNC;
  71         STI R1;
  72         RTS;
  73
  74 ENDPROC(_bfin_write_DMEM_CONTROL)
  75 #endif
  76
  77 #endif