arch/blackfin/mach-common/cpufreq.c

   1 /*
   2  * Blackfin core clock scaling
   3  *
   4  * Copyright 2008-2011 Analog Devices Inc.
   5  *
   6  * Licensed under the GPL-2 or later.
   7  */
   8
   9 #include <linux/kernel.h>
  10 #include <linux/module.h>
  11 #include <linux/types.h>
  12 #include <linux/init.h>
  13 #include <linux/clk.h>
  14 #include <linux/cpufreq.h>
  15 #include <linux/fs.h>
  16 #include <linux/delay.h>
  17 #include <asm/blackfin.h>
  18 #include <asm/time.h>
  19 #include <asm/dpmc.h>
  20
  21
  22 /* this is the table of CCLK frequencies, in Hz */
  23 /* .index is the entry in the auxiliary dpm_state_table[] */
  24 static struct cpufreq_frequency_table bfin_freq_table[] = {
  25         {
  26                 .frequency = CPUFREQ_TABLE_END,
  27                 .index = 0,
  28         },
  29         {
  30                 .frequency = CPUFREQ_TABLE_END,
  31                 .index = 1,
  32         },
  33         {
  34                 .frequency = CPUFREQ_TABLE_END,
  35                 .index = 2,
  36         },
  37         {
  38                 .frequency = CPUFREQ_TABLE_END,
  39                 .index = 0,
  40         },
  41 };
  42
  43 static struct bfin_dpm_state {
  44         unsigned int csel; /* system clock divider */
  45         unsigned int tscale; /* change the divider on the core timer interrupt */
  46 } dpm_state_table[3];
  47
  48 #if defined(CONFIG_CYCLES_CLOCKSOURCE)
  49 /*
  50  * normalized to maximum frequency offset for CYCLES,
  51  * used in time-ts cycles clock source, but could be used
  52  * somewhere also.
  53  */
  54 unsigned long long __bfin_cycles_off;
  55 unsigned int __bfin_cycles_mod;
  56 #endif
  57
  58 /**************************************************************************/
  59 static void __init bfin_init_tables(unsigned long cclk, unsigned long sclk)
  60 {
  61
  62         unsigned long csel, min_cclk;
  63         int index;
  64
  65         /* Anomaly 273 seems to still exist on non-BF54x w/dcache turned on */
  66 #if ANOMALY_05000273 || ANOMALY_05000274 || \
  67         (!defined(CONFIG_BF54x) && defined(CONFIG_BFIN_EXTMEM_DCACHEABLE))
  68         min_cclk = sclk * 2;
  69 #else
  70         min_cclk = sclk;
  71 #endif
  72
  73 #ifndef CONFIG_BF60x
  74         csel = ((bfin_read_PLL_DIV() & CSEL) >> 4);
  75 #else
  76         csel = bfin_read32(CGU0_DIV) & 0x1F;
  77 #endif
  78
  79         for (index = 0;  (cclk >> index) >= min_cclk && csel <= 3; index++, csel++) {
  80                 bfin_freq_table[index].frequency = cclk >> index;
  81 #ifndef CONFIG_BF60x
  82                 dpm_state_table[index].csel = csel << 4; /* Shift now into PLL_DIV bitpos */
  83                 dpm_state_table[index].tscale =  (TIME_SCALE / (1 << csel)) - 1;
  84 #else
  85                 dpm_state_table[index].csel = csel;
  86                 dpm_state_table[index].tscale =  TIME_SCALE >> index;
  87 #endif
  88
  89                 pr_debug("cpufreq: freq:%d csel:0x%x tscale:%d\n",
  90                                                  bfin_freq_table[index].frequency,
  91                                                  dpm_state_table[index].csel,
  92                                                  dpm_state_table[index].tscale);
  93         }
  94         return;
  95 }
  96
  97 static void bfin_adjust_core_timer(void *info)
  98 {
  99         unsigned int tscale;
 100         unsigned int index = *(unsigned int *)info;
 101
 102         /* we have to adjust the core timer, because it is using cclk */
 103         tscale = dpm_state_table[index].tscale;
 104         bfin_write_TSCALE(tscale);
 105         return;
 106 }
 107
 108 static unsigned int bfin_getfreq_khz(unsigned int cpu)
 109 {
 110         /* Both CoreA/B have the same core clock */
 111         return get_cclk() / 1000;
 112 }
 113
 114 #ifdef CONFIG_BF60x
 115 unsigned long cpu_set_cclk(int cpu, unsigned long new)
 116 {
 117         struct clk *clk;
 118         int ret;
 119
 120         clk = clk_get(NULL, "CCLK");
 121         if (IS_ERR(clk))
 122                 return -ENODEV;
 123
 124         ret = clk_set_rate(clk, new);
 125         clk_put(clk);
 126         return ret;
 127 }
 128 #endif
 129
 130 static int bfin_target(struct cpufreq_policy *poli,
 131                         unsigned int target_freq, unsigned int relation)
 132 {
 133 #ifndef CONFIG_BF60x
 134         unsigned int plldiv;
 135 #endif
 136         unsigned int index, cpu;
 137         unsigned long flags, cclk_hz;
 138         struct cpufreq_freqs freqs;
 139         static unsigned long lpj_ref;
 140         static unsigned int  lpj_ref_freq;
 141         int ret = 0;
 142
 143 #if defined(CONFIG_CYCLES_CLOCKSOURCE)
 144         cycles_t cycles;
 145 #endif
 146
 147         for_each_online_cpu(cpu) {
 148                 struct cpufreq_policy *policy = cpufreq_cpu_get(cpu);
 149
 150                 if (!policy)
 151                         continue;
 152
 153                 if (cpufreq_frequency_table_target(policy, bfin_freq_table,
 154                                  target_freq, relation, &index))
 155                         return -EINVAL;
 156
 157                 cclk_hz = bfin_freq_table[index].frequency;
 158
 159                 freqs.old = bfin_getfreq_khz(0);
 160                 freqs.new = cclk_hz;
 161                 freqs.cpu = cpu;
 162
 163                 pr_debug("cpufreq: changing cclk to %lu; target = %u, oldfreq = %u\n",
 164                          cclk_hz, target_freq, freqs.old);
 165
 166                 cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
 167                 if (cpu == CPUFREQ_CPU) {
 168                         flags = hard_local_irq_save();
 169 #ifndef CONFIG_BF60x
 170                         plldiv = (bfin_read_PLL_DIV() & SSEL) |
 171                                                 dpm_state_table[index].csel;
 172                         bfin_write_PLL_DIV(plldiv);
 173 #else
 174                         ret = cpu_set_cclk(cpu, freqs.new * 1000);
 175                         if (ret != 0) {
 176                                 pr_debug("cpufreq set freq failed %d\n", ret);
 177                                 break;
 178                         }
 179 #endif
 180                         on_each_cpu(bfin_adjust_core_timer, &index, 1);
 181 #if defined(CONFIG_CYCLES_CLOCKSOURCE)
 182                         cycles = get_cycles();
 183                         SSYNC();
 184                         cycles += 10; /* ~10 cycles we lose after get_cycles() */
 185                         __bfin_cycles_off +=
 186                             (cycles << __bfin_cycles_mod) - (cycles << index);
 187                         __bfin_cycles_mod = index;
 188 #endif
 189                         if (!lpj_ref_freq) {
 190                                 lpj_ref = loops_per_jiffy;
 191                                 lpj_ref_freq = freqs.old;
 192                         }
 193                         if (freqs.new != freqs.old) {
 194                                 loops_per_jiffy = cpufreq_scale(lpj_ref,
 195                                                 lpj_ref_freq, freqs.new);
 196                         }
 197                         hard_local_irq_restore(flags);
 198                 }
 199                 /* TODO: just test case for cycles clock source, remove later */
 200                 cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
 201         }
 202
 203         pr_debug("cpufreq: done\n");
 204         return ret;
 205 }
 206
 207 static int bfin_verify_speed(struct cpufreq_policy *policy)
 208 {
 209         return cpufreq_frequency_table_verify(policy, bfin_freq_table);
 210 }
 211
 212 static int __bfin_cpu_init(struct cpufreq_policy *policy)
 213 {
 214
 215         unsigned long cclk, sclk;
 216
 217         cclk = get_cclk() / 1000;
 218         sclk = get_sclk() / 1000;
 219
 220         if (policy->cpu == CPUFREQ_CPU)
 221                 bfin_init_tables(cclk, sclk);
 222
 223         policy->cpuinfo.transition_latency = 50000; /* 50us assumed */
 224
 225         policy->cur = cclk;
 226         cpufreq_frequency_table_get_attr(bfin_freq_table, policy->cpu);
 227         return cpufreq_frequency_table_cpuinfo(policy, bfin_freq_table);
 228 }
 229
 230 static struct freq_attr *bfin_freq_attr[] = {
 231         &cpufreq_freq_attr_scaling_available_freqs,
 232         NULL,
 233 };
 234
 235 static struct cpufreq_driver bfin_driver = {
 236         .verify = bfin_verify_speed,
 237         .target = bfin_target,
 238         .get = bfin_getfreq_khz,
 239         .init = __bfin_cpu_init,
 240         .name = "bfin cpufreq",
 241         .owner = THIS_MODULE,
 242         .attr = bfin_freq_attr,
 243 };
 244
 245 static int __init bfin_cpu_init(void)
 246 {
 247         return cpufreq_register_driver(&bfin_driver);
 248 }
 249
 250 static void __exit bfin_cpu_exit(void)
 251 {
 252         cpufreq_unregister_driver(&bfin_driver);
 253 }
 254
 255 MODULE_AUTHOR("Michael Hennerich <hennerich@blackfin.uclinux.org>");
 256 MODULE_DESCRIPTION("cpufreq driver for Blackfin");
 257 MODULE_LICENSE("GPL");
 258
 259 module_init(bfin_cpu_init);
 260 module_exit(bfin_cpu_exit);