arch/blackfin/mach-common/dpmc_modes.S

   1 /*
   2  * Copyright 2004-2008 Analog Devices Inc.
   3  *
   4  * Licensed under the GPL-2 or later.
   5  */
   6
   7 #include <linux/linkage.h>
   8 #include <asm/blackfin.h>
   9 #include <mach/irq.h>
  10 #include <asm/dpmc.h>
  11
  12 .section .l1.text
  13
  14 ENTRY(_sleep_mode)
  15         [--SP] = ( R7:0, P5:0 );
  16         [--SP] =  RETS;
  17
  18         call _set_sic_iwr;
  19
  20         P0.H = hi(PLL_CTL);
  21         P0.L = lo(PLL_CTL);
  22         R1 = W[P0](z);
  23         BITSET (R1, 3);
  24         W[P0] = R1.L;
  25
  26         CLI R2;
  27         SSYNC;
  28         IDLE;
  29         STI R2;
  30
  31         call _test_pll_locked;
  32
  33         R0 = IWR_ENABLE(0);
  34         R1 = IWR_DISABLE_ALL;
  35         R2 = IWR_DISABLE_ALL;
  36
  37         call _set_sic_iwr;
  38
  39         P0.H = hi(PLL_CTL);
  40         P0.L = lo(PLL_CTL);
  41         R7 = w[p0](z);
  42         BITCLR (R7, 3);
  43         BITCLR (R7, 5);
  44         w[p0] = R7.L;
  45         IDLE;
  46         call _test_pll_locked;
  47
  48         RETS = [SP++];
  49         ( R7:0, P5:0 ) = [SP++];
  50         RTS;
  51 ENDPROC(_sleep_mode)
  52
  53 ENTRY(_hibernate_mode)
  54         [--SP] = ( R7:0, P5:0 );
  55         [--SP] =  RETS;
  56
  57         R3 = R0;
  58         R0 = IWR_DISABLE_ALL;
  59         R1 = IWR_DISABLE_ALL;
  60         R2 = IWR_DISABLE_ALL;
  61         call _set_sic_iwr;
  62         call _set_dram_srfs;
  63         SSYNC;
  64
  65         P0.H = hi(VR_CTL);
  66         P0.L = lo(VR_CTL);
  67
  68         W[P0] = R3.L;
  69         CLI R2;
  70         IDLE;
  71 .Lforever:
  72         jump .Lforever;
  73 ENDPROC(_hibernate_mode)
  74
  75 ENTRY(_sleep_deeper)
  76         [--SP] = ( R7:0, P5:0 );
  77         [--SP] =  RETS;
  78
  79         CLI R4;
  80
  81         P3 = R0;
  82         P4 = R1;
  83         P5 = R2;
  84
  85         R0 = IWR_ENABLE(0);
  86         R1 = IWR_DISABLE_ALL;
  87         R2 = IWR_DISABLE_ALL;
  88
  89         call _set_sic_iwr;
  90         call _set_dram_srfs;    /* Set SDRAM Self Refresh */
  91
  92         P0.H = hi(PLL_DIV);
  93         P0.L = lo(PLL_DIV);
  94         R6 = W[P0](z);
  95         R0.L = 0xF;
  96         W[P0] = R0.l;           /* Set Max VCO to SCLK divider */
  97
  98         P0.H = hi(PLL_CTL);
  99         P0.L = lo(PLL_CTL);
 100         R5 = W[P0](z);
 101         R0.L = (CONFIG_MIN_VCO_HZ/CONFIG_CLKIN_HZ) << 9;
 102         W[P0] = R0.l;           /* Set Min CLKIN to VCO multiplier */
 103
 104         SSYNC;
 105         IDLE;
 106
 107         call _test_pll_locked;
 108
 109         P0.H = hi(VR_CTL);
 110         P0.L = lo(VR_CTL);
 111         R7 = W[P0](z);
 112         R1 = 0x6;
 113         R1 <<= 16;
 114         R2 = 0x0404(Z);
 115         R1 = R1|R2;
 116
 117         R2 = DEPOSIT(R7, R1);
 118         W[P0] = R2;             /* Set Min Core Voltage */
 119
 120         SSYNC;
 121         IDLE;
 122
 123         call _test_pll_locked;
 124
 125         R0 = P3;
 126         R1 = P4;
 127         R3 = P5;
 128         call _set_sic_iwr;      /* Set Awake from IDLE */
 129
 130         P0.H = hi(PLL_CTL);
 131         P0.L = lo(PLL_CTL);
 132         R0 = W[P0](z);
 133         BITSET (R0, 3);
 134         W[P0] = R0.L;           /* Turn CCLK OFF */
 135         SSYNC;
 136         IDLE;
 137
 138         call _test_pll_locked;
 139
 140         R0 = IWR_ENABLE(0);
 141         R1 = IWR_DISABLE_ALL;
 142         R2 = IWR_DISABLE_ALL;
 143
 144         call _set_sic_iwr;      /* Set Awake from IDLE PLL */
 145
 146         P0.H = hi(VR_CTL);
 147         P0.L = lo(VR_CTL);
 148         W[P0]= R7;
 149
 150         SSYNC;
 151         IDLE;
 152
 153         call _test_pll_locked;
 154
 155         P0.H = hi(PLL_DIV);
 156         P0.L = lo(PLL_DIV);
 157         W[P0]= R6;              /* Restore CCLK and SCLK divider */
 158
 159         P0.H = hi(PLL_CTL);
 160         P0.L = lo(PLL_CTL);
 161         w[p0] = R5;             /* Restore VCO multiplier */
 162         IDLE;
 163         call _test_pll_locked;
 164
 165         call _unset_dram_srfs;  /* SDRAM Self Refresh Off */
 166
 167         STI R4;
 168
 169         RETS = [SP++];
 170         ( R7:0, P5:0 ) = [SP++];
 171         RTS;
 172 ENDPROC(_sleep_deeper)
 173
 174 ENTRY(_set_dram_srfs)
 175         /*  set the dram to self refresh mode */
 176         SSYNC;
 177 #if defined(EBIU_RSTCTL)        /* DDR */
 178         P0.H = hi(EBIU_RSTCTL);
 179         P0.L = lo(EBIU_RSTCTL);
 180         R2 = [P0];
 181         BITSET(R2, 3); /* SRREQ enter self-refresh mode */
 182         [P0] = R2;
 183         SSYNC;
 184 1:
 185         R2 = [P0];
 186         CC = BITTST(R2, 4);
 187         if !CC JUMP 1b;
 188 #else                           /* SDRAM */
 189         P0.L = lo(EBIU_SDGCTL);
 190         P0.H = hi(EBIU_SDGCTL);
 191         R2 = [P0];
 192         BITSET(R2, 24); /* SRFS enter self-refresh mode */
 193         [P0] = R2;
 194         SSYNC;
 195
 196         P0.L = lo(EBIU_SDSTAT);
 197         P0.H = hi(EBIU_SDSTAT);
 198 1:
 199         R2 = w[P0];
 200         SSYNC;
 201         cc = BITTST(R2, 1); /* SDSRA poll self-refresh status */
 202         if !cc jump 1b;
 203
 204         P0.L = lo(EBIU_SDGCTL);
 205         P0.H = hi(EBIU_SDGCTL);
 206         R2 = [P0];
 207         BITCLR(R2, 0); /* SCTLE disable CLKOUT */
 208         [P0] = R2;
 209 #endif
 210         RTS;
 211 ENDPROC(_set_dram_srfs)
 212
 213 ENTRY(_unset_dram_srfs)
 214         /*  set the dram out of self refresh mode */
 215 #if defined(EBIU_RSTCTL)        /* DDR */
 216         P0.H = hi(EBIU_RSTCTL);
 217         P0.L = lo(EBIU_RSTCTL);
 218         R2 = [P0];
 219         BITCLR(R2, 3); /* clear SRREQ bit */
 220         [P0] = R2;
 221 #elif defined(EBIU_SDGCTL)      /* SDRAM */
 222
 223         P0.L = lo(EBIU_SDGCTL); /* release CLKOUT from self-refresh */
 224         P0.H = hi(EBIU_SDGCTL);
 225         R2 = [P0];
 226         BITSET(R2, 0); /* SCTLE enable CLKOUT */
 227         [P0] = R2
 228         SSYNC;
 229
 230         P0.L = lo(EBIU_SDGCTL); /* release SDRAM from self-refresh */
 231         P0.H = hi(EBIU_SDGCTL);
 232         R2 = [P0];
 233         BITCLR(R2, 24); /* clear SRFS bit */
 234         [P0] = R2
 235 #endif
 236         SSYNC;
 237         RTS;
 238 ENDPROC(_unset_dram_srfs)
 239
 240 ENTRY(_set_sic_iwr)
 241 #if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561) || \
 242         defined(CONFIG_BF538) || defined(CONFIG_BF539) || defined(CONFIG_BF51x)
 243         P0.H = hi(SIC_IWR0);
 244         P0.L = lo(SIC_IWR0);
 245         P1.H = hi(SIC_IWR1);
 246         P1.L = lo(SIC_IWR1);
 247         [P1] = R1;
 248 #if defined(CONFIG_BF54x)
 249         P1.H = hi(SIC_IWR2);
 250         P1.L = lo(SIC_IWR2);
 251         [P1] = R2;
 252 #endif
 253 #else
 254         P0.H = hi(SIC_IWR);
 255         P0.L = lo(SIC_IWR);
 256 #endif
 257         [P0] = R0;
 258
 259         SSYNC;
 260         RTS;
 261 ENDPROC(_set_sic_iwr)
 262
 263 ENTRY(_test_pll_locked)
 264         P0.H = hi(PLL_STAT);
 265         P0.L = lo(PLL_STAT);
 266 1:
 267         R0 = W[P0] (Z);
 268         CC = BITTST(R0,5);
 269         IF !CC JUMP 1b;
 270         RTS;
 271 ENDPROC(_test_pll_locked)
 272
 273 .section .text
 274
 275 ENTRY(_do_hibernate)
 276         [--SP] = ( R7:0, P5:0 );
 277         [--SP] =  RETS;
 278         /* Save System MMRs */
 279         R2 = R0;
 280         P0.H = hi(PLL_CTL);
 281         P0.L = lo(PLL_CTL);
 282
 283 #ifdef SIC_IMASK0
 284         PM_SYS_PUSH(SIC_IMASK0)
 285 #endif
 286 #ifdef SIC_IMASK1
 287         PM_SYS_PUSH(SIC_IMASK1)
 288 #endif
 289 #ifdef SIC_IMASK2
 290         PM_SYS_PUSH(SIC_IMASK2)
 291 #endif
 292 #ifdef SIC_IMASK
 293         PM_SYS_PUSH(SIC_IMASK)
 294 #endif
 295 #ifdef SIC_IAR0
 296         PM_SYS_PUSH(SIC_IAR0)
 297         PM_SYS_PUSH(SIC_IAR1)
 298         PM_SYS_PUSH(SIC_IAR2)
 299 #endif
 300 #ifdef SIC_IAR3
 301         PM_SYS_PUSH(SIC_IAR3)
 302 #endif
 303 #ifdef SIC_IAR4
 304         PM_SYS_PUSH(SIC_IAR4)
 305         PM_SYS_PUSH(SIC_IAR5)
 306         PM_SYS_PUSH(SIC_IAR6)
 307 #endif
 308 #ifdef SIC_IAR7
 309         PM_SYS_PUSH(SIC_IAR7)
 310 #endif
 311 #ifdef SIC_IAR8
 312         PM_SYS_PUSH(SIC_IAR8)
 313         PM_SYS_PUSH(SIC_IAR9)
 314         PM_SYS_PUSH(SIC_IAR10)
 315         PM_SYS_PUSH(SIC_IAR11)
 316 #endif
 317
 318 #ifdef SIC_IWR
 319         PM_SYS_PUSH(SIC_IWR)
 320 #endif
 321 #ifdef SIC_IWR0
 322         PM_SYS_PUSH(SIC_IWR0)
 323 #endif
 324 #ifdef SIC_IWR1
 325         PM_SYS_PUSH(SIC_IWR1)
 326 #endif
 327 #ifdef SIC_IWR2
 328         PM_SYS_PUSH(SIC_IWR2)
 329 #endif
 330
 331 #ifdef PINT0_ASSIGN
 332         PM_SYS_PUSH(PINT0_MASK_SET)
 333         PM_SYS_PUSH(PINT1_MASK_SET)
 334         PM_SYS_PUSH(PINT2_MASK_SET)
 335         PM_SYS_PUSH(PINT3_MASK_SET)
 336         PM_SYS_PUSH(PINT0_ASSIGN)
 337         PM_SYS_PUSH(PINT1_ASSIGN)
 338         PM_SYS_PUSH(PINT2_ASSIGN)
 339         PM_SYS_PUSH(PINT3_ASSIGN)
 340         PM_SYS_PUSH(PINT0_INVERT_SET)
 341         PM_SYS_PUSH(PINT1_INVERT_SET)
 342         PM_SYS_PUSH(PINT2_INVERT_SET)
 343         PM_SYS_PUSH(PINT3_INVERT_SET)
 344         PM_SYS_PUSH(PINT0_EDGE_SET)
 345         PM_SYS_PUSH(PINT1_EDGE_SET)
 346         PM_SYS_PUSH(PINT2_EDGE_SET)
 347         PM_SYS_PUSH(PINT3_EDGE_SET)
 348 #endif
 349
 350         PM_SYS_PUSH(EBIU_AMBCTL0)
 351         PM_SYS_PUSH(EBIU_AMBCTL1)
 352         PM_SYS_PUSH16(EBIU_AMGCTL)
 353
 354 #ifdef EBIU_FCTL
 355         PM_SYS_PUSH(EBIU_MBSCTL)
 356         PM_SYS_PUSH(EBIU_MODE)
 357         PM_SYS_PUSH(EBIU_FCTL)
 358 #endif
 359
 360 #ifdef PORTCIO_FER
 361         PM_SYS_PUSH16(PORTCIO_DIR)
 362         PM_SYS_PUSH16(PORTCIO_INEN)
 363         PM_SYS_PUSH16(PORTCIO)
 364         PM_SYS_PUSH16(PORTCIO_FER)
 365         PM_SYS_PUSH16(PORTDIO_DIR)
 366         PM_SYS_PUSH16(PORTDIO_INEN)
 367         PM_SYS_PUSH16(PORTDIO)
 368         PM_SYS_PUSH16(PORTDIO_FER)
 369         PM_SYS_PUSH16(PORTEIO_DIR)
 370         PM_SYS_PUSH16(PORTEIO_INEN)
 371         PM_SYS_PUSH16(PORTEIO)
 372         PM_SYS_PUSH16(PORTEIO_FER)
 373 #endif
 374
 375         PM_SYS_PUSH16(SYSCR)
 376
 377         /* Save Core MMRs */
 378         P0.H = hi(SRAM_BASE_ADDRESS);
 379         P0.L = lo(SRAM_BASE_ADDRESS);
 380
 381         PM_PUSH(DMEM_CONTROL)
 382         PM_PUSH(DCPLB_ADDR0)
 383         PM_PUSH(DCPLB_ADDR1)
 384         PM_PUSH(DCPLB_ADDR2)
 385         PM_PUSH(DCPLB_ADDR3)
 386         PM_PUSH(DCPLB_ADDR4)
 387         PM_PUSH(DCPLB_ADDR5)
 388         PM_PUSH(DCPLB_ADDR6)
 389         PM_PUSH(DCPLB_ADDR7)
 390         PM_PUSH(DCPLB_ADDR8)
 391         PM_PUSH(DCPLB_ADDR9)
 392         PM_PUSH(DCPLB_ADDR10)
 393         PM_PUSH(DCPLB_ADDR11)
 394         PM_PUSH(DCPLB_ADDR12)
 395         PM_PUSH(DCPLB_ADDR13)
 396         PM_PUSH(DCPLB_ADDR14)
 397         PM_PUSH(DCPLB_ADDR15)
 398         PM_PUSH(DCPLB_DATA0)
 399         PM_PUSH(DCPLB_DATA1)
 400         PM_PUSH(DCPLB_DATA2)
 401         PM_PUSH(DCPLB_DATA3)
 402         PM_PUSH(DCPLB_DATA4)
 403         PM_PUSH(DCPLB_DATA5)
 404         PM_PUSH(DCPLB_DATA6)
 405         PM_PUSH(DCPLB_DATA7)
 406         PM_PUSH(DCPLB_DATA8)
 407         PM_PUSH(DCPLB_DATA9)
 408         PM_PUSH(DCPLB_DATA10)
 409         PM_PUSH(DCPLB_DATA11)
 410         PM_PUSH(DCPLB_DATA12)
 411         PM_PUSH(DCPLB_DATA13)
 412         PM_PUSH(DCPLB_DATA14)
 413         PM_PUSH(DCPLB_DATA15)
 414         PM_PUSH(IMEM_CONTROL)
 415         PM_PUSH(ICPLB_ADDR0)
 416         PM_PUSH(ICPLB_ADDR1)
 417         PM_PUSH(ICPLB_ADDR2)
 418         PM_PUSH(ICPLB_ADDR3)
 419         PM_PUSH(ICPLB_ADDR4)
 420         PM_PUSH(ICPLB_ADDR5)
 421         PM_PUSH(ICPLB_ADDR6)
 422         PM_PUSH(ICPLB_ADDR7)
 423         PM_PUSH(ICPLB_ADDR8)
 424         PM_PUSH(ICPLB_ADDR9)
 425         PM_PUSH(ICPLB_ADDR10)
 426         PM_PUSH(ICPLB_ADDR11)
 427         PM_PUSH(ICPLB_ADDR12)
 428         PM_PUSH(ICPLB_ADDR13)
 429         PM_PUSH(ICPLB_ADDR14)
 430         PM_PUSH(ICPLB_ADDR15)
 431         PM_PUSH(ICPLB_DATA0)
 432         PM_PUSH(ICPLB_DATA1)
 433         PM_PUSH(ICPLB_DATA2)
 434         PM_PUSH(ICPLB_DATA3)
 435         PM_PUSH(ICPLB_DATA4)
 436         PM_PUSH(ICPLB_DATA5)
 437         PM_PUSH(ICPLB_DATA6)
 438         PM_PUSH(ICPLB_DATA7)
 439         PM_PUSH(ICPLB_DATA8)
 440         PM_PUSH(ICPLB_DATA9)
 441         PM_PUSH(ICPLB_DATA10)
 442         PM_PUSH(ICPLB_DATA11)
 443         PM_PUSH(ICPLB_DATA12)
 444         PM_PUSH(ICPLB_DATA13)
 445         PM_PUSH(ICPLB_DATA14)
 446         PM_PUSH(ICPLB_DATA15)
 447         PM_PUSH(EVT0)
 448         PM_PUSH(EVT1)
 449         PM_PUSH(EVT2)
 450         PM_PUSH(EVT3)
 451         PM_PUSH(EVT4)
 452         PM_PUSH(EVT5)
 453         PM_PUSH(EVT6)
 454         PM_PUSH(EVT7)
 455         PM_PUSH(EVT8)
 456         PM_PUSH(EVT9)
 457         PM_PUSH(EVT10)
 458         PM_PUSH(EVT11)
 459         PM_PUSH(EVT12)
 460         PM_PUSH(EVT13)
 461         PM_PUSH(EVT14)
 462         PM_PUSH(EVT15)
 463         PM_PUSH(IMASK)
 464         PM_PUSH(ILAT)
 465         PM_PUSH(IPRIO)
 466         PM_PUSH(TCNTL)
 467         PM_PUSH(TPERIOD)
 468         PM_PUSH(TSCALE)
 469         PM_PUSH(TCOUNT)
 470         PM_PUSH(TBUFCTL)
 471
 472         /* Save Core Registers */
 473         [--sp] = SYSCFG;
 474         [--sp] = ( R7:0, P5:0 );
 475         [--sp] = fp;
 476         [--sp] = usp;
 477
 478         [--sp] = i0;
 479         [--sp] = i1;
 480         [--sp] = i2;
 481         [--sp] = i3;
 482
 483         [--sp] = m0;
 484         [--sp] = m1;
 485         [--sp] = m2;
 486         [--sp] = m3;
 487
 488         [--sp] = l0;
 489         [--sp] = l1;
 490         [--sp] = l2;
 491         [--sp] = l3;
 492
 493         [--sp] = b0;
 494         [--sp] = b1;
 495         [--sp] = b2;
 496         [--sp] = b3;
 497         [--sp] = a0.x;
 498         [--sp] = a0.w;
 499         [--sp] = a1.x;
 500         [--sp] = a1.w;
 501
 502         [--sp] = LC0;
 503         [--sp] = LC1;
 504         [--sp] = LT0;
 505         [--sp] = LT1;
 506         [--sp] = LB0;
 507         [--sp] = LB1;
 508
 509         [--sp] = ASTAT;
 510         [--sp] = CYCLES;
 511         [--sp] = CYCLES2;
 512
 513         [--sp] = RETS;
 514         r0 = RETI;
 515         [--sp] = r0;
 516         [--sp] = RETX;
 517         [--sp] = RETN;
 518         [--sp] = RETE;
 519         [--sp] = SEQSTAT;
 520
 521         /* Save Magic, return address and Stack Pointer */
 522         P0.H = 0;
 523         P0.L = 0;
 524         R0.H = 0xDEAD;  /* Hibernate Magic */
 525         R0.L = 0xBEEF;
 526         [P0++] = R0;    /* Store Hibernate Magic */
 527         R0.H = .Lpm_resume_here;
 528         R0.L = .Lpm_resume_here;
 529         [P0++] = R0;    /* Save Return Address */
 530         [P0++] = SP;    /* Save Stack Pointer */
 531         P0.H = _hibernate_mode;
 532         P0.L = _hibernate_mode;
 533         R0 = R2;
 534         call (P0); /* Goodbye */
 535
 536 .Lpm_resume_here:
 537
 538         /* Restore Core Registers */
 539         SEQSTAT = [sp++];
 540         RETE = [sp++];
 541         RETN = [sp++];
 542         RETX = [sp++];
 543         r0 = [sp++];
 544         RETI = r0;
 545         RETS = [sp++];
 546
 547         CYCLES2 = [sp++];
 548         CYCLES = [sp++];
 549         ASTAT = [sp++];
 550
 551         LB1 = [sp++];
 552         LB0 = [sp++];
 553         LT1 = [sp++];
 554         LT0 = [sp++];
 555         LC1 = [sp++];
 556         LC0 = [sp++];
 557
 558         a1.w = [sp++];
 559         a1.x = [sp++];
 560         a0.w = [sp++];
 561         a0.x = [sp++];
 562         b3 = [sp++];
 563         b2 = [sp++];
 564         b1 = [sp++];
 565         b0 = [sp++];
 566
 567         l3 = [sp++];
 568         l2 = [sp++];
 569         l1 = [sp++];
 570         l0 = [sp++];
 571
 572         m3 = [sp++];
 573         m2 = [sp++];
 574         m1 = [sp++];
 575         m0 = [sp++];
 576
 577         i3 = [sp++];
 578         i2 = [sp++];
 579         i1 = [sp++];
 580         i0 = [sp++];
 581
 582         usp = [sp++];
 583         fp = [sp++];
 584
 585         ( R7 : 0, P5 : 0) = [ SP ++ ];
 586         SYSCFG = [sp++];
 587
 588         /* Restore Core MMRs */
 589
 590         PM_POP(TBUFCTL)
 591         PM_POP(TCOUNT)
 592         PM_POP(TSCALE)
 593         PM_POP(TPERIOD)
 594         PM_POP(TCNTL)
 595         PM_POP(IPRIO)
 596         PM_POP(ILAT)
 597         PM_POP(IMASK)
 598         PM_POP(EVT15)
 599         PM_POP(EVT14)
 600         PM_POP(EVT13)
 601         PM_POP(EVT12)
 602         PM_POP(EVT11)
 603         PM_POP(EVT10)
 604         PM_POP(EVT9)
 605         PM_POP(EVT8)
 606         PM_POP(EVT7)
 607         PM_POP(EVT6)
 608         PM_POP(EVT5)
 609         PM_POP(EVT4)
 610         PM_POP(EVT3)
 611         PM_POP(EVT2)
 612         PM_POP(EVT1)
 613         PM_POP(EVT0)
 614         PM_POP(ICPLB_DATA15)
 615         PM_POP(ICPLB_DATA14)
 616         PM_POP(ICPLB_DATA13)
 617         PM_POP(ICPLB_DATA12)
 618         PM_POP(ICPLB_DATA11)
 619         PM_POP(ICPLB_DATA10)
 620         PM_POP(ICPLB_DATA9)
 621         PM_POP(ICPLB_DATA8)
 622         PM_POP(ICPLB_DATA7)
 623         PM_POP(ICPLB_DATA6)
 624         PM_POP(ICPLB_DATA5)
 625         PM_POP(ICPLB_DATA4)
 626         PM_POP(ICPLB_DATA3)
 627         PM_POP(ICPLB_DATA2)
 628         PM_POP(ICPLB_DATA1)
 629         PM_POP(ICPLB_DATA0)
 630         PM_POP(ICPLB_ADDR15)
 631         PM_POP(ICPLB_ADDR14)
 632         PM_POP(ICPLB_ADDR13)
 633         PM_POP(ICPLB_ADDR12)
 634         PM_POP(ICPLB_ADDR11)
 635         PM_POP(ICPLB_ADDR10)
 636         PM_POP(ICPLB_ADDR9)
 637         PM_POP(ICPLB_ADDR8)
 638         PM_POP(ICPLB_ADDR7)
 639         PM_POP(ICPLB_ADDR6)
 640         PM_POP(ICPLB_ADDR5)
 641         PM_POP(ICPLB_ADDR4)
 642         PM_POP(ICPLB_ADDR3)
 643         PM_POP(ICPLB_ADDR2)
 644         PM_POP(ICPLB_ADDR1)
 645         PM_POP(ICPLB_ADDR0)
 646         PM_POP(IMEM_CONTROL)
 647         PM_POP(DCPLB_DATA15)
 648         PM_POP(DCPLB_DATA14)
 649         PM_POP(DCPLB_DATA13)
 650         PM_POP(DCPLB_DATA12)
 651         PM_POP(DCPLB_DATA11)
 652         PM_POP(DCPLB_DATA10)
 653         PM_POP(DCPLB_DATA9)
 654         PM_POP(DCPLB_DATA8)
 655         PM_POP(DCPLB_DATA7)
 656         PM_POP(DCPLB_DATA6)
 657         PM_POP(DCPLB_DATA5)
 658         PM_POP(DCPLB_DATA4)
 659         PM_POP(DCPLB_DATA3)
 660         PM_POP(DCPLB_DATA2)
 661         PM_POP(DCPLB_DATA1)
 662         PM_POP(DCPLB_DATA0)
 663         PM_POP(DCPLB_ADDR15)
 664         PM_POP(DCPLB_ADDR14)
 665         PM_POP(DCPLB_ADDR13)
 666         PM_POP(DCPLB_ADDR12)
 667         PM_POP(DCPLB_ADDR11)
 668         PM_POP(DCPLB_ADDR10)
 669         PM_POP(DCPLB_ADDR9)
 670         PM_POP(DCPLB_ADDR8)
 671         PM_POP(DCPLB_ADDR7)
 672         PM_POP(DCPLB_ADDR6)
 673         PM_POP(DCPLB_ADDR5)
 674         PM_POP(DCPLB_ADDR4)
 675         PM_POP(DCPLB_ADDR3)
 676         PM_POP(DCPLB_ADDR2)
 677         PM_POP(DCPLB_ADDR1)
 678         PM_POP(DCPLB_ADDR0)
 679         PM_POP(DMEM_CONTROL)
 680
 681         /* Restore System MMRs */
 682
 683         P0.H = hi(PLL_CTL);
 684         P0.L = lo(PLL_CTL);
 685         PM_SYS_POP16(SYSCR)
 686
 687 #ifdef PORTCIO_FER
 688         PM_SYS_POP16(PORTEIO_FER)
 689         PM_SYS_POP16(PORTEIO)
 690         PM_SYS_POP16(PORTEIO_INEN)
 691         PM_SYS_POP16(PORTEIO_DIR)
 692         PM_SYS_POP16(PORTDIO_FER)
 693         PM_SYS_POP16(PORTDIO)
 694         PM_SYS_POP16(PORTDIO_INEN)
 695         PM_SYS_POP16(PORTDIO_DIR)
 696         PM_SYS_POP16(PORTCIO_FER)
 697         PM_SYS_POP16(PORTCIO)
 698         PM_SYS_POP16(PORTCIO_INEN)
 699         PM_SYS_POP16(PORTCIO_DIR)
 700 #endif
 701
 702 #ifdef EBIU_FCTL
 703         PM_SYS_POP(EBIU_FCTL)
 704         PM_SYS_POP(EBIU_MODE)
 705         PM_SYS_POP(EBIU_MBSCTL)
 706 #endif
 707         PM_SYS_POP16(EBIU_AMGCTL)
 708         PM_SYS_POP(EBIU_AMBCTL1)
 709         PM_SYS_POP(EBIU_AMBCTL0)
 710
 711 #ifdef PINT0_ASSIGN
 712         PM_SYS_POP(PINT3_EDGE_SET)
 713         PM_SYS_POP(PINT2_EDGE_SET)
 714         PM_SYS_POP(PINT1_EDGE_SET)
 715         PM_SYS_POP(PINT0_EDGE_SET)
 716         PM_SYS_POP(PINT3_INVERT_SET)
 717         PM_SYS_POP(PINT2_INVERT_SET)
 718         PM_SYS_POP(PINT1_INVERT_SET)
 719         PM_SYS_POP(PINT0_INVERT_SET)
 720         PM_SYS_POP(PINT3_ASSIGN)
 721         PM_SYS_POP(PINT2_ASSIGN)
 722         PM_SYS_POP(PINT1_ASSIGN)
 723         PM_SYS_POP(PINT0_ASSIGN)
 724         PM_SYS_POP(PINT3_MASK_SET)
 725         PM_SYS_POP(PINT2_MASK_SET)
 726         PM_SYS_POP(PINT1_MASK_SET)
 727         PM_SYS_POP(PINT0_MASK_SET)
 728 #endif
 729
 730 #ifdef SIC_IWR2
 731         PM_SYS_POP(SIC_IWR2)
 732 #endif
 733 #ifdef SIC_IWR1
 734         PM_SYS_POP(SIC_IWR1)
 735 #endif
 736 #ifdef SIC_IWR0
 737         PM_SYS_POP(SIC_IWR0)
 738 #endif
 739 #ifdef SIC_IWR
 740         PM_SYS_POP(SIC_IWR)
 741 #endif
 742
 743 #ifdef SIC_IAR8
 744         PM_SYS_POP(SIC_IAR11)
 745         PM_SYS_POP(SIC_IAR10)
 746         PM_SYS_POP(SIC_IAR9)
 747         PM_SYS_POP(SIC_IAR8)
 748 #endif
 749 #ifdef SIC_IAR7
 750         PM_SYS_POP(SIC_IAR7)
 751 #endif
 752 #ifdef SIC_IAR6
 753         PM_SYS_POP(SIC_IAR6)
 754         PM_SYS_POP(SIC_IAR5)
 755         PM_SYS_POP(SIC_IAR4)
 756 #endif
 757 #ifdef SIC_IAR3
 758         PM_SYS_POP(SIC_IAR3)
 759 #endif
 760 #ifdef SIC_IAR0
 761         PM_SYS_POP(SIC_IAR2)
 762         PM_SYS_POP(SIC_IAR1)
 763         PM_SYS_POP(SIC_IAR0)
 764 #endif
 765 #ifdef SIC_IMASK
 766         PM_SYS_POP(SIC_IMASK)
 767 #endif
 768 #ifdef SIC_IMASK2
 769         PM_SYS_POP(SIC_IMASK2)
 770 #endif
 771 #ifdef SIC_IMASK1
 772         PM_SYS_POP(SIC_IMASK1)
 773 #endif
 774 #ifdef SIC_IMASK0
 775         PM_SYS_POP(SIC_IMASK0)
 776 #endif
 777
 778         [--sp] = RETI;  /* Clear Global Interrupt Disable */
 779         SP += 4;
 780
 781         RETS = [SP++];
 782         ( R7:0, P5:0 ) = [SP++];
 783         RTS;
 784 ENDPROC(_do_hibernate)