2 * Copyright 2004-2008 Analog Devices Inc.
4 * Licensed under the GPL-2 or later.
7 #include <linux/linkage.h>
8 #include <asm/blackfin.h>
15 [--SP] = ( R7:0, P5:0 );
31 call _test_pll_locked;
46 call _test_pll_locked;
49 ( R7:0, P5:0 ) = [SP++];
53 ENTRY(_hibernate_mode)
54 [--SP] = ( R7:0, P5:0 );
73 ENDPROC(_hibernate_mode)
76 [--SP] = ( R7:0, P5:0 );
90 call _set_dram_srfs; /* Set SDRAM Self Refresh */
96 W[P0] = R0.l; /* Set Max VCO to SCLK divider */
101 R0.L = (CONFIG_MIN_VCO_HZ/CONFIG_CLKIN_HZ) << 9;
102 W[P0] = R0.l; /* Set Min CLKIN to VCO multiplier */
107 call _test_pll_locked;
117 R2 = DEPOSIT(R7, R1);
118 W[P0] = R2; /* Set Min Core Voltage */
123 call _test_pll_locked;
128 call _set_sic_iwr; /* Set Awake from IDLE */
134 W[P0] = R0.L; /* Turn CCLK OFF */
138 call _test_pll_locked;
141 R1 = IWR_DISABLE_ALL;
142 R2 = IWR_DISABLE_ALL;
144 call _set_sic_iwr; /* Set Awake from IDLE PLL */
153 call _test_pll_locked;
157 W[P0]= R6; /* Restore CCLK and SCLK divider */
161 w[p0] = R5; /* Restore VCO multiplier */
163 call _test_pll_locked;
165 call _unset_dram_srfs; /* SDRAM Self Refresh Off */
170 ( R7:0, P5:0 ) = [SP++];
172 ENDPROC(_sleep_deeper)
174 ENTRY(_set_dram_srfs)
175 /* set the dram to self refresh mode */
177 #if defined(EBIU_RSTCTL) /* DDR */
178 P0.H = hi(EBIU_RSTCTL);
179 P0.L = lo(EBIU_RSTCTL);
181 BITSET(R2, 3); /* SRREQ enter self-refresh mode */
189 P0.L = lo(EBIU_SDGCTL);
190 P0.H = hi(EBIU_SDGCTL);
192 BITSET(R2, 24); /* SRFS enter self-refresh mode */
196 P0.L = lo(EBIU_SDSTAT);
197 P0.H = hi(EBIU_SDSTAT);
201 cc = BITTST(R2, 1); /* SDSRA poll self-refresh status */
204 P0.L = lo(EBIU_SDGCTL);
205 P0.H = hi(EBIU_SDGCTL);
207 BITCLR(R2, 0); /* SCTLE disable CLKOUT */
211 ENDPROC(_set_dram_srfs)
213 ENTRY(_unset_dram_srfs)
214 /* set the dram out of self refresh mode */
215 #if defined(EBIU_RSTCTL) /* DDR */
216 P0.H = hi(EBIU_RSTCTL);
217 P0.L = lo(EBIU_RSTCTL);
219 BITCLR(R2, 3); /* clear SRREQ bit */
221 #elif defined(EBIU_SDGCTL) /* SDRAM */
223 P0.L = lo(EBIU_SDGCTL); /* release CLKOUT from self-refresh */
224 P0.H = hi(EBIU_SDGCTL);
226 BITSET(R2, 0); /* SCTLE enable CLKOUT */
230 P0.L = lo(EBIU_SDGCTL); /* release SDRAM from self-refresh */
231 P0.H = hi(EBIU_SDGCTL);
233 BITCLR(R2, 24); /* clear SRFS bit */
238 ENDPROC(_unset_dram_srfs)
242 P0.H = hi(SYSMMR_BASE);
243 P0.L = lo(SYSMMR_BASE);
244 [P0 + (SIC_IWR0 - SYSMMR_BASE)] = R0;
245 [P0 + (SIC_IWR1 - SYSMMR_BASE)] = R1;
247 [P0 + (SIC_IWR2 - SYSMMR_BASE)] = R2;
257 ENDPROC(_set_sic_iwr)
259 ENTRY(_test_pll_locked)
267 ENDPROC(_test_pll_locked)
272 R0 = [P0 + (x - SRAM_BASE_ADDRESS)];\
277 [P0 + (x - SRAM_BASE_ADDRESS)] = R0;\
279 #define PM_SYS_PUSH(x) \
280 R0 = [P0 + (x - PLL_CTL)];\
283 #define PM_SYS_POP(x) \
285 [P0 + (x - PLL_CTL)] = R0;\
287 #define PM_SYS_PUSH16(x) \
288 R0 = w[P0 + (x - PLL_CTL)];\
291 #define PM_SYS_POP16(x) \
293 w[P0 + (x - PLL_CTL)] = R0;\
296 [--SP] = ( R7:0, P5:0 );
298 /* Save System MMRs */
304 PM_SYS_PUSH(SIC_IMASK0)
307 PM_SYS_PUSH(SIC_IMASK1)
310 PM_SYS_PUSH(SIC_IMASK2)
313 PM_SYS_PUSH(SIC_IMASK)
316 PM_SYS_PUSH(SIC_IAR0)
317 PM_SYS_PUSH(SIC_IAR1)
318 PM_SYS_PUSH(SIC_IAR2)
321 PM_SYS_PUSH(SIC_IAR3)
324 PM_SYS_PUSH(SIC_IAR4)
325 PM_SYS_PUSH(SIC_IAR5)
326 PM_SYS_PUSH(SIC_IAR6)
329 PM_SYS_PUSH(SIC_IAR7)
332 PM_SYS_PUSH(SIC_IAR8)
333 PM_SYS_PUSH(SIC_IAR9)
334 PM_SYS_PUSH(SIC_IAR10)
335 PM_SYS_PUSH(SIC_IAR11)
342 PM_SYS_PUSH(SIC_IWR0)
345 PM_SYS_PUSH(SIC_IWR1)
348 PM_SYS_PUSH(SIC_IWR2)
352 PM_SYS_PUSH(PINT0_MASK_SET)
353 PM_SYS_PUSH(PINT1_MASK_SET)
354 PM_SYS_PUSH(PINT2_MASK_SET)
355 PM_SYS_PUSH(PINT3_MASK_SET)
356 PM_SYS_PUSH(PINT0_ASSIGN)
357 PM_SYS_PUSH(PINT1_ASSIGN)
358 PM_SYS_PUSH(PINT2_ASSIGN)
359 PM_SYS_PUSH(PINT3_ASSIGN)
360 PM_SYS_PUSH(PINT0_INVERT_SET)
361 PM_SYS_PUSH(PINT1_INVERT_SET)
362 PM_SYS_PUSH(PINT2_INVERT_SET)
363 PM_SYS_PUSH(PINT3_INVERT_SET)
364 PM_SYS_PUSH(PINT0_EDGE_SET)
365 PM_SYS_PUSH(PINT1_EDGE_SET)
366 PM_SYS_PUSH(PINT2_EDGE_SET)
367 PM_SYS_PUSH(PINT3_EDGE_SET)
370 PM_SYS_PUSH(EBIU_AMBCTL0)
371 PM_SYS_PUSH(EBIU_AMBCTL1)
372 PM_SYS_PUSH16(EBIU_AMGCTL)
375 PM_SYS_PUSH(EBIU_MBSCTL)
376 PM_SYS_PUSH(EBIU_MODE)
377 PM_SYS_PUSH(EBIU_FCTL)
381 PM_SYS_PUSH16(PORTCIO_DIR)
382 PM_SYS_PUSH16(PORTCIO_INEN)
383 PM_SYS_PUSH16(PORTCIO)
384 PM_SYS_PUSH16(PORTCIO_FER)
385 PM_SYS_PUSH16(PORTDIO_DIR)
386 PM_SYS_PUSH16(PORTDIO_INEN)
387 PM_SYS_PUSH16(PORTDIO)
388 PM_SYS_PUSH16(PORTDIO_FER)
389 PM_SYS_PUSH16(PORTEIO_DIR)
390 PM_SYS_PUSH16(PORTEIO_INEN)
391 PM_SYS_PUSH16(PORTEIO)
392 PM_SYS_PUSH16(PORTEIO_FER)
398 P0.H = hi(SRAM_BASE_ADDRESS);
399 P0.L = lo(SRAM_BASE_ADDRESS);
401 PM_PUSH(DMEM_CONTROL)
412 PM_PUSH(DCPLB_ADDR10)
413 PM_PUSH(DCPLB_ADDR11)
414 PM_PUSH(DCPLB_ADDR12)
415 PM_PUSH(DCPLB_ADDR13)
416 PM_PUSH(DCPLB_ADDR14)
417 PM_PUSH(DCPLB_ADDR15)
428 PM_PUSH(DCPLB_DATA10)
429 PM_PUSH(DCPLB_DATA11)
430 PM_PUSH(DCPLB_DATA12)
431 PM_PUSH(DCPLB_DATA13)
432 PM_PUSH(DCPLB_DATA14)
433 PM_PUSH(DCPLB_DATA15)
434 PM_PUSH(IMEM_CONTROL)
445 PM_PUSH(ICPLB_ADDR10)
446 PM_PUSH(ICPLB_ADDR11)
447 PM_PUSH(ICPLB_ADDR12)
448 PM_PUSH(ICPLB_ADDR13)
449 PM_PUSH(ICPLB_ADDR14)
450 PM_PUSH(ICPLB_ADDR15)
461 PM_PUSH(ICPLB_DATA10)
462 PM_PUSH(ICPLB_DATA11)
463 PM_PUSH(ICPLB_DATA12)
464 PM_PUSH(ICPLB_DATA13)
465 PM_PUSH(ICPLB_DATA14)
466 PM_PUSH(ICPLB_DATA15)
492 /* Save Core Registers */
494 [--sp] = ( R7:0, P5:0 );
539 /* Save Magic, return address and Stack Pointer */
542 R0.H = 0xDEAD; /* Hibernate Magic */
544 [P0++] = R0; /* Store Hibernate Magic */
545 R0.H = .Lpm_resume_here;
546 R0.L = .Lpm_resume_here;
547 [P0++] = R0; /* Save Return Address */
548 [P0++] = SP; /* Save Stack Pointer */
549 P0.H = _hibernate_mode;
550 P0.L = _hibernate_mode;
552 call (P0); /* Goodbye */
556 /* Restore Core Registers */
601 ( R7 : 0, P5 : 0) = [ SP ++ ];
604 /* Restore Core MMRs */
697 /* Restore System MMRs */
704 PM_SYS_POP16(PORTEIO_FER)
705 PM_SYS_POP16(PORTEIO)
706 PM_SYS_POP16(PORTEIO_INEN)
707 PM_SYS_POP16(PORTEIO_DIR)
708 PM_SYS_POP16(PORTDIO_FER)
709 PM_SYS_POP16(PORTDIO)
710 PM_SYS_POP16(PORTDIO_INEN)
711 PM_SYS_POP16(PORTDIO_DIR)
712 PM_SYS_POP16(PORTCIO_FER)
713 PM_SYS_POP16(PORTCIO)
714 PM_SYS_POP16(PORTCIO_INEN)
715 PM_SYS_POP16(PORTCIO_DIR)
719 PM_SYS_POP(EBIU_FCTL)
720 PM_SYS_POP(EBIU_MODE)
721 PM_SYS_POP(EBIU_MBSCTL)
723 PM_SYS_POP16(EBIU_AMGCTL)
724 PM_SYS_POP(EBIU_AMBCTL1)
725 PM_SYS_POP(EBIU_AMBCTL0)
728 PM_SYS_POP(PINT3_EDGE_SET)
729 PM_SYS_POP(PINT2_EDGE_SET)
730 PM_SYS_POP(PINT1_EDGE_SET)
731 PM_SYS_POP(PINT0_EDGE_SET)
732 PM_SYS_POP(PINT3_INVERT_SET)
733 PM_SYS_POP(PINT2_INVERT_SET)
734 PM_SYS_POP(PINT1_INVERT_SET)
735 PM_SYS_POP(PINT0_INVERT_SET)
736 PM_SYS_POP(PINT3_ASSIGN)
737 PM_SYS_POP(PINT2_ASSIGN)
738 PM_SYS_POP(PINT1_ASSIGN)
739 PM_SYS_POP(PINT0_ASSIGN)
740 PM_SYS_POP(PINT3_MASK_SET)
741 PM_SYS_POP(PINT2_MASK_SET)
742 PM_SYS_POP(PINT1_MASK_SET)
743 PM_SYS_POP(PINT0_MASK_SET)
760 PM_SYS_POP(SIC_IAR11)
761 PM_SYS_POP(SIC_IAR10)
782 PM_SYS_POP(SIC_IMASK)
785 PM_SYS_POP(SIC_IMASK2)
788 PM_SYS_POP(SIC_IMASK1)
791 PM_SYS_POP(SIC_IMASK0)
794 [--sp] = RETI; /* Clear Global Interrupt Disable */
798 ( R7:0, P5:0 ) = [SP++];
800 ENDPROC(_do_hibernate)