2 * Copyright 2004-2008 Analog Devices Inc.
4 * Licensed under the GPL-2 or later.
7 #include <linux/linkage.h>
8 #include <asm/blackfin.h>
15 [--SP] = ( R7:0, P5:0 );
31 call _test_pll_locked;
46 call _test_pll_locked;
49 ( R7:0, P5:0 ) = [SP++];
54 * This func never returns as it puts the part into hibernate, and
55 * is only called from do_hibernate, so we don't bother saving or
56 * restoring any of the normal C runtime state. When we wake up,
57 * the entry point will be in do_hibernate and not here.
59 * We accept just one argument -- the value to write to VR_CTL.
61 ENTRY(_hibernate_mode)
62 /* Save/setup the regs we need early for minor pipeline optimization */
67 /* Disable all wakeup sources */
75 /* Finally, we climb into our cave to hibernate */
81 ENDPROC(_hibernate_mode)
84 [--SP] = ( R7:0, P5:0 );
98 call _set_dram_srfs; /* Set SDRAM Self Refresh */
104 W[P0] = R0.l; /* Set Max VCO to SCLK divider */
109 R0.L = (CONFIG_MIN_VCO_HZ/CONFIG_CLKIN_HZ) << 9;
110 W[P0] = R0.l; /* Set Min CLKIN to VCO multiplier */
115 call _test_pll_locked;
125 R2 = DEPOSIT(R7, R1);
126 W[P0] = R2; /* Set Min Core Voltage */
131 call _test_pll_locked;
136 call _set_sic_iwr; /* Set Awake from IDLE */
142 W[P0] = R0.L; /* Turn CCLK OFF */
146 call _test_pll_locked;
149 R1 = IWR_DISABLE_ALL;
150 R2 = IWR_DISABLE_ALL;
152 call _set_sic_iwr; /* Set Awake from IDLE PLL */
161 call _test_pll_locked;
165 W[P0]= R6; /* Restore CCLK and SCLK divider */
169 w[p0] = R5; /* Restore VCO multiplier */
171 call _test_pll_locked;
173 call _unset_dram_srfs; /* SDRAM Self Refresh Off */
178 ( R7:0, P5:0 ) = [SP++];
180 ENDPROC(_sleep_deeper)
182 ENTRY(_set_dram_srfs)
183 /* set the dram to self refresh mode */
185 #if defined(EBIU_RSTCTL) /* DDR */
186 P0.H = hi(EBIU_RSTCTL);
187 P0.L = lo(EBIU_RSTCTL);
189 BITSET(R2, 3); /* SRREQ enter self-refresh mode */
197 P0.L = lo(EBIU_SDGCTL);
198 P0.H = hi(EBIU_SDGCTL);
200 BITSET(R2, 24); /* SRFS enter self-refresh mode */
204 P0.L = lo(EBIU_SDSTAT);
205 P0.H = hi(EBIU_SDSTAT);
209 cc = BITTST(R2, 1); /* SDSRA poll self-refresh status */
212 P0.L = lo(EBIU_SDGCTL);
213 P0.H = hi(EBIU_SDGCTL);
215 BITCLR(R2, 0); /* SCTLE disable CLKOUT */
219 ENDPROC(_set_dram_srfs)
221 ENTRY(_unset_dram_srfs)
222 /* set the dram out of self refresh mode */
223 #if defined(EBIU_RSTCTL) /* DDR */
224 P0.H = hi(EBIU_RSTCTL);
225 P0.L = lo(EBIU_RSTCTL);
227 BITCLR(R2, 3); /* clear SRREQ bit */
229 #elif defined(EBIU_SDGCTL) /* SDRAM */
231 P0.L = lo(EBIU_SDGCTL); /* release CLKOUT from self-refresh */
232 P0.H = hi(EBIU_SDGCTL);
234 BITSET(R2, 0); /* SCTLE enable CLKOUT */
238 P0.L = lo(EBIU_SDGCTL); /* release SDRAM from self-refresh */
239 P0.H = hi(EBIU_SDGCTL);
241 BITCLR(R2, 24); /* clear SRFS bit */
246 ENDPROC(_unset_dram_srfs)
250 P0.H = hi(SYSMMR_BASE);
251 P0.L = lo(SYSMMR_BASE);
252 [P0 + (SIC_IWR0 - SYSMMR_BASE)] = R0;
253 [P0 + (SIC_IWR1 - SYSMMR_BASE)] = R1;
255 [P0 + (SIC_IWR2 - SYSMMR_BASE)] = R2;
265 ENDPROC(_set_sic_iwr)
267 ENTRY(_test_pll_locked)
275 ENDPROC(_test_pll_locked)
294 #define PM_REGSET0 R7:7
295 #define PM_REGSET1 R7:6
296 #define PM_REGSET2 R7:5
297 #define PM_REGSET3 R7:4
298 #define PM_REGSET4 R7:3
299 #define PM_REGSET5 R7:2
300 #define PM_REGSET6 R7:1
301 #define PM_REGSET7 R7:0
302 #define PM_REGSET8 R7:0, P5:5
303 #define PM_REGSET9 R7:0, P5:4
304 #define PM_REGSET10 R7:0, P5:3
305 #define PM_REGSET11 R7:0, P5:2
306 #define PM_REGSET12 R7:0, P5:1
307 #define PM_REGSET13 R7:0, P5:0
309 #define _PM_PUSH(n, x, w, base) PM_REG##n = w[FP + ((x) - (base))];
310 #define _PM_POP(n, x, w, base) w[FP + ((x) - (base))] = PM_REG##n;
311 #define PM_PUSH_SYNC(n) [--sp] = (PM_REGSET##n);
312 #define PM_POP_SYNC(n) (PM_REGSET##n) = [sp++];
313 #define PM_PUSH(n, x) PM_REG##n = [FP++];
314 #define PM_POP(n, x) [FP--] = PM_REG##n;
315 #define PM_CORE_PUSH(n, x) _PM_PUSH(n, x, , COREMMR_BASE)
316 #define PM_CORE_POP(n, x) _PM_POP(n, x, , COREMMR_BASE)
317 #define PM_SYS_PUSH(n, x) _PM_PUSH(n, x, , SYSMMR_BASE)
318 #define PM_SYS_POP(n, x) _PM_POP(n, x, , SYSMMR_BASE)
319 #define PM_SYS_PUSH16(n, x) _PM_PUSH(n, x, w, SYSMMR_BASE)
320 #define PM_SYS_POP16(n, x) _PM_POP(n, x, w, SYSMMR_BASE)
324 * Save the core regs early so we can blow them away when
325 * saving/restoring MMR states
327 [--sp] = (R7:0, P5:0);
362 /* We can't push RETI directly as that'll change IPEND[4] */
373 /* Save first func arg in M3 */
376 /* Save system MMRs */
377 FP.H = hi(SYSMMR_BASE);
378 FP.L = lo(SYSMMR_BASE);
381 PM_SYS_PUSH(0, SIC_IMASK0)
382 PM_SYS_PUSH(1, SIC_IMASK1)
384 PM_SYS_PUSH(2, SIC_IMASK2)
387 PM_SYS_PUSH(0, SIC_IMASK)
390 PM_SYS_PUSH(3, SIC_IAR0)
391 PM_SYS_PUSH(4, SIC_IAR1)
392 PM_SYS_PUSH(5, SIC_IAR2)
395 PM_SYS_PUSH(6, SIC_IAR3)
398 PM_SYS_PUSH(7, SIC_IAR4)
399 PM_SYS_PUSH(8, SIC_IAR5)
400 PM_SYS_PUSH(9, SIC_IAR6)
403 PM_SYS_PUSH(10, SIC_IAR7)
406 PM_SYS_PUSH(11, SIC_IAR8)
407 PM_SYS_PUSH(12, SIC_IAR9)
408 PM_SYS_PUSH(13, SIC_IAR10)
412 PM_SYS_PUSH(0, SIC_IAR11)
416 PM_SYS_PUSH(1, SIC_IWR)
419 PM_SYS_PUSH(1, SIC_IWR0)
422 PM_SYS_PUSH(2, SIC_IWR1)
425 PM_SYS_PUSH(3, SIC_IWR2)
429 PM_SYS_PUSH(4, PINT0_MASK_SET)
430 PM_SYS_PUSH(5, PINT1_MASK_SET)
431 PM_SYS_PUSH(6, PINT2_MASK_SET)
432 PM_SYS_PUSH(7, PINT3_MASK_SET)
433 PM_SYS_PUSH(8, PINT0_ASSIGN)
434 PM_SYS_PUSH(9, PINT1_ASSIGN)
435 PM_SYS_PUSH(10, PINT2_ASSIGN)
436 PM_SYS_PUSH(11, PINT3_ASSIGN)
437 PM_SYS_PUSH(12, PINT0_INVERT_SET)
438 PM_SYS_PUSH(13, PINT1_INVERT_SET)
440 PM_SYS_PUSH(0, PINT2_INVERT_SET)
441 PM_SYS_PUSH(1, PINT3_INVERT_SET)
442 PM_SYS_PUSH(2, PINT0_EDGE_SET)
443 PM_SYS_PUSH(3, PINT1_EDGE_SET)
444 PM_SYS_PUSH(4, PINT2_EDGE_SET)
445 PM_SYS_PUSH(5, PINT3_EDGE_SET)
448 PM_SYS_PUSH16(6, SYSCR)
450 PM_SYS_PUSH16(7, EBIU_AMGCTL)
451 PM_SYS_PUSH(8, EBIU_AMBCTL0)
452 PM_SYS_PUSH(9, EBIU_AMBCTL1)
454 PM_SYS_PUSH(10, EBIU_MBSCTL)
455 PM_SYS_PUSH(11, EBIU_MODE)
456 PM_SYS_PUSH(12, EBIU_FCTL)
463 I0.H = hi(COREMMR_BASE);
464 I0.L = lo(COREMMR_BASE);
472 I1.L = lo(DCPLB_ADDR0);
473 I2.L = lo(DCPLB_DATA0);
474 I3.L = lo(ICPLB_ADDR0);
475 B0.L = lo(ICPLB_DATA0);
482 PM_PUSH(0, DCPLB_ADDR0)
483 PM_PUSH(1, DCPLB_ADDR1)
484 PM_PUSH(2, DCPLB_ADDR2)
485 PM_PUSH(3, DCPLB_ADDR3)
486 PM_PUSH(4, DCPLB_ADDR4)
487 PM_PUSH(5, DCPLB_ADDR5)
488 PM_PUSH(6, DCPLB_ADDR6)
489 PM_PUSH(7, DCPLB_ADDR7)
490 PM_PUSH(8, DCPLB_ADDR8)
491 PM_PUSH(9, DCPLB_ADDR9)
492 PM_PUSH(10, DCPLB_ADDR10)
493 PM_PUSH(11, DCPLB_ADDR11)
494 PM_PUSH(12, DCPLB_ADDR12)
495 PM_PUSH(13, DCPLB_ADDR13)
497 PM_PUSH(0, DCPLB_ADDR14)
498 PM_PUSH(1, DCPLB_ADDR15)
502 PM_PUSH(2, DCPLB_DATA0)
503 PM_PUSH(3, DCPLB_DATA1)
504 PM_PUSH(4, DCPLB_DATA2)
505 PM_PUSH(5, DCPLB_DATA3)
506 PM_PUSH(6, DCPLB_DATA4)
507 PM_PUSH(7, DCPLB_DATA5)
508 PM_PUSH(8, DCPLB_DATA6)
509 PM_PUSH(9, DCPLB_DATA7)
510 PM_PUSH(10, DCPLB_DATA8)
511 PM_PUSH(11, DCPLB_DATA9)
512 PM_PUSH(12, DCPLB_DATA10)
513 PM_PUSH(13, DCPLB_DATA11)
515 PM_PUSH(0, DCPLB_DATA12)
516 PM_PUSH(1, DCPLB_DATA13)
517 PM_PUSH(2, DCPLB_DATA14)
518 PM_PUSH(3, DCPLB_DATA15)
522 PM_PUSH(4, ICPLB_ADDR0)
523 PM_PUSH(5, ICPLB_ADDR1)
524 PM_PUSH(6, ICPLB_ADDR2)
525 PM_PUSH(7, ICPLB_ADDR3)
526 PM_PUSH(8, ICPLB_ADDR4)
527 PM_PUSH(9, ICPLB_ADDR5)
528 PM_PUSH(10, ICPLB_ADDR6)
529 PM_PUSH(11, ICPLB_ADDR7)
530 PM_PUSH(12, ICPLB_ADDR8)
531 PM_PUSH(13, ICPLB_ADDR9)
533 PM_PUSH(0, ICPLB_ADDR10)
534 PM_PUSH(1, ICPLB_ADDR11)
535 PM_PUSH(2, ICPLB_ADDR12)
536 PM_PUSH(3, ICPLB_ADDR13)
537 PM_PUSH(4, ICPLB_ADDR14)
538 PM_PUSH(5, ICPLB_ADDR15)
542 PM_PUSH(6, ICPLB_DATA0)
543 PM_PUSH(7, ICPLB_DATA1)
544 PM_PUSH(8, ICPLB_DATA2)
545 PM_PUSH(9, ICPLB_DATA3)
546 PM_PUSH(10, ICPLB_DATA4)
547 PM_PUSH(11, ICPLB_DATA5)
548 PM_PUSH(12, ICPLB_DATA6)
549 PM_PUSH(13, ICPLB_DATA7)
551 PM_PUSH(0, ICPLB_DATA8)
552 PM_PUSH(1, ICPLB_DATA9)
553 PM_PUSH(2, ICPLB_DATA10)
554 PM_PUSH(3, ICPLB_DATA11)
555 PM_PUSH(4, ICPLB_DATA12)
556 PM_PUSH(5, ICPLB_DATA13)
557 PM_PUSH(6, ICPLB_DATA14)
558 PM_PUSH(7, ICPLB_DATA15)
593 /* Misc non-contiguous registers */
595 PM_CORE_PUSH(0, DMEM_CONTROL);
596 PM_CORE_PUSH(1, IMEM_CONTROL);
597 PM_CORE_PUSH(2, TBUFCTL);
600 /* Setup args to hibernate mode early for pipeline optimization */
602 P1.H = _hibernate_mode;
603 P1.L = _hibernate_mode;
605 /* Save Magic, return address and Stack Pointer */
607 R1.H = 0xDEAD; /* Hibernate Magic */
609 R2.H = .Lpm_resume_here;
610 R2.L = .Lpm_resume_here;
611 [P0++] = R1; /* Store Hibernate Magic */
612 [P0++] = R2; /* Save Return Address */
613 [P0++] = SP; /* Save Stack Pointer */
615 /* Must use an indirect call as we need to jump to L1 */
616 call (P1); /* Goodbye */
620 /* Restore Core MMRs */
621 I0.H = hi(COREMMR_BASE);
622 I0.L = lo(COREMMR_BASE);
630 I1.L = lo(DCPLB_ADDR15);
631 I2.L = lo(DCPLB_DATA15);
632 I3.L = lo(ICPLB_ADDR15);
633 B0.L = lo(ICPLB_DATA15);
638 /* Misc non-contiguous registers */
641 PM_CORE_POP(2, TBUFCTL)
642 PM_CORE_POP(1, IMEM_CONTROL)
643 PM_CORE_POP(0, DMEM_CONTROL)
657 FP += -4; /* IPEND */
680 PM_POP(7, ICPLB_DATA15)
681 PM_POP(6, ICPLB_DATA14)
682 PM_POP(5, ICPLB_DATA13)
683 PM_POP(4, ICPLB_DATA12)
684 PM_POP(3, ICPLB_DATA11)
685 PM_POP(2, ICPLB_DATA10)
686 PM_POP(1, ICPLB_DATA9)
687 PM_POP(0, ICPLB_DATA8)
689 PM_POP(13, ICPLB_DATA7)
690 PM_POP(12, ICPLB_DATA6)
691 PM_POP(11, ICPLB_DATA5)
692 PM_POP(10, ICPLB_DATA4)
693 PM_POP(9, ICPLB_DATA3)
694 PM_POP(8, ICPLB_DATA2)
695 PM_POP(7, ICPLB_DATA1)
696 PM_POP(6, ICPLB_DATA0)
700 PM_POP(5, ICPLB_ADDR15)
701 PM_POP(4, ICPLB_ADDR14)
702 PM_POP(3, ICPLB_ADDR13)
703 PM_POP(2, ICPLB_ADDR12)
704 PM_POP(1, ICPLB_ADDR11)
705 PM_POP(0, ICPLB_ADDR10)
707 PM_POP(13, ICPLB_ADDR9)
708 PM_POP(12, ICPLB_ADDR8)
709 PM_POP(11, ICPLB_ADDR7)
710 PM_POP(10, ICPLB_ADDR6)
711 PM_POP(9, ICPLB_ADDR5)
712 PM_POP(8, ICPLB_ADDR4)
713 PM_POP(7, ICPLB_ADDR3)
714 PM_POP(6, ICPLB_ADDR2)
715 PM_POP(5, ICPLB_ADDR1)
716 PM_POP(4, ICPLB_ADDR0)
720 PM_POP(3, DCPLB_DATA15)
721 PM_POP(2, DCPLB_DATA14)
722 PM_POP(1, DCPLB_DATA13)
723 PM_POP(0, DCPLB_DATA12)
725 PM_POP(13, DCPLB_DATA11)
726 PM_POP(12, DCPLB_DATA10)
727 PM_POP(11, DCPLB_DATA9)
728 PM_POP(10, DCPLB_DATA8)
729 PM_POP(9, DCPLB_DATA7)
730 PM_POP(8, DCPLB_DATA6)
731 PM_POP(7, DCPLB_DATA5)
732 PM_POP(6, DCPLB_DATA4)
733 PM_POP(5, DCPLB_DATA3)
734 PM_POP(4, DCPLB_DATA2)
735 PM_POP(3, DCPLB_DATA1)
736 PM_POP(2, DCPLB_DATA0)
740 PM_POP(1, DCPLB_ADDR15)
741 PM_POP(0, DCPLB_ADDR14)
743 PM_POP(13, DCPLB_ADDR13)
744 PM_POP(12, DCPLB_ADDR12)
745 PM_POP(11, DCPLB_ADDR11)
746 PM_POP(10, DCPLB_ADDR10)
747 PM_POP(9, DCPLB_ADDR9)
748 PM_POP(8, DCPLB_ADDR8)
749 PM_POP(7, DCPLB_ADDR7)
750 PM_POP(6, DCPLB_ADDR6)
751 PM_POP(5, DCPLB_ADDR5)
752 PM_POP(4, DCPLB_ADDR4)
753 PM_POP(3, DCPLB_ADDR3)
754 PM_POP(2, DCPLB_ADDR2)
755 PM_POP(1, DCPLB_ADDR1)
756 PM_POP(0, DCPLB_ADDR0)
758 /* Restore System MMRs */
759 FP.H = hi(SYSMMR_BASE);
760 FP.L = lo(SYSMMR_BASE);
764 PM_SYS_POP(12, EBIU_FCTL)
765 PM_SYS_POP(11, EBIU_MODE)
766 PM_SYS_POP(10, EBIU_MBSCTL)
770 PM_SYS_POP(9, EBIU_AMBCTL1)
771 PM_SYS_POP(8, EBIU_AMBCTL0)
772 PM_SYS_POP16(7, EBIU_AMGCTL)
774 PM_SYS_POP16(6, SYSCR)
777 PM_SYS_POP(5, PINT3_EDGE_SET)
778 PM_SYS_POP(4, PINT2_EDGE_SET)
779 PM_SYS_POP(3, PINT1_EDGE_SET)
780 PM_SYS_POP(2, PINT0_EDGE_SET)
781 PM_SYS_POP(1, PINT3_INVERT_SET)
782 PM_SYS_POP(0, PINT2_INVERT_SET)
784 PM_SYS_POP(13, PINT1_INVERT_SET)
785 PM_SYS_POP(12, PINT0_INVERT_SET)
786 PM_SYS_POP(11, PINT3_ASSIGN)
787 PM_SYS_POP(10, PINT2_ASSIGN)
788 PM_SYS_POP(9, PINT1_ASSIGN)
789 PM_SYS_POP(8, PINT0_ASSIGN)
790 PM_SYS_POP(7, PINT3_MASK_SET)
791 PM_SYS_POP(6, PINT2_MASK_SET)
792 PM_SYS_POP(5, PINT1_MASK_SET)
793 PM_SYS_POP(4, PINT0_MASK_SET)
797 PM_SYS_POP(3, SIC_IWR2)
800 PM_SYS_POP(2, SIC_IWR1)
803 PM_SYS_POP(1, SIC_IWR0)
806 PM_SYS_POP(1, SIC_IWR)
810 PM_SYS_POP(0, SIC_IAR11)
814 PM_SYS_POP(13, SIC_IAR10)
815 PM_SYS_POP(12, SIC_IAR9)
816 PM_SYS_POP(11, SIC_IAR8)
819 PM_SYS_POP(10, SIC_IAR7)
822 PM_SYS_POP(9, SIC_IAR6)
823 PM_SYS_POP(8, SIC_IAR5)
824 PM_SYS_POP(7, SIC_IAR4)
827 PM_SYS_POP(6, SIC_IAR3)
830 PM_SYS_POP(5, SIC_IAR2)
831 PM_SYS_POP(4, SIC_IAR1)
832 PM_SYS_POP(3, SIC_IAR0)
836 PM_SYS_POP(2, SIC_IMASK2)
838 PM_SYS_POP(1, SIC_IMASK1)
839 PM_SYS_POP(0, SIC_IMASK0)
841 PM_SYS_POP(0, SIC_IMASK)
844 /* Restore Core Registers */
887 (R7:0, P5:0) = [sp++];
889 [--sp] = RETI; /* Clear Global Interrupt Disable */
893 ENDPROC(_do_hibernate)