arch/cris/arch-v10/kernel/time.c

   1 /*
   2  *  linux/arch/cris/arch-v10/kernel/time.c
   3  *
   4  *  Copyright (C) 1991, 1992, 1995  Linus Torvalds
   5  *  Copyright (C) 1999-2002 Axis Communications AB
   6  *
   7  */
   8
   9 #include <linux/timex.h>
  10 #include <linux/time.h>
  11 #include <linux/jiffies.h>
  12 #include <linux/interrupt.h>
  13 #include <linux/swap.h>
  14 #include <linux/sched.h>
  15 #include <linux/init.h>
  16 #include <linux/mm.h>
  17 #include <arch/svinto.h>
  18 #include <asm/types.h>
  19 #include <asm/signal.h>
  20 #include <asm/io.h>
  21 #include <asm/delay.h>
  22 #include <asm/rtc.h>
  23 #include <asm/irq_regs.h>
  24
  25 /* define this if you need to use print_timestamp */
  26 /* it will make jiffies at 96 hz instead of 100 hz though */
  27 #undef USE_CASCADE_TIMERS
  28
  29 extern int set_rtc_mmss(unsigned long nowtime);
  30 extern int have_rtc;
  31
  32 unsigned long get_ns_in_jiffie(void)
  33 {
  34         unsigned char timer_count, t1;
  35         unsigned short presc_count;
  36         unsigned long ns;
  37         unsigned long flags;
  38
  39         local_irq_save(flags);
  40         timer_count = *R_TIMER0_DATA;
  41         presc_count = *R_TIM_PRESC_STATUS;
  42         /* presc_count might be wrapped */
  43         t1 = *R_TIMER0_DATA;
  44
  45         if (timer_count != t1){
  46                 /* it wrapped, read prescaler again...  */
  47                 presc_count = *R_TIM_PRESC_STATUS;
  48                 timer_count = t1;
  49         }
  50         local_irq_restore(flags);
  51         if (presc_count >= PRESCALE_VALUE/2 ){
  52                 presc_count =  PRESCALE_VALUE - presc_count + PRESCALE_VALUE/2;
  53         } else {
  54                 presc_count =  PRESCALE_VALUE - presc_count - PRESCALE_VALUE/2;
  55         }
  56
  57         ns = ( (TIMER0_DIV - timer_count) * ((1000000000/HZ)/TIMER0_DIV )) +
  58              ( (presc_count) * (1000000000/PRESCALE_FREQ));
  59         return ns;
  60 }
  61
  62 unsigned long do_slow_gettimeoffset(void)
  63 {
  64         unsigned long count;
  65
  66         /* The timer interrupt comes from Etrax timer 0. In order to get
  67          * better precision, we check the current value. It might have
  68          * underflowed already though.
  69          */
  70         count = *R_TIMER0_DATA;
  71
  72         /* Convert timer value to usec */
  73         return (TIMER0_DIV - count) * ((NSEC_PER_SEC/1000)/HZ)/TIMER0_DIV;
  74 }
  75
  76 /* Excerpt from the Etrax100 HSDD about the built-in watchdog:
  77  *
  78  * 3.10.4 Watchdog timer
  79
  80  * When the watchdog timer is started, it generates an NMI if the watchdog
  81  * isn't restarted or stopped within 0.1 s. If it still isn't restarted or
  82  * stopped after an additional 3.3 ms, the watchdog resets the chip.
  83  * The watchdog timer is stopped after reset. The watchdog timer is controlled
  84  * by the R_WATCHDOG register. The R_WATCHDOG register contains an enable bit
  85  * and a 3-bit key value. The effect of writing to the R_WATCHDOG register is
  86  * described in the table below:
  87  *
  88  *   Watchdog    Value written:
  89  *   state:      To enable:  To key:      Operation:
  90  *   --------    ----------  -------      ----------
  91  *   stopped         0         X          No effect.
  92  *   stopped         1       key_val      Start watchdog with key = key_val.
  93  *   started         0       ~key         Stop watchdog
  94  *   started         1       ~key         Restart watchdog with key = ~key.
  95  *   started         X       new_key_val  Change key to new_key_val.
  96  *
  97  * Note: '~' is the bitwise NOT operator.
  98  *
  99  */
 100
 101 /* right now, starting the watchdog is the same as resetting it */
 102 #define start_watchdog reset_watchdog
 103
 104 #if defined(CONFIG_ETRAX_WATCHDOG) && !defined(CONFIG_SVINTO_SIM)
 105 static int watchdog_key = 0;  /* arbitrary number */
 106 #endif
 107
 108 /* number of pages to consider "out of memory". it is normal that the memory
 109  * is used though, so put this really low.
 110  */
 111
 112 #define WATCHDOG_MIN_FREE_PAGES 8
 113
 114 void
 115 reset_watchdog(void)
 116 {
 117 #if defined(CONFIG_ETRAX_WATCHDOG) && !defined(CONFIG_SVINTO_SIM)
 118         /* only keep watchdog happy as long as we have memory left! */
 119         if(nr_free_pages() > WATCHDOG_MIN_FREE_PAGES) {
 120                 /* reset the watchdog with the inverse of the old key */
 121                 watchdog_key ^= 0x7; /* invert key, which is 3 bits */
 122                 *R_WATCHDOG = IO_FIELD(R_WATCHDOG, key, watchdog_key) |
 123                         IO_STATE(R_WATCHDOG, enable, start);
 124         }
 125 #endif
 126 }
 127
 128 /* stop the watchdog - we still need the correct key */
 129
 130 void
 131 stop_watchdog(void)
 132 {
 133 #if defined(CONFIG_ETRAX_WATCHDOG) && !defined(CONFIG_SVINTO_SIM)
 134         watchdog_key ^= 0x7; /* invert key, which is 3 bits */
 135         *R_WATCHDOG = IO_FIELD(R_WATCHDOG, key, watchdog_key) |
 136                 IO_STATE(R_WATCHDOG, enable, stop);
 137 #endif
 138 }
 139
 140
 141 /*
 142  * timer_interrupt() needs to keep up the real-time clock,
 143  * as well as call the "do_timer()" routine every clocktick
 144  */
 145
 146 //static unsigned short myjiff; /* used by our debug routine print_timestamp */
 147
 148 extern void cris_do_profile(struct pt_regs *regs);
 149
 150 static inline irqreturn_t
 151 timer_interrupt(int irq, void *dev_id)
 152 {
 153         struct pt_regs *regs = get_irq_regs();
 154         /* acknowledge the timer irq */
 155
 156 #ifdef USE_CASCADE_TIMERS
 157         *R_TIMER_CTRL =
 158                 IO_FIELD( R_TIMER_CTRL, timerdiv1, 0) |
 159                 IO_FIELD( R_TIMER_CTRL, timerdiv0, 0) |
 160                 IO_STATE( R_TIMER_CTRL, i1, clr) |
 161                 IO_STATE( R_TIMER_CTRL, tm1, run) |
 162                 IO_STATE( R_TIMER_CTRL, clksel1, cascade0) |
 163                 IO_STATE( R_TIMER_CTRL, i0, clr) |
 164                 IO_STATE( R_TIMER_CTRL, tm0, run) |
 165                 IO_STATE( R_TIMER_CTRL, clksel0, c6250kHz);
 166 #else
 167         *R_TIMER_CTRL = r_timer_ctrl_shadow |
 168                 IO_STATE(R_TIMER_CTRL, i0, clr);
 169 #endif
 170
 171         /* reset watchdog otherwise it resets us! */
 172         reset_watchdog();
 173
 174         /* Update statistics. */
 175         update_process_times(user_mode(regs));
 176
 177         /* call the real timer interrupt handler */
 178
 179         do_timer(1);
 180
 181         cris_do_profile(regs); /* Save profiling information */
 182         return IRQ_HANDLED;
 183 }
 184
 185 /* timer is IRQF_SHARED so drivers can add stuff to the timer irq chain
 186  * it needs to be IRQF_DISABLED to make the jiffies update work properly
 187  */
 188
 189 static struct irqaction irq2  = {
 190         .handler = timer_interrupt,
 191         .flags = IRQF_SHARED | IRQF_DISABLED,
 192         .name = "timer",
 193 };
 194
 195 void __init
 196 time_init(void)
 197 {
 198         /* probe for the RTC and read it if it exists
 199          * Before the RTC can be probed the loops_per_usec variable needs
 200          * to be initialized to make usleep work. A better value for
 201          * loops_per_usec is calculated by the kernel later once the
 202          * clock has started.
 203          */
 204         loops_per_usec = 50;
 205
 206         if(RTC_INIT() < 0)
 207                 have_rtc = 0;
 208         else
 209                 have_rtc = 1;
 210
 211         /* Setup the etrax timers
 212          * Base frequency is 25000 hz, divider 250 -> 100 HZ
 213          * In normal mode, we use timer0, so timer1 is free. In cascade
 214          * mode (which we sometimes use for debugging) both timers are used.
 215          * Remember that linux/timex.h contains #defines that rely on the
 216          * timer settings below (hz and divide factor) !!!
 217          */
 218
 219 #ifdef USE_CASCADE_TIMERS
 220         *R_TIMER_CTRL =
 221                 IO_FIELD( R_TIMER_CTRL, timerdiv1, 0) |
 222                 IO_FIELD( R_TIMER_CTRL, timerdiv0, 0) |
 223                 IO_STATE( R_TIMER_CTRL, i1, nop) |
 224                 IO_STATE( R_TIMER_CTRL, tm1, stop_ld) |
 225                 IO_STATE( R_TIMER_CTRL, clksel1, cascade0) |
 226                 IO_STATE( R_TIMER_CTRL, i0, nop) |
 227                 IO_STATE( R_TIMER_CTRL, tm0, stop_ld) |
 228                 IO_STATE( R_TIMER_CTRL, clksel0, c6250kHz);
 229
 230         *R_TIMER_CTRL = r_timer_ctrl_shadow =
 231                 IO_FIELD( R_TIMER_CTRL, timerdiv1, 0) |
 232                 IO_FIELD( R_TIMER_CTRL, timerdiv0, 0) |
 233                 IO_STATE( R_TIMER_CTRL, i1, nop) |
 234                 IO_STATE( R_TIMER_CTRL, tm1, run) |
 235                 IO_STATE( R_TIMER_CTRL, clksel1, cascade0) |
 236                 IO_STATE( R_TIMER_CTRL, i0, nop) |
 237                 IO_STATE( R_TIMER_CTRL, tm0, run) |
 238                 IO_STATE( R_TIMER_CTRL, clksel0, c6250kHz);
 239 #else
 240         *R_TIMER_CTRL =
 241                 IO_FIELD(R_TIMER_CTRL, timerdiv1, 192)      |
 242                 IO_FIELD(R_TIMER_CTRL, timerdiv0, TIMER0_DIV)      |
 243                 IO_STATE(R_TIMER_CTRL, i1,        nop)      |
 244                 IO_STATE(R_TIMER_CTRL, tm1,       stop_ld)  |
 245                 IO_STATE(R_TIMER_CTRL, clksel1,   c19k2Hz)  |
 246                 IO_STATE(R_TIMER_CTRL, i0,        nop)      |
 247                 IO_STATE(R_TIMER_CTRL, tm0,       stop_ld)  |
 248                 IO_STATE(R_TIMER_CTRL, clksel0,   flexible);
 249
 250         *R_TIMER_CTRL = r_timer_ctrl_shadow =
 251                 IO_FIELD(R_TIMER_CTRL, timerdiv1, 192)      |
 252                 IO_FIELD(R_TIMER_CTRL, timerdiv0, TIMER0_DIV)      |
 253                 IO_STATE(R_TIMER_CTRL, i1,        nop)      |
 254                 IO_STATE(R_TIMER_CTRL, tm1,       run)      |
 255                 IO_STATE(R_TIMER_CTRL, clksel1,   c19k2Hz)  |
 256                 IO_STATE(R_TIMER_CTRL, i0,        nop)      |
 257                 IO_STATE(R_TIMER_CTRL, tm0,       run)      |
 258                 IO_STATE(R_TIMER_CTRL, clksel0,   flexible);
 259
 260         *R_TIMER_PRESCALE = PRESCALE_VALUE;
 261 #endif
 262
 263         *R_IRQ_MASK0_SET =
 264                 IO_STATE(R_IRQ_MASK0_SET, timer0, set); /* unmask the timer irq */
 265
 266         /* now actually register the timer irq handler that calls timer_interrupt() */
 267
 268         setup_irq(2, &irq2); /* irq 2 is the timer0 irq in etrax */
 269
 270         /* enable watchdog if we should use one */
 271
 272 #if defined(CONFIG_ETRAX_WATCHDOG) && !defined(CONFIG_SVINTO_SIM)
 273         printk("Enabling watchdog...\n");
 274         start_watchdog();
 275
 276         /* If we use the hardware watchdog, we want to trap it as an NMI
 277            and dump registers before it resets us.  For this to happen, we
 278            must set the "m" NMI enable flag (which once set, is unset only
 279            when an NMI is taken).
 280
 281            The same goes for the external NMI, but that doesn't have any
 282            driver or infrastructure support yet.  */
 283         asm ("setf m");
 284
 285         *R_IRQ_MASK0_SET =
 286                 IO_STATE(R_IRQ_MASK0_SET, watchdog_nmi, set);
 287         *R_VECT_MASK_SET =
 288                 IO_STATE(R_VECT_MASK_SET, nmi, set);
 289 #endif
 290 }