arch/frv/kernel/head-mmu-fr451.S

   1 /* head-mmu-fr451.S: FR451 mmu-linux specific bits of initialisation
   2  *
   3  * Copyright (C) 2004 Red Hat, Inc. All Rights Reserved.
   4  * Written by David Howells (dhowells@redhat.com)
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * as published by the Free Software Foundation; either version
   9  * 2 of the License, or (at your option) any later version.
  10  */
  11
  12 #include <linux/threads.h>
  13 #include <linux/linkage.h>
  14 #include <asm/ptrace.h>
  15 #include <asm/page.h>
  16 #include <asm/mem-layout.h>
  17 #include <asm/spr-regs.h>
  18 #include <asm/mb86943a.h>
  19 #include "head.inc"
  20
  21
  22 #define __400_DBR0      0xfe000e00
  23 #define __400_DBR1      0xfe000e08
  24 #define __400_DBR2      0xfe000e10
  25 #define __400_DBR3      0xfe000e18
  26 #define __400_DAM0      0xfe000f00
  27 #define __400_DAM1      0xfe000f08
  28 #define __400_DAM2      0xfe000f10
  29 #define __400_DAM3      0xfe000f18
  30 #define __400_LGCR      0xfe000010
  31 #define __400_LCR       0xfe000100
  32 #define __400_LSBR      0xfe000c00
  33
  34         .section        .text.init,"ax"
  35         .balign         4
  36
  37 ###############################################################################
  38 #
  39 # describe the position and layout of the SDRAM controller registers
  40 #
  41 #       ENTRY:                  EXIT:
  42 # GR5   -                       cacheline size
  43 # GR11  -                       displacement of 2nd SDRAM addr reg from GR14
  44 # GR12  -                       displacement of 3rd SDRAM addr reg from GR14
  45 # GR13  -                       displacement of 4th SDRAM addr reg from GR14
  46 # GR14  -                       address of 1st SDRAM addr reg
  47 # GR15  -                       amount to shift address by to match SDRAM addr reg
  48 # GR26  &__head_reference       [saved]
  49 # GR30  LED address             [saved]
  50 # CC0   -                       T if DBR0 is present
  51 # CC1   -                       T if DBR1 is present
  52 # CC2   -                       T if DBR2 is present
  53 # CC3   -                       T if DBR3 is present
  54 #
  55 ###############################################################################
  56         .globl          __head_fr451_describe_sdram
  57 __head_fr451_describe_sdram:
  58         sethi.p         %hi(__400_DBR0),gr14
  59         setlo           %lo(__400_DBR0),gr14
  60         setlos.p        #__400_DBR1-__400_DBR0,gr11
  61         setlos          #__400_DBR2-__400_DBR0,gr12
  62         setlos.p        #__400_DBR3-__400_DBR0,gr13
  63         setlos          #32,gr5                 ; cacheline size
  64         setlos.p        #0,gr15                 ; amount to shift addr reg by
  65         setlos          #0x00ff,gr4
  66         movgs           gr4,cccr                ; extant DARS/DAMK regs
  67         bralr
  68
  69 ###############################################################################
  70 #
  71 # rearrange the bus controller registers
  72 #
  73 #       ENTRY:                  EXIT:
  74 # GR26  &__head_reference       [saved]
  75 # GR30  LED address             revised LED address
  76 #
  77 ###############################################################################
  78         .globl          __head_fr451_set_busctl
  79 __head_fr451_set_busctl:
  80         sethi.p         %hi(__400_LGCR),gr4
  81         setlo           %lo(__400_LGCR),gr4
  82         sethi.p         %hi(__400_LSBR),gr10
  83         setlo           %lo(__400_LSBR),gr10
  84         sethi.p         %hi(__400_LCR),gr11
  85         setlo           %lo(__400_LCR),gr11
  86
  87         # set the bus controller
  88         ldi             @(gr4,#0),gr5
  89         ori             gr5,#0xff,gr5           ; make sure all chip-selects are enabled
  90         sti             gr5,@(gr4,#0)
  91
  92         sethi.p         %hi(__region_CS1),gr4
  93         setlo           %lo(__region_CS1),gr4
  94         sethi.p         %hi(__region_CS1_M),gr5
  95         setlo           %lo(__region_CS1_M),gr5
  96         sethi.p         %hi(__region_CS1_C),gr6
  97         setlo           %lo(__region_CS1_C),gr6
  98         sti             gr4,@(gr10,#1*0x08)
  99         sti             gr5,@(gr10,#1*0x08+0x100)
 100         sti             gr6,@(gr11,#1*0x08)
 101         sethi.p         %hi(__region_CS2),gr4
 102         setlo           %lo(__region_CS2),gr4
 103         sethi.p         %hi(__region_CS2_M),gr5
 104         setlo           %lo(__region_CS2_M),gr5
 105         sethi.p         %hi(__region_CS2_C),gr6
 106         setlo           %lo(__region_CS2_C),gr6
 107         sti             gr4,@(gr10,#2*0x08)
 108         sti             gr5,@(gr10,#2*0x08+0x100)
 109         sti             gr6,@(gr11,#2*0x08)
 110         sethi.p         %hi(__region_CS3),gr4
 111         setlo           %lo(__region_CS3),gr4
 112         sethi.p         %hi(__region_CS3_M),gr5
 113         setlo           %lo(__region_CS3_M),gr5
 114         sethi.p         %hi(__region_CS3_C),gr6
 115         setlo           %lo(__region_CS3_C),gr6
 116         sti             gr4,@(gr10,#3*0x08)
 117         sti             gr5,@(gr10,#3*0x08+0x100)
 118         sti             gr6,@(gr11,#3*0x08)
 119         sethi.p         %hi(__region_CS4),gr4
 120         setlo           %lo(__region_CS4),gr4
 121         sethi.p         %hi(__region_CS4_M),gr5
 122         setlo           %lo(__region_CS4_M),gr5
 123         sethi.p         %hi(__region_CS4_C),gr6
 124         setlo           %lo(__region_CS4_C),gr6
 125         sti             gr4,@(gr10,#4*0x08)
 126         sti             gr5,@(gr10,#4*0x08+0x100)
 127         sti             gr6,@(gr11,#4*0x08)
 128         sethi.p         %hi(__region_CS5),gr4
 129         setlo           %lo(__region_CS5),gr4
 130         sethi.p         %hi(__region_CS5_M),gr5
 131         setlo           %lo(__region_CS5_M),gr5
 132         sethi.p         %hi(__region_CS5_C),gr6
 133         setlo           %lo(__region_CS5_C),gr6
 134         sti             gr4,@(gr10,#5*0x08)
 135         sti             gr5,@(gr10,#5*0x08+0x100)
 136         sti             gr6,@(gr11,#5*0x08)
 137         sethi.p         %hi(__region_CS6),gr4
 138         setlo           %lo(__region_CS6),gr4
 139         sethi.p         %hi(__region_CS6_M),gr5
 140         setlo           %lo(__region_CS6_M),gr5
 141         sethi.p         %hi(__region_CS6_C),gr6
 142         setlo           %lo(__region_CS6_C),gr6
 143         sti             gr4,@(gr10,#6*0x08)
 144         sti             gr5,@(gr10,#6*0x08+0x100)
 145         sti             gr6,@(gr11,#6*0x08)
 146         sethi.p         %hi(__region_CS7),gr4
 147         setlo           %lo(__region_CS7),gr4
 148         sethi.p         %hi(__region_CS7_M),gr5
 149         setlo           %lo(__region_CS7_M),gr5
 150         sethi.p         %hi(__region_CS7_C),gr6
 151         setlo           %lo(__region_CS7_C),gr6
 152         sti             gr4,@(gr10,#7*0x08)
 153         sti             gr5,@(gr10,#7*0x08+0x100)
 154         sti             gr6,@(gr11,#7*0x08)
 155         membar
 156         bar
 157
 158         # adjust LED bank address
 159 #ifdef CONFIG_MB93091_VDK
 160         sethi.p         %hi(__region_CS2 + 0x01200004),gr30
 161         setlo           %lo(__region_CS2 + 0x01200004),gr30
 162 #endif
 163         bralr
 164
 165 ###############################################################################
 166 #
 167 # determine the total SDRAM size
 168 #
 169 #       ENTRY:                  EXIT:
 170 # GR25  -                       SDRAM size
 171 # GR26  &__head_reference       [saved]
 172 # GR30  LED address             [saved]
 173 #
 174 ###############################################################################
 175         .globl          __head_fr451_survey_sdram
 176 __head_fr451_survey_sdram:
 177         sethi.p         %hi(__400_DAM0),gr11
 178         setlo           %lo(__400_DAM0),gr11
 179         sethi.p         %hi(__400_DBR0),gr12
 180         setlo           %lo(__400_DBR0),gr12
 181
 182         sethi.p         %hi(0xfe000000),gr17            ; unused SDRAM DBR value
 183         setlo           %lo(0xfe000000),gr17
 184         setlos          #0,gr25
 185
 186         ldi             @(gr12,#0x00),gr4               ; DAR0
 187         subcc           gr4,gr17,gr0,icc0
 188         beq             icc0,#0,__head_no_DCS0
 189         ldi             @(gr11,#0x00),gr6               ; DAM0: bits 31:20 match addr 31:20
 190         add             gr25,gr6,gr25
 191         addi            gr25,#1,gr25
 192 __head_no_DCS0:
 193
 194         ldi             @(gr12,#0x08),gr4               ; DAR1
 195         subcc           gr4,gr17,gr0,icc0
 196         beq             icc0,#0,__head_no_DCS1
 197         ldi             @(gr11,#0x08),gr6               ; DAM1: bits 31:20 match addr 31:20
 198         add             gr25,gr6,gr25
 199         addi            gr25,#1,gr25
 200 __head_no_DCS1:
 201
 202         ldi             @(gr12,#0x10),gr4               ; DAR2
 203         subcc           gr4,gr17,gr0,icc0
 204         beq             icc0,#0,__head_no_DCS2
 205         ldi             @(gr11,#0x10),gr6               ; DAM2: bits 31:20 match addr 31:20
 206         add             gr25,gr6,gr25
 207         addi            gr25,#1,gr25
 208 __head_no_DCS2:
 209
 210         ldi             @(gr12,#0x18),gr4               ; DAR3
 211         subcc           gr4,gr17,gr0,icc0
 212         beq             icc0,#0,__head_no_DCS3
 213         ldi             @(gr11,#0x18),gr6               ; DAM3: bits 31:20 match addr 31:20
 214         add             gr25,gr6,gr25
 215         addi            gr25,#1,gr25
 216 __head_no_DCS3:
 217         bralr
 218
 219 ###############################################################################
 220 #
 221 # set the protection map with the I/DAMPR registers
 222 #
 223 #       ENTRY:                  EXIT:
 224 # GR25  SDRAM size              [saved]
 225 # GR26  &__head_reference       [saved]
 226 # GR30  LED address             [saved]
 227 #
 228 #
 229 # Using this map:
 230 #       REGISTERS       ADDRESS RANGE           VIEW
 231 #       =============== ======================  ===============================
 232 #       IAMPR0/DAMPR0   0xC0000000-0xCFFFFFFF   Cached kernel RAM Window
 233 #       DAMPR11         0xE0000000-0xFFFFFFFF   Uncached I/O
 234 #
 235 ###############################################################################
 236         .globl          __head_fr451_set_protection
 237 __head_fr451_set_protection:
 238         movsg           lr,gr27
 239
 240         # set the I/O region protection registers for FR451 in MMU mode
 241 #define PGPROT_IO       xAMPRx_L|xAMPRx_M|xAMPRx_S_KERNEL|xAMPRx_C|xAMPRx_V
 242
 243         sethi.p         %hi(__region_IO),gr5
 244         setlo           %lo(__region_IO),gr5
 245         setlos          #PGPROT_IO|xAMPRx_SS_512Mb,gr4
 246         or              gr4,gr5,gr4
 247         movgs           gr5,damlr11                     ; General I/O tile
 248         movgs           gr4,dampr11
 249
 250         # need to open a window onto at least part of the RAM for the kernel's use
 251         sethi.p         %hi(__sdram_base),gr8
 252         setlo           %lo(__sdram_base),gr8           ; physical address
 253         sethi.p         %hi(__page_offset),gr9
 254         setlo           %lo(__page_offset),gr9          ; virtual address
 255
 256         setlos          #xAMPRx_L|xAMPRx_M|xAMPRx_SS_256Mb|xAMPRx_S_KERNEL|xAMPRx_V,gr11
 257         or              gr8,gr11,gr8
 258
 259         movgs           gr9,iamlr0                      ; mapped from real address 0
 260         movgs           gr8,iampr0                      ; cached kernel memory at 0xC0000000
 261         movgs           gr9,damlr0
 262         movgs           gr8,dampr0
 263
 264         # set a temporary mapping for the kernel running at address 0 until we've turned on the MMU
 265         sethi.p         %hi(__sdram_base),gr9
 266         setlo           %lo(__sdram_base),gr9           ; virtual address
 267
 268         and.p           gr4,gr11,gr4
 269         and             gr5,gr11,gr5
 270         or.p            gr4,gr11,gr4
 271         or              gr5,gr11,gr5
 272
 273         movgs           gr9,iamlr1                      ; mapped from real address 0
 274         movgs           gr8,iampr1                      ; cached kernel memory at 0x00000000
 275         movgs           gr9,damlr1
 276         movgs           gr8,dampr1
 277
 278         # we use DAMR2-10 for kmap_atomic(), cache flush and TLB management
 279         # since the DAMLR regs are not going to change, we can set them now
 280         # also set up IAMLR2 to the same as DAMLR5
 281         sethi.p         %hi(KMAP_ATOMIC_PRIMARY_FRAME),gr4
 282         setlo           %lo(KMAP_ATOMIC_PRIMARY_FRAME),gr4
 283         sethi.p         %hi(PAGE_SIZE),gr5
 284         setlo           %lo(PAGE_SIZE),gr5
 285
 286         movgs           gr4,damlr2
 287         movgs           gr4,iamlr2
 288         add             gr4,gr5,gr4
 289         movgs           gr4,damlr3
 290         add             gr4,gr5,gr4
 291         movgs           gr4,damlr4
 292         add             gr4,gr5,gr4
 293         movgs           gr4,damlr5
 294         add             gr4,gr5,gr4
 295         movgs           gr4,damlr6
 296         add             gr4,gr5,gr4
 297         movgs           gr4,damlr7
 298         add             gr4,gr5,gr4
 299         movgs           gr4,damlr8
 300         add             gr4,gr5,gr4
 301         movgs           gr4,damlr9
 302         add             gr4,gr5,gr4
 303         movgs           gr4,damlr10
 304
 305         movgs           gr0,dampr2
 306         movgs           gr0,dampr4
 307         movgs           gr0,dampr5
 308         movgs           gr0,dampr6
 309         movgs           gr0,dampr7
 310         movgs           gr0,dampr8
 311         movgs           gr0,dampr9
 312         movgs           gr0,dampr10
 313
 314         movgs           gr0,iamlr3
 315         movgs           gr0,iamlr4
 316         movgs           gr0,iamlr5
 317         movgs           gr0,iamlr6
 318         movgs           gr0,iamlr7
 319
 320         movgs           gr0,iampr2
 321         movgs           gr0,iampr3
 322         movgs           gr0,iampr4
 323         movgs           gr0,iampr5
 324         movgs           gr0,iampr6
 325         movgs           gr0,iampr7
 326
 327         # start in TLB context 0 with the swapper's page tables
 328         movgs           gr0,cxnr
 329
 330         sethi.p         %hi(swapper_pg_dir),gr4
 331         setlo           %lo(swapper_pg_dir),gr4
 332         sethi.p         %hi(__page_offset),gr5
 333         setlo           %lo(__page_offset),gr5
 334         sub             gr4,gr5,gr4
 335         movgs           gr4,ttbr
 336         setlos          #xAMPRx_L|xAMPRx_M|xAMPRx_SS_16Kb|xAMPRx_S|xAMPRx_C|xAMPRx_V,gr5
 337         or              gr4,gr5,gr4
 338         movgs           gr4,dampr3
 339
 340         # the FR451 also has an extra trap base register
 341         movsg           tbr,gr4
 342         movgs           gr4,btbr
 343
 344         LEDS            0x3300
 345         jmpl            @(gr27,gr0)
 346
 347 ###############################################################################
 348 #
 349 # finish setting up the protection registers
 350 #
 351 ###############################################################################
 352         .globl          __head_fr451_finalise_protection
 353 __head_fr451_finalise_protection:
 354         # turn on the timers as appropriate
 355         movgs           gr0,timerh
 356         movgs           gr0,timerl
 357         movgs           gr0,timerd
 358         movsg           hsr0,gr4
 359         sethi.p         %hi(HSR0_ETMI),gr5
 360         setlo           %lo(HSR0_ETMI),gr5
 361         or              gr4,gr5,gr4
 362         movgs           gr4,hsr0
 363
 364         # clear the TLB entry cache
 365         movgs           gr0,iamlr1
 366         movgs           gr0,iampr1
 367         movgs           gr0,damlr1
 368         movgs           gr0,dampr1
 369
 370         # clear the PGE cache
 371         sethi.p         %hi(__flush_tlb_all),gr4
 372         setlo           %lo(__flush_tlb_all),gr4
 373         jmpl            @(gr4,gr0)