arch/frv/kernel/irq-mb93093.c

   1 /* irq-mb93093.c: MB93093 FPGA interrupt handling
   2  *
   3  * Copyright (C) 2006 Red Hat, Inc. All Rights Reserved.
   4  * Written by David Howells (dhowells@redhat.com)
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * as published by the Free Software Foundation; either version
   9  * 2 of the License, or (at your option) any later version.
  10  */
  11
  12 #include <linux/ptrace.h>
  13 #include <linux/errno.h>
  14 #include <linux/signal.h>
  15 #include <linux/sched.h>
  16 #include <linux/ioport.h>
  17 #include <linux/interrupt.h>
  18 #include <linux/init.h>
  19 #include <linux/irq.h>
  20
  21 #include <asm/io.h>
  22 #include <asm/system.h>
  23 #include <asm/bitops.h>
  24 #include <asm/delay.h>
  25 #include <asm/irq.h>
  26 #include <asm/irc-regs.h>
  27
  28 #define __reg16(ADDR) (*(volatile unsigned short *)(__region_CS2 + (ADDR)))
  29
  30 #define __get_IMR()     ({ __reg16(0x0a); })
  31 #define __set_IMR(M)    do { __reg16(0x0a) = (M);  wmb(); } while(0)
  32 #define __get_IFR()     ({ __reg16(0x02); })
  33 #define __clr_IFR(M)    do { __reg16(0x02) = ~(M); wmb(); } while(0)
  34
  35 /*
  36  * off-CPU FPGA PIC operations
  37  */
  38 static void frv_fpga_enable(unsigned int irq)
  39 {
  40         uint16_t imr = __get_IMR();
  41
  42         imr &= ~(1 << (irq - IRQ_BASE_FPGA));
  43
  44         __set_IMR(imr);
  45 }
  46
  47 static void frv_fpga_disable(unsigned int irq)
  48 {
  49         uint16_t imr = __get_IMR();
  50
  51         imr |= 1 << (irq - IRQ_BASE_FPGA);
  52
  53         __set_IMR(imr);
  54 }
  55
  56 static void frv_fpga_ack(unsigned int irq)
  57 {
  58         __clr_IFR(1 << (irq - IRQ_BASE_FPGA));
  59 }
  60
  61 static void frv_fpga_end(unsigned int irq)
  62 {
  63 }
  64
  65 static struct irq_chip frv_fpga_pic = {
  66         .name           = "mb93093",
  67         .enable         = frv_fpga_enable,
  68         .disable        = frv_fpga_disable,
  69         .ack            = frv_fpga_ack,
  70         .mask           = frv_fpga_disable,
  71         .unmask         = frv_fpga_enable,
  72         .end            = frv_fpga_end,
  73 };
  74
  75 /*
  76  * FPGA PIC interrupt handler
  77  */
  78 static irqreturn_t fpga_interrupt(int irq, void *_mask, struct pt_regs *regs)
  79 {
  80         uint16_t imr, mask = (unsigned long) _mask;
  81         irqreturn_t iret = 0;
  82
  83         imr = __get_IMR();
  84         mask = mask & ~imr & __get_IFR();
  85
  86         /* poll all the triggered IRQs */
  87         while (mask) {
  88                 int irq;
  89
  90                 asm("scan %1,gr0,%0" : "=r"(irq) : "r"(mask));
  91                 irq = 31 - irq;
  92                 mask &= ~(1 << irq);
  93
  94                 if (__do_IRQ(IRQ_BASE_FPGA + irq, regs))
  95                         iret |= IRQ_HANDLED;
  96         }
  97
  98         return iret;
  99 }
 100
 101 /*
 102  * define an interrupt action for each FPGA PIC output
 103  * - use dev_id to indicate the FPGA PIC input to output mappings
 104  */
 105 static struct irqaction fpga_irq[1]  = {
 106         [0] = {
 107                 .handler        = fpga_interrupt,
 108                 .flags          = IRQF_DISABLED,
 109                 .mask           = CPU_MASK_NONE,
 110                 .name           = "fpga.0",
 111                 .dev_id         = (void *) 0x0700UL,
 112         }
 113 };
 114
 115 /*
 116  * initialise the motherboard FPGA's PIC
 117  */
 118 void __init fpga_init(void)
 119 {
 120         int irq;
 121
 122         /* all PIC inputs are all set to be edge triggered */
 123         __set_IMR(0x0700);
 124         __clr_IFR(0x0000);
 125
 126         for (irq = IRQ_BASE_FPGA + 8; irq <= IRQ_BASE_FPGA + 10; irq++)
 127                 set_irq_chip_and_handler(irq, &frv_fpga_pic, handle_edge_irq);
 128
 129         /* the FPGA drives external IRQ input #2 on the CPU PIC */
 130         setup_irq(IRQ_CPU_EXTERNAL2, &fpga_irq[0]);
 131 }