arch/frv/kernel/irq.c

   1 /* irq.c: FRV IRQ handling
   2  *
   3  * Copyright (C) 2003, 2004, 2006 Red Hat, Inc. All Rights Reserved.
   4  * Written by David Howells (dhowells@redhat.com)
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * as published by the Free Software Foundation; either version
   9  * 2 of the License, or (at your option) any later version.
  10  */
  11
  12 #include <linux/ptrace.h>
  13 #include <linux/errno.h>
  14 #include <linux/signal.h>
  15 #include <linux/sched.h>
  16 #include <linux/ioport.h>
  17 #include <linux/interrupt.h>
  18 #include <linux/timex.h>
  19 #include <linux/slab.h>
  20 #include <linux/random.h>
  21 #include <linux/smp_lock.h>
  22 #include <linux/init.h>
  23 #include <linux/kernel_stat.h>
  24 #include <linux/irq.h>
  25 #include <linux/proc_fs.h>
  26 #include <linux/seq_file.h>
  27 #include <linux/module.h>
  28
  29 #include <asm/atomic.h>
  30 #include <asm/io.h>
  31 #include <asm/smp.h>
  32 #include <asm/system.h>
  33 #include <asm/bitops.h>
  34 #include <asm/uaccess.h>
  35 #include <asm/pgalloc.h>
  36 #include <asm/delay.h>
  37 #include <asm/irq.h>
  38 #include <asm/irc-regs.h>
  39 #include <asm/gdb-stub.h>
  40
  41 #define set_IRR(N,A,B,C,D) __set_IRR(N, (A << 28) | (B << 24) | (C << 20) | (D << 16))
  42
  43 extern void __init fpga_init(void);
  44 #ifdef CONFIG_FUJITSU_MB93493
  45 extern void __init mb93493_init(void);
  46 #endif
  47
  48 #define __reg16(ADDR) (*(volatile unsigned short *)(ADDR))
  49
  50 atomic_t irq_err_count;
  51
  52 /*
  53  * Generic, controller-independent functions:
  54  */
  55 int show_interrupts(struct seq_file *p, void *v)
  56 {
  57         int i = *(loff_t *) v, cpu;
  58         struct irqaction * action;
  59         unsigned long flags;
  60
  61         if (i == 0) {
  62                 char cpuname[12];
  63
  64                 seq_printf(p, "    ");
  65                 for_each_present_cpu(cpu) {
  66                         sprintf(cpuname, "CPU%d", cpu);
  67                         seq_printf(p, " %10s", cpuname);
  68                 }
  69                 seq_putc(p, '\n');
  70         }
  71
  72         if (i < NR_IRQS) {
  73                 spin_lock_irqsave(&irq_desc[i].lock, flags);
  74                 action = irq_desc[i].action;
  75                 if (action) {
  76                         seq_printf(p, "%3d: ", i);
  77                         for_each_present_cpu(cpu)
  78                                 seq_printf(p, "%10u ", kstat_cpu(cpu).irqs[i]);
  79                         seq_printf(p, " %10s", irq_desc[i].chip->name ? : "-");
  80                         seq_printf(p, "  %s", action->name);
  81                         for (action = action->next;
  82                              action;
  83                              action = action->next)
  84                                 seq_printf(p, ", %s", action->name);
  85
  86                         seq_putc(p, '\n');
  87                 }
  88
  89                 spin_unlock_irqrestore(&irq_desc[i].lock, flags);
  90         } else if (i == NR_IRQS) {
  91                 seq_printf(p, "Err: %10u\n", atomic_read(&irq_err_count));
  92         }
  93
  94         return 0;
  95 }
  96
  97 /*
  98  * on-CPU PIC operations
  99  */
 100 static void frv_cpupic_ack(unsigned int irqlevel)
 101 {
 102         __clr_RC(irqlevel);
 103         __clr_IRL();
 104 }
 105
 106 static void frv_cpupic_mask(unsigned int irqlevel)
 107 {
 108         __set_MASK(irqlevel);
 109 }
 110
 111 static void frv_cpupic_mask_ack(unsigned int irqlevel)
 112 {
 113         __set_MASK(irqlevel);
 114         __clr_RC(irqlevel);
 115         __clr_IRL();
 116 }
 117
 118 static void frv_cpupic_unmask(unsigned int irqlevel)
 119 {
 120         __clr_MASK(irqlevel);
 121 }
 122
 123 static void frv_cpupic_end(unsigned int irqlevel)
 124 {
 125         __clr_MASK(irqlevel);
 126 }
 127
 128 static struct irq_chip frv_cpu_pic = {
 129         .name           = "cpu",
 130         .ack            = frv_cpupic_ack,
 131         .mask           = frv_cpupic_mask,
 132         .mask_ack       = frv_cpupic_mask_ack,
 133         .unmask         = frv_cpupic_unmask,
 134         .end            = frv_cpupic_end,
 135 };
 136
 137 /*
 138  * handles all normal device IRQ's
 139  * - registers are referred to by the __frame variable (GR28)
 140  * - IRQ distribution is complicated in this arch because of the many PICs, the
 141  *   way they work and the way they cascade
 142  */
 143 asmlinkage void do_IRQ(void)
 144 {
 145         irq_enter();
 146         generic_handle_irq(__get_IRL(), __frame);
 147         irq_exit();
 148 }
 149
 150 /*
 151  * handles all NMIs when not co-opted by the debugger
 152  * - registers are referred to by the __frame variable (GR28)
 153  */
 154 asmlinkage void do_NMI(void)
 155 {
 156 }
 157
 158 /*
 159  * initialise the interrupt system
 160  */
 161 void __init init_IRQ(void)
 162 {
 163         int level;
 164
 165         for (level = 1; level <= 14; level++)
 166                 set_irq_chip_and_handler(level, &frv_cpu_pic,
 167                                          handle_level_irq);
 168
 169         set_irq_handler(IRQ_CPU_TIMER0, handle_edge_irq);
 170
 171         /* set the trigger levels for internal interrupt sources
 172          * - timers all falling-edge
 173          * - ERR0 is rising-edge
 174          * - all others are high-level
 175          */
 176         __set_IITMR(0, 0x003f0000);     /* DMA0-3, TIMER0-2 */
 177         __set_IITMR(1, 0x20000000);     /* ERR0-1, UART0-1, DMA4-7 */
 178
 179         /* route internal interrupts */
 180         set_IRR(4, IRQ_DMA3_LEVEL, IRQ_DMA2_LEVEL, IRQ_DMA1_LEVEL,
 181                 IRQ_DMA0_LEVEL);
 182         set_IRR(5, 0, IRQ_TIMER2_LEVEL, IRQ_TIMER1_LEVEL, IRQ_TIMER0_LEVEL);
 183         set_IRR(6, IRQ_GDBSTUB_LEVEL, IRQ_GDBSTUB_LEVEL,
 184                 IRQ_UART1_LEVEL, IRQ_UART0_LEVEL);
 185         set_IRR(7, IRQ_DMA7_LEVEL, IRQ_DMA6_LEVEL, IRQ_DMA5_LEVEL,
 186                 IRQ_DMA4_LEVEL);
 187
 188         /* route external interrupts */
 189         set_IRR(2, IRQ_XIRQ7_LEVEL, IRQ_XIRQ6_LEVEL, IRQ_XIRQ5_LEVEL,
 190                 IRQ_XIRQ4_LEVEL);
 191         set_IRR(3, IRQ_XIRQ3_LEVEL, IRQ_XIRQ2_LEVEL, IRQ_XIRQ1_LEVEL,
 192                 IRQ_XIRQ0_LEVEL);
 193
 194 #if defined(CONFIG_MB93091_VDK)
 195         __set_TM1(0x55550000);          /* XIRQ7-0 all active low */
 196 #elif defined(CONFIG_MB93093_PDK)
 197         __set_TM1(0x15550000);          /* XIRQ7 active high, 6-0 all active low */
 198 #else
 199 #error dont know external IRQ trigger levels for this setup
 200 #endif
 201
 202         fpga_init();
 203 #ifdef CONFIG_FUJITSU_MB93493
 204         mb93493_init();
 205 #endif
 206 }