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[deliverable/linux.git] / arch / frv / kernel / setup.c
1 /* setup.c: FRV specific setup
2 *
3 * Copyright (C) 2003-5 Red Hat, Inc. All Rights Reserved.
4 * Written by David Howells (dhowells@redhat.com)
5 * - Derived from arch/m68k/kernel/setup.c
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version
10 * 2 of the License, or (at your option) any later version.
11 */
12
13 #include <linux/utsrelease.h>
14 #include <linux/kernel.h>
15 #include <linux/sched.h>
16 #include <linux/delay.h>
17 #include <linux/interrupt.h>
18 #include <linux/fs.h>
19 #include <linux/mm.h>
20 #include <linux/fb.h>
21 #include <linux/console.h>
22 #include <linux/genhd.h>
23 #include <linux/errno.h>
24 #include <linux/string.h>
25 #include <linux/major.h>
26 #include <linux/bootmem.h>
27 #include <linux/highmem.h>
28 #include <linux/seq_file.h>
29 #include <linux/serial.h>
30 #include <linux/serial_core.h>
31 #include <linux/serial_reg.h>
32
33 #include <asm/setup.h>
34 #include <asm/serial.h>
35 #include <asm/irq.h>
36 #include <asm/sections.h>
37 #include <asm/pgalloc.h>
38 #include <asm/busctl-regs.h>
39 #include <asm/serial-regs.h>
40 #include <asm/timer-regs.h>
41 #include <asm/irc-regs.h>
42 #include <asm/spr-regs.h>
43 #include <asm/mb-regs.h>
44 #include <asm/mb93493-regs.h>
45 #include <asm/gdb-stub.h>
46 #include <asm/irq-routing.h>
47 #include <asm/io.h>
48
49 #ifdef CONFIG_BLK_DEV_INITRD
50 #include <linux/blk.h>
51 #include <asm/pgtable.h>
52 #endif
53
54 #include "local.h"
55
56 #ifdef CONFIG_MB93090_MB00
57 static void __init mb93090_display(void);
58 #endif
59 #ifdef CONFIG_MMU
60 static void __init setup_linux_memory(void);
61 #else
62 static void __init setup_uclinux_memory(void);
63 #endif
64
65 #ifdef CONFIG_CONSOLE
66 extern struct consw *conswitchp;
67 #endif
68
69 #ifdef CONFIG_MB93090_MB00
70 static char __initdata mb93090_banner[] = "FJ/RH FR-V Linux";
71 static char __initdata mb93090_version[] = UTS_RELEASE;
72
73 int __nongprelbss mb93090_mb00_detected;
74 #endif
75
76 const char __frv_unknown_system[] = "unknown";
77 const char __frv_mb93091_cb10[] = "mb93091-cb10";
78 const char __frv_mb93091_cb11[] = "mb93091-cb11";
79 const char __frv_mb93091_cb30[] = "mb93091-cb30";
80 const char __frv_mb93091_cb41[] = "mb93091-cb41";
81 const char __frv_mb93091_cb60[] = "mb93091-cb60";
82 const char __frv_mb93091_cb70[] = "mb93091-cb70";
83 const char __frv_mb93091_cb451[] = "mb93091-cb451";
84 const char __frv_mb93090_mb00[] = "mb93090-mb00";
85
86 const char __frv_mb93493[] = "mb93493";
87
88 const char __frv_mb93093[] = "mb93093";
89
90 static const char *__nongprelbss cpu_series;
91 static const char *__nongprelbss cpu_core;
92 static const char *__nongprelbss cpu_silicon;
93 static const char *__nongprelbss cpu_mmu;
94 static const char *__nongprelbss cpu_system;
95 static const char *__nongprelbss cpu_board1;
96 static const char *__nongprelbss cpu_board2;
97
98 static unsigned long __nongprelbss cpu_psr_all;
99 static unsigned long __nongprelbss cpu_hsr0_all;
100
101 unsigned long __nongprelbss pdm_suspend_mode;
102
103 unsigned long __nongprelbss rom_length;
104 unsigned long __nongprelbss memory_start;
105 unsigned long __nongprelbss memory_end;
106
107 unsigned long __nongprelbss dma_coherent_mem_start;
108 unsigned long __nongprelbss dma_coherent_mem_end;
109
110 unsigned long __initdata __sdram_old_base;
111 unsigned long __initdata num_mappedpages;
112
113 struct cpuinfo_frv __nongprelbss boot_cpu_data;
114
115 char command_line[COMMAND_LINE_SIZE];
116 char __initdata redboot_command_line[COMMAND_LINE_SIZE];
117
118 #ifdef CONFIG_PM
119 #define __pminit
120 #define __pminitdata
121 #else
122 #define __pminit __init
123 #define __pminitdata __initdata
124 #endif
125
126 struct clock_cmode {
127 uint8_t xbus, sdram, corebus, core, dsu;
128 };
129
130 #define _frac(N,D) ((N)<<4 | (D))
131 #define _x0_16 _frac(1,6)
132 #define _x0_25 _frac(1,4)
133 #define _x0_33 _frac(1,3)
134 #define _x0_375 _frac(3,8)
135 #define _x0_5 _frac(1,2)
136 #define _x0_66 _frac(2,3)
137 #define _x0_75 _frac(3,4)
138 #define _x1 _frac(1,1)
139 #define _x1_5 _frac(3,2)
140 #define _x2 _frac(2,1)
141 #define _x3 _frac(3,1)
142 #define _x4 _frac(4,1)
143 #define _x4_5 _frac(9,2)
144 #define _x6 _frac(6,1)
145 #define _x8 _frac(8,1)
146 #define _x9 _frac(9,1)
147
148 int __nongprelbss clock_p0_current;
149 int __nongprelbss clock_cm_current;
150 int __nongprelbss clock_cmode_current;
151 #ifdef CONFIG_PM
152 int __nongprelbss clock_cmodes_permitted;
153 unsigned long __nongprelbss clock_bits_settable;
154 #endif
155
156 static struct clock_cmode __pminitdata undef_clock_cmode = { _x1, _x1, _x1, _x1, _x1 };
157
158 static struct clock_cmode __pminitdata clock_cmodes_fr401_fr403[16] = {
159 [4] = { _x1, _x1, _x2, _x2, _x0_25 },
160 [5] = { _x1, _x2, _x4, _x4, _x0_5 },
161 [8] = { _x1, _x1, _x1, _x2, _x0_25 },
162 [9] = { _x1, _x2, _x2, _x4, _x0_5 },
163 [11] = { _x1, _x4, _x4, _x8, _x1 },
164 [12] = { _x1, _x1, _x2, _x4, _x0_5 },
165 [13] = { _x1, _x2, _x4, _x8, _x1 },
166 };
167
168 static struct clock_cmode __pminitdata clock_cmodes_fr405[16] = {
169 [0] = { _x1, _x1, _x1, _x1, _x0_5 },
170 [1] = { _x1, _x1, _x1, _x3, _x0_25 },
171 [2] = { _x1, _x1, _x2, _x6, _x0_5 },
172 [3] = { _x1, _x2, _x2, _x6, _x0_5 },
173 [4] = { _x1, _x1, _x2, _x2, _x0_16 },
174 [8] = { _x1, _x1, _x1, _x2, _x0_16 },
175 [9] = { _x1, _x2, _x2, _x4, _x0_33 },
176 [12] = { _x1, _x1, _x2, _x4, _x0_33 },
177 [14] = { _x1, _x3, _x3, _x9, _x0_75 },
178 [15] = { _x1, _x1_5, _x1_5, _x4_5, _x0_375 },
179
180 #define CLOCK_CMODES_PERMITTED_FR405 0xd31f
181 };
182
183 static struct clock_cmode __pminitdata clock_cmodes_fr555[16] = {
184 [0] = { _x1, _x2, _x2, _x4, _x0_33 },
185 [1] = { _x1, _x3, _x3, _x6, _x0_5 },
186 [2] = { _x1, _x2, _x4, _x8, _x0_66 },
187 [3] = { _x1, _x1_5, _x3, _x6, _x0_5 },
188 [4] = { _x1, _x3, _x3, _x9, _x0_75 },
189 [5] = { _x1, _x2, _x2, _x6, _x0_5 },
190 [6] = { _x1, _x1_5, _x1_5, _x4_5, _x0_375 },
191 };
192
193 static const struct clock_cmode __pminitdata *clock_cmodes;
194 static int __pminitdata clock_doubled;
195
196 static struct uart_port __initdata __frv_uart0 = {
197 .uartclk = 0,
198 .membase = (char *) UART0_BASE,
199 .irq = IRQ_CPU_UART0,
200 .regshift = 3,
201 .iotype = UPIO_MEM,
202 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
203 };
204
205 static struct uart_port __initdata __frv_uart1 = {
206 .uartclk = 0,
207 .membase = (char *) UART1_BASE,
208 .irq = IRQ_CPU_UART1,
209 .regshift = 3,
210 .iotype = UPIO_MEM,
211 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
212 };
213
214 #if 0
215 static void __init printk_xampr(unsigned long ampr, unsigned long amlr, char i_d, int n)
216 {
217 unsigned long phys, virt, cxn, size;
218
219 #ifdef CONFIG_MMU
220 virt = amlr & 0xffffc000;
221 cxn = amlr & 0x3fff;
222 #else
223 virt = ampr & 0xffffc000;
224 cxn = 0;
225 #endif
226 phys = ampr & xAMPRx_PPFN;
227 size = 1 << (((ampr & xAMPRx_SS) >> 4) + 17);
228
229 printk("%cAMPR%d: va %08lx-%08lx [pa %08lx] %c%c%c%c [cxn:%04lx]\n",
230 i_d, n,
231 virt, virt + size - 1,
232 phys,
233 ampr & xAMPRx_S ? 'S' : '-',
234 ampr & xAMPRx_C ? 'C' : '-',
235 ampr & DAMPRx_WP ? 'W' : '-',
236 ampr & xAMPRx_V ? 'V' : '-',
237 cxn
238 );
239 }
240 #endif
241
242 /*****************************************************************************/
243 /*
244 * dump the memory map
245 */
246 static void __init dump_memory_map(void)
247 {
248
249 #if 0
250 /* dump the protection map */
251 printk_xampr(__get_IAMPR(0), __get_IAMLR(0), 'I', 0);
252 printk_xampr(__get_IAMPR(1), __get_IAMLR(1), 'I', 1);
253 printk_xampr(__get_IAMPR(2), __get_IAMLR(2), 'I', 2);
254 printk_xampr(__get_IAMPR(3), __get_IAMLR(3), 'I', 3);
255 printk_xampr(__get_IAMPR(4), __get_IAMLR(4), 'I', 4);
256 printk_xampr(__get_IAMPR(5), __get_IAMLR(5), 'I', 5);
257 printk_xampr(__get_IAMPR(6), __get_IAMLR(6), 'I', 6);
258 printk_xampr(__get_IAMPR(7), __get_IAMLR(7), 'I', 7);
259 printk_xampr(__get_IAMPR(8), __get_IAMLR(8), 'I', 8);
260 printk_xampr(__get_IAMPR(9), __get_IAMLR(9), 'i', 9);
261 printk_xampr(__get_IAMPR(10), __get_IAMLR(10), 'I', 10);
262 printk_xampr(__get_IAMPR(11), __get_IAMLR(11), 'I', 11);
263 printk_xampr(__get_IAMPR(12), __get_IAMLR(12), 'I', 12);
264 printk_xampr(__get_IAMPR(13), __get_IAMLR(13), 'I', 13);
265 printk_xampr(__get_IAMPR(14), __get_IAMLR(14), 'I', 14);
266 printk_xampr(__get_IAMPR(15), __get_IAMLR(15), 'I', 15);
267
268 printk_xampr(__get_DAMPR(0), __get_DAMLR(0), 'D', 0);
269 printk_xampr(__get_DAMPR(1), __get_DAMLR(1), 'D', 1);
270 printk_xampr(__get_DAMPR(2), __get_DAMLR(2), 'D', 2);
271 printk_xampr(__get_DAMPR(3), __get_DAMLR(3), 'D', 3);
272 printk_xampr(__get_DAMPR(4), __get_DAMLR(4), 'D', 4);
273 printk_xampr(__get_DAMPR(5), __get_DAMLR(5), 'D', 5);
274 printk_xampr(__get_DAMPR(6), __get_DAMLR(6), 'D', 6);
275 printk_xampr(__get_DAMPR(7), __get_DAMLR(7), 'D', 7);
276 printk_xampr(__get_DAMPR(8), __get_DAMLR(8), 'D', 8);
277 printk_xampr(__get_DAMPR(9), __get_DAMLR(9), 'D', 9);
278 printk_xampr(__get_DAMPR(10), __get_DAMLR(10), 'D', 10);
279 printk_xampr(__get_DAMPR(11), __get_DAMLR(11), 'D', 11);
280 printk_xampr(__get_DAMPR(12), __get_DAMLR(12), 'D', 12);
281 printk_xampr(__get_DAMPR(13), __get_DAMLR(13), 'D', 13);
282 printk_xampr(__get_DAMPR(14), __get_DAMLR(14), 'D', 14);
283 printk_xampr(__get_DAMPR(15), __get_DAMLR(15), 'D', 15);
284 #endif
285
286 #if 0
287 /* dump the bus controller registers */
288 printk("LGCR: %08lx\n", __get_LGCR());
289 printk("Master: %08lx-%08lx CR=%08lx\n",
290 __get_LEMBR(), __get_LEMBR() + __get_LEMAM(),
291 __get_LMAICR());
292
293 int loop;
294 for (loop = 1; loop <= 7; loop++) {
295 unsigned long lcr = __get_LCR(loop), lsbr = __get_LSBR(loop);
296 printk("CS#%d: %08lx-%08lx %c%c%c%c%c%c%c%c%c\n",
297 loop,
298 lsbr, lsbr + __get_LSAM(loop),
299 lcr & 0x80000000 ? 'r' : '-',
300 lcr & 0x40000000 ? 'w' : '-',
301 lcr & 0x08000000 ? 'b' : '-',
302 lcr & 0x04000000 ? 'B' : '-',
303 lcr & 0x02000000 ? 'C' : '-',
304 lcr & 0x01000000 ? 'D' : '-',
305 lcr & 0x00800000 ? 'W' : '-',
306 lcr & 0x00400000 ? 'R' : '-',
307 (lcr & 0x00030000) == 0x00000000 ? '4' :
308 (lcr & 0x00030000) == 0x00010000 ? '2' :
309 (lcr & 0x00030000) == 0x00020000 ? '1' :
310 '-'
311 );
312 }
313 #endif
314
315 #if 0
316 printk("\n");
317 #endif
318 } /* end dump_memory_map() */
319
320 /*****************************************************************************/
321 /*
322 * attempt to detect a VDK motherboard and DAV daughter board on an MB93091 system
323 */
324 #ifdef CONFIG_MB93091_VDK
325 static void __init detect_mb93091(void)
326 {
327 #ifdef CONFIG_MB93090_MB00
328 /* Detect CB70 without motherboard */
329 if (!(cpu_system == __frv_mb93091_cb70 && ((*(unsigned short *)0xffc00030) & 0x100))) {
330 cpu_board1 = __frv_mb93090_mb00;
331 mb93090_mb00_detected = 1;
332 }
333 #endif
334
335 #ifdef CONFIG_FUJITSU_MB93493
336 cpu_board2 = __frv_mb93493;
337 #endif
338
339 } /* end detect_mb93091() */
340 #endif
341
342 /*****************************************************************************/
343 /*
344 * determine the CPU type and set appropriate parameters
345 *
346 * Family Series CPU Core Silicon Imple Vers
347 * ----------------------------------------------------------
348 * FR-V --+-> FR400 --+-> FR401 --+-> MB93401 02 00 [1]
349 * | | |
350 * | | +-> MB93401/A 02 01
351 * | | |
352 * | | +-> MB93403 02 02
353 * | |
354 * | +-> FR405 ----> MB93405 04 00
355 * |
356 * +-> FR450 ----> FR451 ----> MB93451 05 00
357 * |
358 * +-> FR500 ----> FR501 --+-> MB93501 01 01 [2]
359 * | |
360 * | +-> MB93501/A 01 02
361 * |
362 * +-> FR550 --+-> FR551 ----> MB93555 03 01
363 *
364 * [1] The MB93401 is an obsolete CPU replaced by the MB93401A
365 * [2] The MB93501 is an obsolete CPU replaced by the MB93501A
366 *
367 * Imple is PSR(Processor Status Register)[31:28].
368 * Vers is PSR(Processor Status Register)[27:24].
369 *
370 * A "Silicon" consists of CPU core and some on-chip peripherals.
371 */
372 static void __init determine_cpu(void)
373 {
374 unsigned long hsr0 = __get_HSR(0);
375 unsigned long psr = __get_PSR();
376
377 /* work out what selectable services the CPU supports */
378 __set_PSR(psr | PSR_EM | PSR_EF | PSR_CM | PSR_NEM);
379 cpu_psr_all = __get_PSR();
380 __set_PSR(psr);
381
382 __set_HSR(0, hsr0 | HSR0_GRLE | HSR0_GRHE | HSR0_FRLE | HSR0_FRHE);
383 cpu_hsr0_all = __get_HSR(0);
384 __set_HSR(0, hsr0);
385
386 /* derive other service specs from the CPU type */
387 cpu_series = "unknown";
388 cpu_core = "unknown";
389 cpu_silicon = "unknown";
390 cpu_mmu = "Prot";
391 cpu_system = __frv_unknown_system;
392 clock_cmodes = NULL;
393 clock_doubled = 0;
394 #ifdef CONFIG_PM
395 clock_bits_settable = CLOCK_BIT_CM_H | CLOCK_BIT_CM_M | CLOCK_BIT_P0;
396 #endif
397
398 switch (PSR_IMPLE(psr)) {
399 case PSR_IMPLE_FR401:
400 cpu_series = "fr400";
401 cpu_core = "fr401";
402 pdm_suspend_mode = HSR0_PDM_PLL_RUN;
403
404 switch (PSR_VERSION(psr)) {
405 case PSR_VERSION_FR401_MB93401:
406 cpu_silicon = "mb93401";
407 cpu_system = __frv_mb93091_cb10;
408 clock_cmodes = clock_cmodes_fr401_fr403;
409 clock_doubled = 1;
410 break;
411 case PSR_VERSION_FR401_MB93401A:
412 cpu_silicon = "mb93401/A";
413 cpu_system = __frv_mb93091_cb11;
414 clock_cmodes = clock_cmodes_fr401_fr403;
415 break;
416 case PSR_VERSION_FR401_MB93403:
417 cpu_silicon = "mb93403";
418 #ifndef CONFIG_MB93093_PDK
419 cpu_system = __frv_mb93091_cb30;
420 #else
421 cpu_system = __frv_mb93093;
422 #endif
423 clock_cmodes = clock_cmodes_fr401_fr403;
424 break;
425 default:
426 break;
427 }
428 break;
429
430 case PSR_IMPLE_FR405:
431 cpu_series = "fr400";
432 cpu_core = "fr405";
433 pdm_suspend_mode = HSR0_PDM_PLL_STOP;
434
435 switch (PSR_VERSION(psr)) {
436 case PSR_VERSION_FR405_MB93405:
437 cpu_silicon = "mb93405";
438 cpu_system = __frv_mb93091_cb60;
439 clock_cmodes = clock_cmodes_fr405;
440 #ifdef CONFIG_PM
441 clock_bits_settable |= CLOCK_BIT_CMODE;
442 clock_cmodes_permitted = CLOCK_CMODES_PERMITTED_FR405;
443 #endif
444
445 /* the FPGA on the CB70 has extra registers
446 * - it has 0x0046 in the VDK_ID FPGA register at 0x1a0, which is
447 * how we tell the difference between it and a CB60
448 */
449 if (*(volatile unsigned short *) 0xffc001a0 == 0x0046)
450 cpu_system = __frv_mb93091_cb70;
451 break;
452 default:
453 break;
454 }
455 break;
456
457 case PSR_IMPLE_FR451:
458 cpu_series = "fr450";
459 cpu_core = "fr451";
460 pdm_suspend_mode = HSR0_PDM_PLL_STOP;
461 #ifdef CONFIG_PM
462 clock_bits_settable |= CLOCK_BIT_CMODE;
463 clock_cmodes_permitted = CLOCK_CMODES_PERMITTED_FR405;
464 #endif
465 switch (PSR_VERSION(psr)) {
466 case PSR_VERSION_FR451_MB93451:
467 cpu_silicon = "mb93451";
468 cpu_mmu = "Prot, SAT, xSAT, DAT";
469 cpu_system = __frv_mb93091_cb451;
470 clock_cmodes = clock_cmodes_fr405;
471 break;
472 default:
473 break;
474 }
475 break;
476
477 case PSR_IMPLE_FR501:
478 cpu_series = "fr500";
479 cpu_core = "fr501";
480 pdm_suspend_mode = HSR0_PDM_PLL_STOP;
481
482 switch (PSR_VERSION(psr)) {
483 case PSR_VERSION_FR501_MB93501: cpu_silicon = "mb93501"; break;
484 case PSR_VERSION_FR501_MB93501A: cpu_silicon = "mb93501/A"; break;
485 default:
486 break;
487 }
488 break;
489
490 case PSR_IMPLE_FR551:
491 cpu_series = "fr550";
492 cpu_core = "fr551";
493 pdm_suspend_mode = HSR0_PDM_PLL_RUN;
494
495 switch (PSR_VERSION(psr)) {
496 case PSR_VERSION_FR551_MB93555:
497 cpu_silicon = "mb93555";
498 cpu_mmu = "Prot, SAT";
499 cpu_system = __frv_mb93091_cb41;
500 clock_cmodes = clock_cmodes_fr555;
501 clock_doubled = 1;
502 break;
503 default:
504 break;
505 }
506 break;
507
508 default:
509 break;
510 }
511
512 printk("- Series:%s CPU:%s Silicon:%s\n",
513 cpu_series, cpu_core, cpu_silicon);
514
515 #ifdef CONFIG_MB93091_VDK
516 detect_mb93091();
517 #endif
518
519 #if defined(CONFIG_MB93093_PDK) && defined(CONFIG_FUJITSU_MB93493)
520 cpu_board2 = __frv_mb93493;
521 #endif
522
523 } /* end determine_cpu() */
524
525 /*****************************************************************************/
526 /*
527 * calculate the bus clock speed
528 */
529 void __pminit determine_clocks(int verbose)
530 {
531 const struct clock_cmode *mode, *tmode;
532 unsigned long clkc, psr, quot;
533
534 clkc = __get_CLKC();
535 psr = __get_PSR();
536
537 clock_p0_current = !!(clkc & CLKC_P0);
538 clock_cm_current = clkc & CLKC_CM;
539 clock_cmode_current = (clkc & CLKC_CMODE) >> CLKC_CMODE_s;
540
541 if (verbose)
542 printk("psr=%08lx hsr0=%08lx clkc=%08lx\n", psr, __get_HSR(0), clkc);
543
544 /* the CB70 has some alternative ways of setting the clock speed through switches accessed
545 * through the FPGA. */
546 if (cpu_system == __frv_mb93091_cb70) {
547 unsigned short clkswr = *(volatile unsigned short *) 0xffc00104UL & 0x1fffUL;
548
549 if (clkswr & 0x1000)
550 __clkin_clock_speed_HZ = 60000000UL;
551 else
552 __clkin_clock_speed_HZ =
553 ((clkswr >> 8) & 0xf) * 10000000 +
554 ((clkswr >> 4) & 0xf) * 1000000 +
555 ((clkswr ) & 0xf) * 100000;
556 }
557 /* the FR451 is currently fixed at 24MHz */
558 else if (cpu_system == __frv_mb93091_cb451) {
559 //__clkin_clock_speed_HZ = 24000000UL; // CB451-FPGA
560 unsigned short clkswr = *(volatile unsigned short *) 0xffc00104UL & 0x1fffUL;
561
562 if (clkswr & 0x1000)
563 __clkin_clock_speed_HZ = 60000000UL;
564 else
565 __clkin_clock_speed_HZ =
566 ((clkswr >> 8) & 0xf) * 10000000 +
567 ((clkswr >> 4) & 0xf) * 1000000 +
568 ((clkswr ) & 0xf) * 100000;
569 }
570 /* otherwise determine the clockspeed from VDK or other registers */
571 else {
572 __clkin_clock_speed_HZ = __get_CLKIN();
573 }
574
575 /* look up the appropriate clock relationships table entry */
576 mode = &undef_clock_cmode;
577 if (clock_cmodes) {
578 tmode = &clock_cmodes[(clkc & CLKC_CMODE) >> CLKC_CMODE_s];
579 if (tmode->xbus)
580 mode = tmode;
581 }
582
583 #define CLOCK(SRC,RATIO) ((SRC) * (((RATIO) >> 4) & 0x0f) / ((RATIO) & 0x0f))
584
585 if (clock_doubled)
586 __clkin_clock_speed_HZ <<= 1;
587
588 __ext_bus_clock_speed_HZ = CLOCK(__clkin_clock_speed_HZ, mode->xbus);
589 __sdram_clock_speed_HZ = CLOCK(__clkin_clock_speed_HZ, mode->sdram);
590 __dsu_clock_speed_HZ = CLOCK(__clkin_clock_speed_HZ, mode->dsu);
591
592 switch (clkc & CLKC_CM) {
593 case 0: /* High */
594 __core_bus_clock_speed_HZ = CLOCK(__clkin_clock_speed_HZ, mode->corebus);
595 __core_clock_speed_HZ = CLOCK(__clkin_clock_speed_HZ, mode->core);
596 break;
597 case 1: /* Medium */
598 __core_bus_clock_speed_HZ = CLOCK(__clkin_clock_speed_HZ, mode->sdram);
599 __core_clock_speed_HZ = CLOCK(__clkin_clock_speed_HZ, mode->sdram);
600 break;
601 case 2: /* Low; not supported */
602 case 3: /* UNDEF */
603 printk("Unsupported CLKC CM %ld\n", clkc & CLKC_CM);
604 panic("Bye");
605 }
606
607 __res_bus_clock_speed_HZ = __ext_bus_clock_speed_HZ;
608 if (clkc & CLKC_P0)
609 __res_bus_clock_speed_HZ >>= 1;
610
611 if (verbose) {
612 printk("CLKIN: %lu.%3.3luMHz\n",
613 __clkin_clock_speed_HZ / 1000000,
614 (__clkin_clock_speed_HZ / 1000) % 1000);
615
616 printk("CLKS:"
617 " ext=%luMHz res=%luMHz sdram=%luMHz cbus=%luMHz core=%luMHz dsu=%luMHz\n",
618 __ext_bus_clock_speed_HZ / 1000000,
619 __res_bus_clock_speed_HZ / 1000000,
620 __sdram_clock_speed_HZ / 1000000,
621 __core_bus_clock_speed_HZ / 1000000,
622 __core_clock_speed_HZ / 1000000,
623 __dsu_clock_speed_HZ / 1000000
624 );
625 }
626
627 /* calculate the number of __delay() loop iterations per sec (2 insn loop) */
628 __delay_loops_MHz = __core_clock_speed_HZ / (1000000 * 2);
629
630 /* set the serial prescaler */
631 __serial_clock_speed_HZ = __res_bus_clock_speed_HZ;
632 quot = 1;
633 while (__serial_clock_speed_HZ / quot / 16 / 65536 > 3000)
634 quot += 1;
635
636 /* double the divisor if P0 is clear, so that if/when P0 is set, it's still achievable
637 * - we have to be careful - dividing too much can mean we can't get 115200 baud
638 */
639 if (__serial_clock_speed_HZ > 32000000 && !(clkc & CLKC_P0))
640 quot <<= 1;
641
642 __serial_clock_speed_HZ /= quot;
643 __frv_uart0.uartclk = __serial_clock_speed_HZ;
644 __frv_uart1.uartclk = __serial_clock_speed_HZ;
645
646 if (verbose)
647 printk(" uart=%luMHz\n", __serial_clock_speed_HZ / 1000000 * quot);
648
649 while (!(__get_UART0_LSR() & UART_LSR_TEMT))
650 continue;
651
652 while (!(__get_UART1_LSR() & UART_LSR_TEMT))
653 continue;
654
655 __set_UCPVR(quot);
656 __set_UCPSR(0);
657 } /* end determine_clocks() */
658
659 /*****************************************************************************/
660 /*
661 * reserve some DMA consistent memory
662 */
663 #ifdef CONFIG_RESERVE_DMA_COHERENT
664 static void __init reserve_dma_coherent(void)
665 {
666 unsigned long ampr;
667
668 /* find the first non-kernel memory tile and steal it */
669 #define __steal_AMPR(r) \
670 if (__get_DAMPR(r) & xAMPRx_V) { \
671 ampr = __get_DAMPR(r); \
672 __set_DAMPR(r, ampr | xAMPRx_S | xAMPRx_C); \
673 __set_IAMPR(r, 0); \
674 goto found; \
675 }
676
677 __steal_AMPR(1);
678 __steal_AMPR(2);
679 __steal_AMPR(3);
680 __steal_AMPR(4);
681 __steal_AMPR(5);
682 __steal_AMPR(6);
683
684 if (PSR_IMPLE(__get_PSR()) == PSR_IMPLE_FR551) {
685 __steal_AMPR(7);
686 __steal_AMPR(8);
687 __steal_AMPR(9);
688 __steal_AMPR(10);
689 __steal_AMPR(11);
690 __steal_AMPR(12);
691 __steal_AMPR(13);
692 __steal_AMPR(14);
693 }
694
695 /* unable to grant any DMA consistent memory */
696 printk("No DMA consistent memory reserved\n");
697 return;
698
699 found:
700 dma_coherent_mem_start = ampr & xAMPRx_PPFN;
701 ampr &= xAMPRx_SS;
702 ampr >>= 4;
703 ampr = 1 << (ampr - 3 + 20);
704 dma_coherent_mem_end = dma_coherent_mem_start + ampr;
705
706 printk("DMA consistent memory reserved %lx-%lx\n",
707 dma_coherent_mem_start, dma_coherent_mem_end);
708
709 } /* end reserve_dma_coherent() */
710 #endif
711
712 /*****************************************************************************/
713 /*
714 * calibrate the delay loop
715 */
716 void __init calibrate_delay(void)
717 {
718 loops_per_jiffy = __delay_loops_MHz * (1000000 / HZ);
719
720 printk("Calibrating delay loop... %lu.%02lu BogoMIPS\n",
721 loops_per_jiffy / (500000 / HZ),
722 (loops_per_jiffy / (5000 / HZ)) % 100);
723
724 } /* end calibrate_delay() */
725
726 /*****************************************************************************/
727 /*
728 * look through the command line for some things we need to know immediately
729 */
730 static void __init parse_cmdline_early(char *cmdline)
731 {
732 if (!cmdline)
733 return;
734
735 while (*cmdline) {
736 if (*cmdline == ' ')
737 cmdline++;
738
739 /* "mem=XXX[kKmM]" sets SDRAM size to <mem>, overriding the value we worked
740 * out from the SDRAM controller mask register
741 */
742 if (!memcmp(cmdline, "mem=", 4)) {
743 unsigned long long mem_size;
744
745 mem_size = memparse(cmdline + 4, &cmdline);
746 memory_end = memory_start + mem_size;
747 }
748
749 while (*cmdline && *cmdline != ' ')
750 cmdline++;
751 }
752
753 } /* end parse_cmdline_early() */
754
755 /*****************************************************************************/
756 /*
757 *
758 */
759 void __init setup_arch(char **cmdline_p)
760 {
761 #ifdef CONFIG_MMU
762 printk("Linux FR-V port done by Red Hat Inc <dhowells@redhat.com>\n");
763 #else
764 printk("uClinux FR-V port done by Red Hat Inc <dhowells@redhat.com>\n");
765 #endif
766
767 memcpy(saved_command_line, redboot_command_line, COMMAND_LINE_SIZE);
768
769 determine_cpu();
770 determine_clocks(1);
771
772 /* For printk-directly-beats-on-serial-hardware hack */
773 console_set_baud(115200);
774 #ifdef CONFIG_GDBSTUB
775 gdbstub_set_baud(115200);
776 #endif
777
778 #ifdef CONFIG_RESERVE_DMA_COHERENT
779 reserve_dma_coherent();
780 #endif
781 dump_memory_map();
782
783 #ifdef CONFIG_MB93090_MB00
784 if (mb93090_mb00_detected)
785 mb93090_display();
786 #endif
787
788 /* register those serial ports that are available */
789 #ifdef CONFIG_FRV_ONCPU_SERIAL
790 #ifndef CONFIG_GDBSTUB_UART0
791 __reg(UART0_BASE + UART_IER * 8) = 0;
792 early_serial_setup(&__frv_uart0);
793 #endif
794 #ifndef CONFIG_GDBSTUB_UART1
795 __reg(UART1_BASE + UART_IER * 8) = 0;
796 early_serial_setup(&__frv_uart1);
797 #endif
798 #endif
799
800 #if defined(CONFIG_CHR_DEV_FLASH) || defined(CONFIG_BLK_DEV_FLASH)
801 /* we need to initialize the Flashrom device here since we might
802 * do things with flash early on in the boot
803 */
804 flash_probe();
805 #endif
806
807 /* deal with the command line - RedBoot may have passed one to the kernel */
808 memcpy(command_line, saved_command_line, sizeof(command_line));
809 *cmdline_p = &command_line[0];
810 parse_cmdline_early(command_line);
811
812 /* set up the memory description
813 * - by now the stack is part of the init task */
814 printk("Memory %08lx-%08lx\n", memory_start, memory_end);
815
816 BUG_ON(memory_start == memory_end);
817
818 init_mm.start_code = (unsigned long) &_stext;
819 init_mm.end_code = (unsigned long) &_etext;
820 init_mm.end_data = (unsigned long) &_edata;
821 #if 0 /* DAVIDM - don't set brk just incase someone decides to use it */
822 init_mm.brk = (unsigned long) &_end;
823 #else
824 init_mm.brk = (unsigned long) 0;
825 #endif
826
827 #ifdef DEBUG
828 printk("KERNEL -> TEXT=0x%06x-0x%06x DATA=0x%06x-0x%06x BSS=0x%06x-0x%06x\n",
829 (int) &_stext, (int) &_etext,
830 (int) &_sdata, (int) &_edata,
831 (int) &_sbss, (int) &_ebss);
832 #endif
833
834 #ifdef CONFIG_VT
835 #if defined(CONFIG_VGA_CONSOLE)
836 conswitchp = &vga_con;
837 #elif defined(CONFIG_DUMMY_CONSOLE)
838 conswitchp = &dummy_con;
839 #endif
840 #endif
841
842 #ifdef CONFIG_BLK_DEV_BLKMEM
843 ROOT_DEV = MKDEV(BLKMEM_MAJOR,0);
844 #endif
845 /*rom_length = (unsigned long)&_flashend - (unsigned long)&_romvec;*/
846
847 #ifdef CONFIG_MMU
848 setup_linux_memory();
849 #else
850 setup_uclinux_memory();
851 #endif
852
853 /* get kmalloc into gear */
854 paging_init();
855
856 /* init DMA */
857 frv_dma_init();
858 #ifdef DEBUG
859 printk("Done setup_arch\n");
860 #endif
861
862 /* start the decrement timer running */
863 // asm volatile("movgs %0,timerd" :: "r"(10000000));
864 // __set_HSR(0, __get_HSR(0) | HSR0_ETMD);
865
866 } /* end setup_arch() */
867
868 #if 0
869 /*****************************************************************************/
870 /*
871 *
872 */
873 static int __devinit setup_arch_serial(void)
874 {
875 /* register those serial ports that are available */
876 #ifndef CONFIG_GDBSTUB_UART0
877 early_serial_setup(&__frv_uart0);
878 #endif
879 #ifndef CONFIG_GDBSTUB_UART1
880 early_serial_setup(&__frv_uart1);
881 #endif
882
883 return 0;
884 } /* end setup_arch_serial() */
885
886 late_initcall(setup_arch_serial);
887 #endif
888
889 /*****************************************************************************/
890 /*
891 * set up the memory map for normal MMU linux
892 */
893 #ifdef CONFIG_MMU
894 static void __init setup_linux_memory(void)
895 {
896 unsigned long bootmap_size, low_top_pfn, kstart, kend, high_mem;
897
898 kstart = (unsigned long) &__kernel_image_start - PAGE_OFFSET;
899 kend = (unsigned long) &__kernel_image_end - PAGE_OFFSET;
900
901 kstart = kstart & PAGE_MASK;
902 kend = (kend + PAGE_SIZE - 1) & PAGE_MASK;
903
904 /* give all the memory to the bootmap allocator, tell it to put the
905 * boot mem_map immediately following the kernel image
906 */
907 bootmap_size = init_bootmem_node(NODE_DATA(0),
908 kend >> PAGE_SHIFT, /* map addr */
909 memory_start >> PAGE_SHIFT, /* start of RAM */
910 memory_end >> PAGE_SHIFT /* end of RAM */
911 );
912
913 /* pass the memory that the kernel can immediately use over to the bootmem allocator */
914 max_mapnr = num_physpages = (memory_end - memory_start) >> PAGE_SHIFT;
915 low_top_pfn = (KERNEL_LOWMEM_END - KERNEL_LOWMEM_START) >> PAGE_SHIFT;
916 high_mem = 0;
917
918 if (num_physpages > low_top_pfn) {
919 #ifdef CONFIG_HIGHMEM
920 high_mem = num_physpages - low_top_pfn;
921 #else
922 max_mapnr = num_physpages = low_top_pfn;
923 #endif
924 }
925 else {
926 low_top_pfn = num_physpages;
927 }
928
929 min_low_pfn = memory_start >> PAGE_SHIFT;
930 max_low_pfn = low_top_pfn;
931 max_pfn = memory_end >> PAGE_SHIFT;
932
933 num_mappedpages = low_top_pfn;
934
935 printk(KERN_NOTICE "%ldMB LOWMEM available.\n", low_top_pfn >> (20 - PAGE_SHIFT));
936
937 free_bootmem(memory_start, low_top_pfn << PAGE_SHIFT);
938
939 #ifdef CONFIG_HIGHMEM
940 if (high_mem)
941 printk(KERN_NOTICE "%ldMB HIGHMEM available.\n", high_mem >> (20 - PAGE_SHIFT));
942 #endif
943
944 /* take back the memory occupied by the kernel image and the bootmem alloc map */
945 reserve_bootmem(kstart, kend - kstart + bootmap_size);
946
947 /* reserve the memory occupied by the initial ramdisk */
948 #ifdef CONFIG_BLK_DEV_INITRD
949 if (LOADER_TYPE && INITRD_START) {
950 if (INITRD_START + INITRD_SIZE <= (low_top_pfn << PAGE_SHIFT)) {
951 reserve_bootmem(INITRD_START, INITRD_SIZE);
952 initrd_start = INITRD_START ? INITRD_START + PAGE_OFFSET : 0;
953 initrd_end = initrd_start + INITRD_SIZE;
954 }
955 else {
956 printk(KERN_ERR
957 "initrd extends beyond end of memory (0x%08lx > 0x%08lx)\n"
958 "disabling initrd\n",
959 INITRD_START + INITRD_SIZE,
960 low_top_pfn << PAGE_SHIFT);
961 initrd_start = 0;
962 }
963 }
964 #endif
965
966 } /* end setup_linux_memory() */
967 #endif
968
969 /*****************************************************************************/
970 /*
971 * set up the memory map for uClinux
972 */
973 #ifndef CONFIG_MMU
974 static void __init setup_uclinux_memory(void)
975 {
976 #ifdef CONFIG_PROTECT_KERNEL
977 unsigned long dampr;
978 #endif
979 unsigned long kend;
980 int bootmap_size;
981
982 kend = (unsigned long) &__kernel_image_end;
983 kend = (kend + PAGE_SIZE - 1) & PAGE_MASK;
984
985 /* give all the memory to the bootmap allocator, tell it to put the
986 * boot mem_map immediately following the kernel image
987 */
988 bootmap_size = init_bootmem_node(NODE_DATA(0),
989 kend >> PAGE_SHIFT, /* map addr */
990 memory_start >> PAGE_SHIFT, /* start of RAM */
991 memory_end >> PAGE_SHIFT /* end of RAM */
992 );
993
994 /* free all the usable memory */
995 free_bootmem(memory_start, memory_end - memory_start);
996
997 high_memory = (void *) (memory_end & PAGE_MASK);
998 max_mapnr = num_physpages = ((unsigned long) high_memory - PAGE_OFFSET) >> PAGE_SHIFT;
999
1000 min_low_pfn = memory_start >> PAGE_SHIFT;
1001 max_low_pfn = memory_end >> PAGE_SHIFT;
1002 max_pfn = max_low_pfn;
1003
1004 /* now take back the bits the core kernel is occupying */
1005 #ifndef CONFIG_PROTECT_KERNEL
1006 reserve_bootmem(kend, bootmap_size);
1007 reserve_bootmem((unsigned long) &__kernel_image_start,
1008 kend - (unsigned long) &__kernel_image_start);
1009
1010 #else
1011 dampr = __get_DAMPR(0);
1012 dampr &= xAMPRx_SS;
1013 dampr = (dampr >> 4) + 17;
1014 dampr = 1 << dampr;
1015
1016 reserve_bootmem(__get_DAMPR(0) & xAMPRx_PPFN, dampr);
1017 #endif
1018
1019 /* reserve some memory to do uncached DMA through if requested */
1020 #ifdef CONFIG_RESERVE_DMA_COHERENT
1021 if (dma_coherent_mem_start)
1022 reserve_bootmem(dma_coherent_mem_start,
1023 dma_coherent_mem_end - dma_coherent_mem_start);
1024 #endif
1025
1026 } /* end setup_uclinux_memory() */
1027 #endif
1028
1029 /*****************************************************************************/
1030 /*
1031 * get CPU information for use by procfs
1032 */
1033 static int show_cpuinfo(struct seq_file *m, void *v)
1034 {
1035 const char *gr, *fr, *fm, *fp, *cm, *nem, *ble;
1036 #ifdef CONFIG_PM
1037 const char *sep;
1038 #endif
1039
1040 gr = cpu_hsr0_all & HSR0_GRHE ? "gr0-63" : "gr0-31";
1041 fr = cpu_hsr0_all & HSR0_FRHE ? "fr0-63" : "fr0-31";
1042 fm = cpu_psr_all & PSR_EM ? ", Media" : "";
1043 fp = cpu_psr_all & PSR_EF ? ", FPU" : "";
1044 cm = cpu_psr_all & PSR_CM ? ", CCCR" : "";
1045 nem = cpu_psr_all & PSR_NEM ? ", NE" : "";
1046 ble = cpu_psr_all & PSR_BE ? "BE" : "LE";
1047
1048 seq_printf(m,
1049 "CPU-Series:\t%s\n"
1050 "CPU-Core:\t%s, %s, %s%s%s\n"
1051 "CPU:\t\t%s\n"
1052 "MMU:\t\t%s\n"
1053 "FP-Media:\t%s%s%s\n"
1054 "System:\t\t%s",
1055 cpu_series,
1056 cpu_core, gr, ble, cm, nem,
1057 cpu_silicon,
1058 cpu_mmu,
1059 fr, fm, fp,
1060 cpu_system);
1061
1062 if (cpu_board1)
1063 seq_printf(m, ", %s", cpu_board1);
1064
1065 if (cpu_board2)
1066 seq_printf(m, ", %s", cpu_board2);
1067
1068 seq_printf(m, "\n");
1069
1070 #ifdef CONFIG_PM
1071 seq_printf(m, "PM-Controls:");
1072 sep = "\t";
1073
1074 if (clock_bits_settable & CLOCK_BIT_CMODE) {
1075 seq_printf(m, "%scmode=0x%04hx", sep, clock_cmodes_permitted);
1076 sep = ", ";
1077 }
1078
1079 if (clock_bits_settable & CLOCK_BIT_CM) {
1080 seq_printf(m, "%scm=0x%lx", sep, clock_bits_settable & CLOCK_BIT_CM);
1081 sep = ", ";
1082 }
1083
1084 if (clock_bits_settable & CLOCK_BIT_P0) {
1085 seq_printf(m, "%sp0=0x3", sep);
1086 sep = ", ";
1087 }
1088
1089 seq_printf(m, "%ssuspend=0x22\n", sep);
1090 #endif
1091
1092 seq_printf(m,
1093 "PM-Status:\tcmode=%d, cm=%d, p0=%d\n",
1094 clock_cmode_current, clock_cm_current, clock_p0_current);
1095
1096 #define print_clk(TAG, VAR) \
1097 seq_printf(m, "Clock-" TAG ":\t%lu.%2.2lu MHz\n", VAR / 1000000, (VAR / 10000) % 100)
1098
1099 print_clk("In", __clkin_clock_speed_HZ);
1100 print_clk("Core", __core_clock_speed_HZ);
1101 print_clk("SDRAM", __sdram_clock_speed_HZ);
1102 print_clk("CBus", __core_bus_clock_speed_HZ);
1103 print_clk("Res", __res_bus_clock_speed_HZ);
1104 print_clk("Ext", __ext_bus_clock_speed_HZ);
1105 print_clk("DSU", __dsu_clock_speed_HZ);
1106
1107 seq_printf(m,
1108 "BogoMips:\t%lu.%02lu\n",
1109 (loops_per_jiffy * HZ) / 500000, ((loops_per_jiffy * HZ) / 5000) % 100);
1110
1111 return 0;
1112 } /* end show_cpuinfo() */
1113
1114 static void *c_start(struct seq_file *m, loff_t *pos)
1115 {
1116 return *pos < NR_CPUS ? (void *) 0x12345678 : NULL;
1117 }
1118
1119 static void *c_next(struct seq_file *m, void *v, loff_t *pos)
1120 {
1121 ++*pos;
1122 return c_start(m, pos);
1123 }
1124
1125 static void c_stop(struct seq_file *m, void *v)
1126 {
1127 }
1128
1129 struct seq_operations cpuinfo_op = {
1130 .start = c_start,
1131 .next = c_next,
1132 .stop = c_stop,
1133 .show = show_cpuinfo,
1134 };
1135
1136 void arch_gettod(int *year, int *mon, int *day, int *hour,
1137 int *min, int *sec)
1138 {
1139 *year = *mon = *day = *hour = *min = *sec = 0;
1140 }
1141
1142 /*****************************************************************************/
1143 /*
1144 *
1145 */
1146 #ifdef CONFIG_MB93090_MB00
1147 static void __init mb93090_sendlcdcmd(uint32_t cmd)
1148 {
1149 unsigned long base = __addr_LCD();
1150 int loop;
1151
1152 /* request reading of the busy flag */
1153 __set_LCD(base, LCD_CMD_READ_BUSY);
1154 __set_LCD(base, LCD_CMD_READ_BUSY & ~LCD_E);
1155
1156 /* wait for the busy flag to become clear */
1157 for (loop = 10000; loop > 0; loop--)
1158 if (!(__get_LCD(base) & 0x80))
1159 break;
1160
1161 /* send the command */
1162 __set_LCD(base, cmd);
1163 __set_LCD(base, cmd & ~LCD_E);
1164
1165 } /* end mb93090_sendlcdcmd() */
1166
1167 /*****************************************************************************/
1168 /*
1169 * write to the MB93090 LEDs and LCD
1170 */
1171 static void __init mb93090_display(void)
1172 {
1173 const char *p;
1174
1175 __set_LEDS(0);
1176
1177 /* set up the LCD */
1178 mb93090_sendlcdcmd(LCD_CMD_CLEAR);
1179 mb93090_sendlcdcmd(LCD_CMD_FUNCSET(1,1,0));
1180 mb93090_sendlcdcmd(LCD_CMD_ON(0,0));
1181 mb93090_sendlcdcmd(LCD_CMD_HOME);
1182
1183 mb93090_sendlcdcmd(LCD_CMD_SET_DD_ADDR(0));
1184 for (p = mb93090_banner; *p; p++)
1185 mb93090_sendlcdcmd(LCD_DATA_WRITE(*p));
1186
1187 mb93090_sendlcdcmd(LCD_CMD_SET_DD_ADDR(64));
1188 for (p = mb93090_version; *p; p++)
1189 mb93090_sendlcdcmd(LCD_DATA_WRITE(*p));
1190
1191 } /* end mb93090_display() */
1192
1193 #endif // CONFIG_MB93090_MB00
Linux kernel - Deliverables
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