arch/frv/lib/atomic64-ops.S

   1 /* kernel atomic64 operations
   2  *
   3  * For an explanation of how atomic ops work in this arch, see:
   4  *   Documentation/frv/atomic-ops.txt
   5  *
   6  * Copyright (C) 2009 Red Hat, Inc. All Rights Reserved.
   7  * Written by David Howells (dhowells@redhat.com)
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License
  11  * as published by the Free Software Foundation; either version
  12  * 2 of the License, or (at your option) any later version.
  13  */
  14
  15 #include <asm/spr-regs.h>
  16
  17         .text
  18         .balign 4
  19
  20
  21 ###############################################################################
  22 #
  23 # uint64_t __xchg_64(uint64_t i, uint64_t *v)
  24 #
  25 ###############################################################################
  26         .globl          __xchg_64
  27         .type           __xchg_64,@function
  28 __xchg_64:
  29         or.p            gr8,gr8,gr4
  30         or              gr9,gr9,gr5
  31 0:
  32         orcc            gr0,gr0,gr0,icc3                /* set ICC3.Z */
  33         ckeq            icc3,cc7
  34         ldd.p           @(gr10,gr0),gr8                 /* LDD.P/ORCR must be atomic */
  35         orcr            cc7,cc7,cc3                     /* set CC3 to true */
  36         cstd.p          gr4,@(gr10,gr0)         ,cc3,#1
  37         corcc           gr29,gr29,gr0           ,cc3,#1 /* clear ICC3.Z if store happens */
  38         beq             icc3,#0,0b
  39         bralr
  40
  41         .size           __xchg_64, .-__xchg_64
  42
  43 ###############################################################################
  44 #
  45 # uint64_t __cmpxchg_64(uint64_t test, uint64_t new, uint64_t *v)
  46 #
  47 ###############################################################################
  48         .globl          __cmpxchg_64
  49         .type           __cmpxchg_64,@function
  50 __cmpxchg_64:
  51         or.p            gr8,gr8,gr4
  52         or              gr9,gr9,gr5
  53 0:
  54         orcc            gr0,gr0,gr0,icc3                /* set ICC3.Z */
  55         ckeq            icc3,cc7
  56         ldd.p           @(gr12,gr0),gr8                 /* LDD.P/ORCR must be atomic */
  57         orcr            cc7,cc7,cc3
  58         subcc           gr8,gr4,gr0,icc0
  59         subcc.p         gr9,gr5,gr0,icc1
  60         bnelr           icc0,#0
  61         bnelr           icc1,#0
  62         cstd.p          gr10,@(gr12,gr0)        ,cc3,#1
  63         corcc           gr29,gr29,gr0           ,cc3,#1 /* clear ICC3.Z if store happens */
  64         beq             icc3,#0,0b
  65         bralr
  66
  67         .size           __cmpxchg_64, .-__cmpxchg_64
  68